Semiconductor device and semiconductor module

Abstract

The present invention provides a semiconductor device capable of adopting a stacked structure and suppressing high-frequency interference. A first electronic circuit including a semiconductor element is formed in a first component. A second component is bonded to a portion of a first surface of the first component. The second component includes a second electronic circuit including a semiconductor element made of a semiconductor material different from that of the semiconductor element of the first electronic circuit. An interlayer insulating film covers the area of ​​the first surface of the first component not bonded to the second component, as well as the second component. Inter-component connection wiring arranged on the interlayer insulating film connects the first electronic circuit to the second electronic circuit through an opening provided in the interlayer insulating film. A shielding structure including a first metal pattern arranged on the interlayer insulating film shields the shielded circuit, which is part of the first electronic circuit, from high frequencies.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a semiconductor module. Background Art

[0002] Electronic devices used in mobile communications, satellite communications, and other applications are equipped with RF front-end modules that integrate high-frequency signal transmission and reception functions. These modules include a monolithic microwave integrated circuit (MMIC) with high-frequency amplification, a control IC that controls the high-frequency amplifier circuit, a switch IC, and a duplexer.

[0003] To achieve miniaturization of RF front-end modules, a structure in which a control IC is stacked on top of an MMIC is known. Furthermore, Patent Document 1 below discloses a semiconductor device in which a redistribution layer is formed on a lower semiconductor chip and flip-chip bonded to the upper semiconductor chip on this redistribution layer. The lower semiconductor chip is mounted on a module substrate, and the redistribution layer and the module substrate are electrically connected via bonding wires.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-151644

[0005] In a structure in which a control IC is stacked on an MMIC, unnecessary high-frequency interference is likely to occur between the high-frequency circuit formed in the MMIC and the electronic circuits on the module substrate and the electronic circuits formed in the control IC. Summary of the Invention

[0006] An object of the present invention is to provide a semiconductor device that can adopt a stacked structure and can suppress high-frequency interference.

[0007] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0008] a first component forming a first electronic circuit including a semiconductor element;

[0009] a second member bonded to a portion of the first surface, which is one surface of the first member, and forming a second electronic circuit, the second electronic circuit including a semiconductor element made of a semiconductor material different from that of the semiconductor element of the first electronic circuit;

[0010] an interlayer insulating film covering a region of the first surface not bonded to the second member and the second member;

[0011] an inter-component connection wiring arranged on the interlayer insulating film and connecting the first electronic circuit and the second electronic circuit via an opening provided in the interlayer insulating film; and

[0012] The shield structure includes a first metal pattern disposed on the interlayer insulating film and shields a shielded circuit that is a part of the first electronic circuit at high frequencies.

[0013] According to another aspect of the present invention, there is provided a semiconductor module comprising:

[0014] module baseboard; and

[0015] A semiconductor device mounted on the mounting surface of the module substrate,

[0016] The semiconductor device includes:

[0017] a first component forming a first electronic circuit including a semiconductor element;

[0018] a second member bonded to a portion of the first surface, which is one surface of the first member, and forming a second electronic circuit, the second electronic circuit including a semiconductor element made of a semiconductor material different from that of the semiconductor element of the first electronic circuit;

[0019] an interlayer insulating film covering the first surface and the second component;

[0020] inter-component connection wiring, arranged on the interlayer insulating film, connecting the first electronic circuit and the second electronic circuit via an opening provided in the interlayer insulating film;

[0021] a shielding structure including a first metal pattern disposed on the interlayer insulating film and shielding a shielded circuit that is a part of the first electronic circuit at high frequencies;

[0022] a first conductive protrusion protruding from the first metal pattern; and

[0023] The second conductor protrusion is provided on the surface of the second component facing the module substrate and is connected to the ground line of the second electronic circuit.

[0024] The module substrate includes:

[0025] grounding conductor; and

[0026] The first pad and the second pad are connected to the ground conductor.

[0027] The first pad and the second pad are connected to the first conductive protrusion and the second conductive protrusion, respectively.

[0028] The shielded circuit is shielded at high frequencies by the shielding structure, so high-frequency interference between the second electronic circuit of the second component and the shielded circuit can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a diagram showing the planar positional relationship of the components of the semiconductor device according to the first embodiment.

[0030] Figure 2 It is a diagram schematically showing the cross-sectional structure of the semiconductor device according to the first embodiment.

[0031] Figure 3A is an equivalent circuit diagram of one unit constituting the power stage amplifier circuit formed in the second component, Figure 3B This is a cross-sectional view of one unit constituting the power stage amplifier circuit formed in the second member.

[0032] Figure 4 FIG. 1 is a schematic diagram showing a cross-sectional structure of a semiconductor module including the semiconductor device according to the first embodiment and a module substrate.

[0033] Figures 5A to 5F The accompanying drawing is a cross-sectional view of a semiconductor device at an intermediate stage of manufacture.

[0034] Figures 6A to 6C The accompanying drawing is a cross-sectional view of a semiconductor device at an intermediate stage of manufacture, Figure 6D is a cross-sectional view of a completed semiconductor device.

[0035] Figure 7 FIG2 is a schematic diagram showing a cross-sectional structure of a semiconductor module according to a second embodiment.

[0036] Figure 8 It is a diagram showing the planar positional relationship of components of the semiconductor device according to the third embodiment.

[0037] Figure 9 It is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a third embodiment.

[0038] Figure 10 It is a diagram showing the planar positional relationship of components of the semiconductor device according to the fourth embodiment.

[0039] Figure 11 It is a diagram schematically showing a cross-sectional structure of a semiconductor device according to a fourth embodiment.

[0040] Figure 12 FIG. 4 is a diagram schematically showing a cross-sectional structure of a semiconductor module including a semiconductor device and a module substrate according to a fourth embodiment.

[0041] Figure 13 It is a diagram showing the planar positional relationship of the components of the semiconductor device according to the fifth embodiment.

[0042] Figure 14 It is a diagram schematically showing the cross-sectional structure of a semiconductor device according to a fifth embodiment.

[0043] Figure 15 FIG. 5 is a diagram schematically showing a cross-sectional structure of a semiconductor module including a semiconductor device according to a fifth embodiment and a module substrate.

[0044] Figure 16A as well as Figure 16B These are a diagram showing the positional relationship of components of the semiconductor module according to the sixth embodiment in a plan view and a diagram schematically showing a cross-sectional structure.

[0045] Figure 17 This is an enlarged view of the cross-sectional structure of a portion where a semiconductor device is mounted in a semiconductor module according to a sixth embodiment.

[0046] Figure 18 It is a diagram showing the positional relationship of components of a semiconductor module according to a modification of the sixth embodiment in a plan view.

[0047] Explanation of Reference Numerals: 20…semiconductor device, 30…first component, 30A…first surface, 31…control circuit, 32…shielded circuit, 33…input switch, 35…solder pad, 40…second component, 41…bias circuit, 42…higher harmonic termination circuit, 43…driver-stage amplifier circuit, 44…input matching circuit, 45…inter-stage matching circuit, 46…power-stage amplifier circuit, 50…interlayer insulating film, 51A, 51B, 51C…vias, 55…protective film, 60…first metal pattern, 60P… Solder pad, 61…Inter-component connection wiring, 62…Solder pad, 63A, 63B…Opening, 65A…First conductor protrusion, 65B…Second conductor protrusion, 65C…Third conductor protrusion, 65D…Fourth conductor protrusion, 66…Metal wire, 70…Solder, 81…Output matching circuit, 82…Band select switch, 83…Duplexer, 84…Low-noise amplifier, 85…Antenna switch, 90…Resin component, 91…Metal shielding film, 92…Shielding wall, 100…Module substrate, 110A…First solder pad, 110B ...second pad, 110C...third pad, 110D...fourth pad, 115...ground plane, 116...ground via, 200...motherboard, 201...peeling layer, 202...element formation layer, 204...connection support, 210...substrate, 301...substrate, 302...multilayer wiring structure, 302C...metal region, 311...second metal pattern, 312...via, 401...base semiconductor layer, 401A...conductive region, 401B...element isolation region, 402...transistor, 402 B…base layer, 402C…collector layer, 402E…emitter layer, 403B…base electrode, 403C…collector electrode, 403E…emitter electrode, 404B…first-layer base wiring, 404BB…base bias wiring, 404C…first-layer collector wiring, 404E…first-layer emitter wiring, 405E…second-layer emitter wiring, 405RF…high-frequency signal input wiring, 406…first-layer interlayer insulating film, 407…second-layer interlayer insulating film, 408…third-layer interlayer insulating film. DETAILED DESCRIPTION

[0048] [First embodiment]

[0049] Reference Figures 1 to 6D The semiconductor device of the first embodiment is described with reference to the accompanying drawings.

[0050] Figure 1This figure shows the planar positional relationship of the components of the semiconductor device 20 of the first embodiment. The second component 40 is bonded to the surface of the first component 30 in surface contact. The surface of the first component 30 to which the second component 40 is bonded is referred to as the first surface 30A. When viewed from above, the second component 40 is contained within the first component 30. For example, the first component 30 is composed of a single semiconductor, and the second component 40 is composed of a compound semiconductor.

[0051] The first component 30 includes a semiconductor substrate of a single semiconductor type and a first electronic circuit formed on the semiconductor substrate. For example, a single crystal substrate composed of a single semiconductor such as silicon or a silicon-on-insulator (SOI) substrate can be used as the semiconductor substrate. The first electronic circuit includes semiconductor elements such as single semiconductor types, such as MOSFETs and bipolar transistors. The first electronic circuit includes a control circuit 31, a shielded circuit 32, and an input switch 33. A portion of the region where the input switch 33 is formed overlaps with the second component 40 when viewed from above.

[0052] The shielded circuit 32 is a circuit that may become a source of spurious signals or a circuit that is easily affected by interference noise. For example, a charge pump can be cited as an example of a circuit that may become a source of spurious signals. A low-noise amplifier can be cited as an example of a circuit that is easily affected by interference noise. Figure 1 In FIG. 1 , regions forming various circuits included in the first electronic circuit are shown surrounded by dotted lines.

[0053] The second component 40 is bonded to a region of the first surface 30A of the first component 30 that does not overlap with the shielded circuit 32 when viewed from above. The second component 40 includes a base semiconductor layer composed of a compound semiconductor layer and a second electronic circuit formed thereon. The second electronic circuit includes a heterojunction bipolar transistor (HBT), passive components, and the like. The semiconductor components included in the second electronic circuit are formed of a semiconductor material different from that of the semiconductor components included in the first electronic circuit.

[0054] The second electronic circuit includes a bias circuit 41, a high-order harmonic termination circuit 42, a driver stage amplifier circuit 43, an input matching circuit 44, an inter-stage matching circuit 45, and a power stage amplifier circuit 46. Figure 1 In FIG. 1 , regions forming various circuits included in the second electronic circuit are shown surrounded by dotted lines.

[0055] A rewiring layer is arranged in a region overlapping the first component 30 and the second component 40 in a plan view. The rewiring layer includes a first metal pattern 60 and a plurality of inter-component connection wirings 61. Figure 1In the figure, hatching is applied to the first metal pattern 60 and the plurality of inter-component connection wirings 61. The first metal pattern 60 is a metal film that includes the shielded circuit 32 when viewed from above. The plurality of inter-component connection wirings 61 connect the first electronic circuit formed in the first component 30 with the second electronic circuit formed in the second component 40 through an opening 63A in the interlayer insulating film provided below the redistribution layer. For example, two inter-component connection wirings 61 connect the control circuit 31 formed in the first component 30 with the bias circuit 41 formed in the second component 40. Another inter-component connection wiring 61 connects the input switch 33 formed in the first component 30 with the input matching circuit 44 formed in the second component 40.

[0056] In a plan view, a plurality of openings 63B penetrating the interlayer insulating film below the rewiring layer in the thickness direction are provided in a region included in the first metal pattern 60. The first metal pattern 60 reaches the first member 30 through these openings 63B.

[0057] Multiple conductor protrusions, including multiple first conductor protrusions 65A, multiple second conductor protrusions 65B, multiple third conductor protrusions 65C, and multiple fourth conductor protrusions 65D, protrude from the redistribution layer. These conductor protrusions are electrically connected to the first electronic circuit or the second electronic circuit. The first conductor protrusion 65A is connected to the first metal pattern 60. The second conductor protrusion 65B and the fourth conductor protrusion 65D are connected to the ground line of the second electronic circuit. The third conductor protrusion 65C is connected to the output port of the power stage amplifier circuit 46. In place of the multiple fourth conductor protrusions 65D, a strip-shaped conductor protrusion that is elongated in one direction when viewed from above may be provided. Similarly, in place of the multiple third conductor protrusions 65C, a strip-shaped conductor protrusion may be provided.

[0058] Next, the functions of the first and second electronic circuits will be described. Input switch 33 selects one of multiple input ports. The high-frequency signal input to the input port selected by input switch 33 is input to driver-stage amplifier circuit 43 via input matching circuit 44. The high-frequency signal amplified by driver-stage amplifier circuit 43 is input to power-stage amplifier circuit 46 via inter-stage matching circuit 45. The high-frequency signal amplified by power-stage amplifier circuit 46 is output externally. Here, the external circuit refers to, for example, an electronic circuit provided on the module substrate on which semiconductor device 20 is mounted.

[0059] The high-frequency signal output to the outside is supplied to the antenna and radiated from the antenna as radio waves. The harmonic termination circuit 42 functions as an impedance matching circuit for the high-frequency signal output from the power-stage amplifier circuit 46 and terminates unwanted harmonics contained in the high-frequency signal. The bias circuit 41 supplies bias current to the driver-stage amplifier circuit 43 and the power-stage amplifier circuit 46.

[0060] The control circuit 31 controls the bias circuit 41. The charge pump included in the shielded circuit 32 boosts or steps down the externally supplied power supply voltage and supplies it to the first and second electronic circuits. The low-noise amplifier included in the shielded circuit 32 amplifies the received signal received by the antenna.

[0061] Figure 2 1 is a diagram schematically showing a cross-sectional structure of the semiconductor device 20 according to the first embodiment. Figure 2 The diagram does not show a specific cross section of the semiconductor device 20 according to the first embodiment, but instead shows each component with a focus on electrical connections.

[0062] Shielded circuit 32 and input switch 33 are formed on the surface of first surface 30A of first component 30. Furthermore, a plurality of solder pads 35 are provided on first surface 30A. Second component 40 is bonded to first surface 30A of first component 30. Second component 40 is not disposed above the area where shielded circuit 32 is disposed.

[0063] The interlayer insulating film 50 covers the area of ​​the first surface 30A of the first component 30 that is not bonded to the second component 40, as well as the second component 40. The interlayer insulating film 50 is formed of an organic insulating material such as polyimide. A plurality of vias 51A, 51B, and 51C are provided, penetrating the interlayer insulating film 50 in the thickness direction. A rewiring layer is disposed on the interlayer insulating film 50. Inter-component connection wiring 61 included in the rewiring layer connects the input switch 33 to the input matching circuit 44 via the via 51A. The first metal pattern 60 included in the rewiring layer is connected to the pad 35 of the first component 30 via the via 51B.

[0064] Furthermore, a plurality of solder pads 62 are arranged on the interlayer insulating film 50. The plurality of solder pads 62 are connected to the second electronic circuit of the second component 40, such as the inter-stage matching circuit 45 and the power stage amplifier circuit 46, through the via holes 51C. Figure 2 Although not shown, a portion of the solder tab 62 is also connected to the first electronic circuit of the first component 30, such as the control circuit 31 ( Figure 1 ) and other connections.

[0065] A plurality of first conductor protrusions 65A are arranged on the first metal pattern 60. Furthermore, a second conductor protrusion 65B, a third conductor protrusion 65C, and a fourth conductor protrusion 65D are arranged on each of the plurality of solder tabs 62. Solder 70 is placed on the top surface of each of the first conductor protrusion 65A, the second conductor protrusion 65B, the third conductor protrusion 65C, and the fourth conductor protrusion 65D. These conductor protrusions are formed, for example, of copper. A structure in which a solder layer is placed on the top surface of a conductor protrusion made of copper is called a "Cu pillar bump." Furthermore, a protrusion having a structure in which no solder is placed, such as an Au bump, can be used as a conductor protrusion. A protrusion having such a structure is also called a "pillar." Furthermore, a protrusion having a structure in which a conductor pillar is erected on a solder tab can be used as a conductor protrusion. A conductor protrusion having such a structure is also called a "pillar." Furthermore, a ball bump formed by reflowing solder into a ball shape can be used as a conductor protrusion. In addition to these various protrusion structures, protrusions having various structures including a conductor protruding from a substrate can also be used as conductor protrusions. In addition, Figure 2 In the figure, description of the protective film covering the first metal pattern 60 and the inter-component connection wiring 61 is omitted.

[0066] Figure 3A The power stage amplifier circuit 46 ( Figure 1 ). Power stage amplifier circuit 46 includes multiple units connected in parallel. Each unit includes a transistor 402, an input capacitor Cin, and a ballast resistor Rb. The base of transistor 402 is connected to high-frequency signal input wiring 405RF via input capacitor Cin. Furthermore, the base of transistor 402 is connected to base bias wiring 404BB via ballast resistor Rb. The emitter of transistor 402 is grounded. A power supply voltage is applied to the collector of transistor 402, and the amplified high-frequency signal is output from the collector.

[0067] Figure 3B This is a cross-sectional view of a unit constituting the power stage amplifier circuit 46 formed in the second component 40. The first component 30 includes a substrate 301 having a semiconductor region such as a silicon substrate or an SOI substrate, and a multilayer wiring structure 302 arranged thereon. Figure 3B Although not shown, the control circuit 31, the shielded circuit 32, the input switch 33 ( Figure 1 ) etc. A protective film may also be provided to cover the surface of the multilayer wiring structure 302. In this case, the second component 40 is bonded to the first component 30 by making surface contact with the surface of the protective film.

[0068] The second component 40 includes a base semiconductor layer 401. The base semiconductor layer 401 is in surface contact with the first component 30, thereby bonding the second component 40 to the first component 30. The base semiconductor layer 401 is divided into a conductive region 401A and an element isolation region 401B. The base semiconductor layer 401 is made of, for example, GaAs. The conductive region 401A is formed of n-type GaAs, while the element isolation region 401B is formed by ion implanting insulating impurities into the n-type GaAs layer.

[0069] Transistor 402 is disposed on conductive region 401A. Transistor 402 includes a collector layer 402C, a base layer 402B, and an emitter layer 402E, stacked sequentially from conductive region 401A. Emitter layer 402E is disposed on a portion of base layer 402B. As an example, collector layer 402C is formed of n-type GaAs, base layer 402B is formed of p-type GaAs, and emitter layer 402E is formed of n-type InGaP. In other words, transistor 402 is a heterojunction bipolar transistor.

[0070] A base electrode 403B is disposed on the base layer 402B and is electrically connected to the base layer 402B. An emitter electrode 403E is disposed on the emitter layer 402E and is electrically connected to the emitter layer 402E. A collector electrode 403C is disposed on the conductive region 401A and is electrically connected to the collector layer 402C via the conductive region 401A.

[0071] A first interlayer insulating film 406 is disposed on the base semiconductor layer 401 to cover the transistor 402, the base electrode 403B, the emitter electrode 403E, and the collector electrode 403C. The first interlayer insulating film 406 is formed of an inorganic insulating material such as SiN. A plurality of openings are provided in the interlayer insulating film 406.

[0072] A first-layer emitter wiring 404E, a collector wiring 404C, a base wiring 404B, a base bias wiring 404BB, and a ballast resistor Rb are arranged on the interlayer insulating film 406. Emitter wiring 404E is connected to emitter electrode 403E via an opening provided in the interlayer insulating film 406. Collector wiring 404C is connected to collector electrode 403C via another opening provided in the interlayer insulating film 406. Base wiring 404B is connected to base electrode 403B via another opening provided in the interlayer insulating film 406.

[0073] Base wiring 404B extends to an area where transistor 402 is not located, with its tip overlapping one end of ballast resistor Rb. In the overlapping portion, base wiring 404B is electrically connected to ballast resistor Rb. The other end of ballast resistor Rb overlaps with base bias wiring 404BB. In the overlapping portion, ballast resistor Rb is electrically connected to base bias wiring 404BB.

[0074] A second interlayer insulating film 407 is provided on the interlayer insulating film 406 to cover the first-layer emitter wiring 404E, collector wiring 404C, base wiring 404B, ballast resistor Rb, and base bias wiring 404BB. The second interlayer insulating film 407 is also formed of an inorganic insulating material such as SiN.

[0075] A second-layer emitter wiring 405E and a high-frequency signal input wiring 405RF are arranged on the second-layer interlayer insulating film 407. The second-layer emitter wiring 405E is connected to the first-layer emitter wiring 404E through an opening provided in the second-layer interlayer insulating film 407. A portion of the high-frequency signal input wiring 405RF overlaps with the first-layer base wiring 404B in a plan view. The overlapping region forms an input capacitor Cin.

[0076] The third interlayer insulating film 408 is arranged to cover the second-layer emitter wiring 405E and the high-frequency signal input wiring 405RF. The third interlayer insulating film 408 is formed of an organic insulating material such as polyimide.

[0077] Figure 4 This is a schematic diagram showing the cross-sectional structure of a semiconductor module including the semiconductor device 20 and module substrate 100 of the first embodiment. The semiconductor device 20 is flip-chip mounted upside down on the mounting surface of the module substrate 100. Multiple pads, including a first pad 110A, a second pad 110B, and a third pad 110C, are arranged on the mounting surface of the module substrate 100. A ground conductor 117 is provided on the module substrate 100. Ground conductor 117 includes a multilayer ground plane 115 arranged on an inner layer of the module substrate 100 and on the lower surface opposite the mounting surface, and a plurality of ground vias 116 interconnecting the multilayer ground planes 115. Ground conductor 117 is connected to first pad 110A and second pad 110B.

[0078] Ground plane 115 connected to first pad 110A and ground plane 115 connected to second pad 110B are separated from each other in the inner layer of module substrate 100. Ground plane 115 disposed on the lower surface of module substrate 100 is continuous from the portion connected to first pad 110A to the portion connected to second pad 110B.

[0079] The first conductive protrusion 65A of the semiconductor device 20 is fixed to the first pad 110A via solder 70 and electrically connected thereto. The second conductive protrusion 65B and the fourth conductive protrusion 65D are fixed to the second pad 110B via solder 70 and electrically connected thereto. The third conductive protrusion 65C is fixed to the third pad 110C via solder 70 and electrically connected thereto. A ground potential is provided to the second electronic circuit formed in the second component 40 via the second conductive protrusion 65B and the fourth conductive protrusion 65D. The first metal pattern 60 is connected to the ground conductor 117 of the module substrate 100 via the first conductive protrusion 65A.

[0080] Next, refer to Figures 5A to 6D The method for manufacturing the semiconductor device 20 according to the first embodiment is described with reference to the accompanying drawings. Figures 5A to 6C FIG is a cross-sectional view of a semiconductor device 20 at an intermediate stage of manufacture. Figure 6D is a cross-sectional view of the completed semiconductor device 20 .

[0081] like Figure 5A As shown, a peeling layer 201 is epitaxially grown on a mother substrate 200 of a single crystal compound semiconductor such as GaAs, and an element formation layer 202 is formed on the peeling layer 201. Figure 2 as well as Figure 3B The element structure of the second component 40 shown in FIG. can be formed by a general semiconductor process. Figure 5A , description is omitted for the element structure formed in the element formation layer 202. At this stage, an element structure corresponding to a plurality of semiconductor devices 20 is formed in the element formation layer 202, but is not separated into individual semiconductor devices 20.

[0082] Next, if Figure 5B As shown, the resist pattern (not shown) is used as an etching mask to etch the element forming layer 202 ( Figure 5A ) and the peeling layer 201 are patterned. At this stage, the element formation layer 202 is separated according to each second component 40.

[0083] Next, if Figure 5C As shown, the connecting support 204 is attached to the separated second components 40. Thus, the plurality of second components 40 are connected to each other via the connecting support 204. Figure 5B The resist pattern used as an etching mask in the patterning process remains, so that the resist pattern is sandwiched between the second component 40 and the connection support body 204.

[0084] Next, if Figure 5DAs shown, the release layer 201 is selectively etched from the mother substrate 200 and the second member 40. As a result, the second member 40 and the connection support 204 are peeled from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor having an etching resistance different from that of either the mother substrate 200 or the second member 40 is used as the release layer 201.

[0085] like Figure 5E As shown, a first electronic circuit ( Figure 2 ), the multilayer wiring structure 302 ( FIG. 3 ), etc. At this stage, the substrate 210 is not separated into the individual semiconductor devices 20 .

[0086] like Figure 5F As shown, the second member 40 is bonded to the substrate 210. The bonding between the second member 40 and the substrate 210 is based on van der Waals bonds or hydrogen bonds. Alternatively, the second member 40 and the substrate 210 may be bonded using electrostatic forces, covalent bonds, eutectic alloy bonds, or the like. For example, if a portion of the surface of the substrate 210 is formed of Au, the second member 40 may be bonded to the Au region by bringing the second member 40 into close contact and applying pressure.

[0087] Next, if Figure 6A As shown, the connection support 204 is peeled off from the second component 40. After the connection support 204 is peeled off, as shown in FIG. Figure 6B As shown, an interlayer insulating film 50 and a rewiring layer are formed on the substrate 210 and the second component 40. The rewiring layer includes inter-component connection wiring 61 and solder pads 62. Figure 6B Although not shown, the redistribution layer also includes a first metal pattern 60 ( Figure 2 ). In addition, Figure 2 In FIG. 5 , the upper surface of the interlayer insulating film 50 is flattened, but in FIG. Figure 6B , an example is shown in which the upper surface of the interlayer insulating film 50 is not planarized.

[0088] Next, if Figure 6C As shown in FIG. 1 , a protective film 55 is formed on the rewiring layer, and a plurality of openings are formed in the protective film 55. The plurality of openings are respectively formed in the configuration Figure 2 The first conductor protrusion 65A, the second conductor protrusion 65B and the third conductor protrusion 65C are shown in the region. Then, the first conductor protrusion 65A, the second conductor protrusion 65B and the third conductor protrusion 65C are formed in these openings and on the protective film 55. Figure 6C Only the third conductor bump 65C is shown. Then, solder 70 is placed on the top surfaces of these conductor bumps and a reflow process is performed.

[0089] Finally, if Figure 6DAs shown, the substrate 210 is cut. Thus, the semiconductor devices 20 are obtained after being singulated. The first part 30 of each of the semiconductor devices 20 after being singulated is larger than the second part 40 when viewed from above. The semiconductor devices 20 after being singulated are flip-chip mounted on the module substrate 100 ( Figure 4 ).

[0090] Next, the excellent effects of the first embodiment will be described.

[0091] In the first embodiment, as Figure 4 As shown, the first metal pattern 60 is connected to the ground conductor 117 of the module substrate 100 via the first conductor protrusion 65A. Therefore, the first metal pattern 60 functions as a shielding structure that shields the shielded circuit 32 at high frequencies. Here, shielding at high frequencies refers to electromagnetic shielding within the radio frequency band. This suppresses high-frequency interference between the shielded circuit 32 and the second electronic circuit formed in the second component 40, other electronic circuits provided on the module substrate 100, and the like.

[0092] Furthermore, in the first embodiment, the ground plane 115 connected to the first pad 110A and the ground plane 115 connected to the second pad 110B are separated from each other on the inner layer of the module substrate 100. These separated inner layer ground planes 115 are connected to each other via the ground plane 115 disposed on the lower surface of the module substrate 100. Consequently, the current path through the ground conductor 117 from the first pad 110A to the second pad 110B is longer. This suppresses the transmission of high-frequency noise between the ground of the second electronic circuit of the second component 40 and the first metal pattern 60. This enhances the effectiveness of shielding the shielded circuit 32 at high frequencies. Furthermore, since the first pad 110A and the second pad 110B are connected to each other via the ground plane 115 on the lower surface of the module substrate 100, they maintain the same DC potential.

[0093] Furthermore, in the first embodiment, the first metal pattern 60 ( Figure 1 、 Figure 2 ) is included in the rewiring layer where the inter-component connection wiring 61 is arranged, so the shielding structure can be formed without adding a new process.

[0094] Next, a modification of the first embodiment will be described.

[0095] In the first embodiment, a metal film that encompasses the shielded circuit 32 in a plan view is used as the first metal pattern 60. However, the first metal pattern 60 may also have a lattice pattern, a stripe pattern, or the like. Furthermore, in the first embodiment, a single rewiring layer is disposed on the interlayer insulating film 50. However, a plurality of rewiring layers, including two or more, may also be disposed. In this case, the first metal pattern 60 may be disposed on multiple rewiring layers.

[0096] In the first embodiment, as Figure 4 As shown, the ground plane 115 connected to the first pad 110A and the ground plane 115 connected to the second pad 110B are separated from each other in the inner layer of the module substrate 100. As another configuration, the ground plane 115 connected to the first pad 110A and the ground plane 115 connected to the second pad 110B may be separated from each other at a position shallower than the first position in the thickness direction of the module substrate 100 when viewed from the mounting surface, and the ground plane 115 connected to the first pad 110A and the ground plane 115 connected to the second pad 110B may be continuous at a position deeper than the first position.

[0097] [Second embodiment]

[0098] Next, refer to Figure 7 The semiconductor module of the second embodiment is described below. Figures 1 to 6D The same configurations as those of the semiconductor device and semiconductor module of the first embodiment described in the accompanying drawings will be omitted.

[0099] Figure 7 Schematic diagram showing the cross-sectional structure of the semiconductor module of the second embodiment. In the second embodiment, the first component 30 includes a metal region 302C at the interface with the second component 40. The metal region 302C is included in the multilayer wiring structure 302 ( Figure 3B The metal region 302C is electrically connected to the first metal pattern 60 via a via 51B that penetrates the interlayer insulating film 50 in the thickness direction. Since the first metal pattern 60 is electrically connected to the ground conductor 117 of the module substrate 100 via the first conductor protrusion 65A, the metal region 302C is also electrically connected to the ground conductor 117.

[0100] Next, the excellent effects of the second embodiment will be described.

[0101] In the second embodiment, the metal region 302C functions as a shield structure, thereby suppressing the transmission of high-frequency noise from or to the second electronic circuit formed in the second member 40 via the substrate 301. This improves the effect of suppressing high-frequency interference.

[0102] [Third embodiment]

[0103] Next, refer to Figure 8 as well as Figure 9 The semiconductor device of the third embodiment is described below. Figures 1 to 6D The same configurations as those of the semiconductor device and semiconductor module of the first embodiment described in the accompanying drawings will be omitted.

[0104] Figure 8 1 is a diagram showing the planar positional relationship of the components of the semiconductor device 20 of the third embodiment. Figure 1 ), the first metal pattern 60 includes the shielded circuit 32 when viewed from above. In contrast, in the third embodiment, the first metal pattern 60 is arranged between the region where the shielded circuit 32 is arranged, the region where the second electronic circuit formed in the second component 40 is arranged, and the region where the other first electronic circuit formed in the first component 30 is arranged. Furthermore, between the region where the shielded circuit 32 is arranged and the region where the second electronic circuit of the second component 40 is arranged, and between the region where the shielded circuit 32 is arranged and the region where the other first electronic circuit of the first component 30 is arranged, a plurality of openings 63B and conductive holes 51B ( Figure 9 ).

[0105] Figure 9 Schematically showing the cross-sectional structure of the semiconductor device 20 of the third embodiment. A first metal pattern 60 and a plurality of vias 51B are arranged between the second electronic circuit including the input matching circuit 44, the inter-stage matching circuit 45, the power stage amplifier circuit 46, etc. formed in the second component 40 and the shielded circuit 32. The plurality of vias 51B penetrate the interlayer insulating film 50 in the thickness direction and connect the solder pad 35 provided on the first surface of the first component 30 to the first metal pattern 60. The first conductor protrusion 65A protrudes from the first metal pattern 60. The first conductor protrusion 65A is connected to the ground conductor 117 ( Figure 4 ) electrical connection.

[0106] Next, the excellent effects of the third embodiment will be described.

[0107] In the third embodiment, the plurality of vias 51B and the first metal pattern 60 arranged between the area where the shielded circuit 32 is located and the area where the second electronic circuit of the second component is located function as a shielding structure (shielding wall structure). This suppresses high-frequency interference between the shielded circuit 32 and the second electronic circuit of the second component 40. For example, the effect of spurious signals generated in the shielded circuit 32 on the second electronic circuit can be reduced. Conversely, the effect of electromagnetic noise generated in the power stage amplifier circuit 46 on the shielded circuit 32 can be reduced.

[0108] Likewise, it is possible to suppress the shielded circuit 32 from interfering with other first electronic circuits of the first component 30, such as the control circuit 31 ( Figure 8 )、Input switch 33( Figure 8 ) between high-frequency interference.

[0109] [Fourth embodiment]

[0110] Next, refer to Figure 10 、 Figure 11 as well as Figure 12 The semiconductor device of the fourth embodiment is described below. Figures 1 to 6D The same configurations as those of the semiconductor device and semiconductor module of the first embodiment described in the accompanying drawings will be omitted.

[0111] Figure 10 1 is a diagram showing the planar positional relationship of the components of the semiconductor device 20 of the fourth embodiment. Figure 1 ), the first metal pattern 60 includes the shielded circuit 32 when viewed from above. In contrast, in the fourth embodiment, the first metal pattern 60 is arranged in an area that overlaps with the periphery of the area where the shielded circuit 32 is arranged when viewed from above, and outside the area where the shielded circuit 32 is arranged.

[0112] Furthermore, the plurality of metal wires 66 are arranged so as to pass through the area where the shielded circuit 32 is arranged when viewed from above. More specifically, the first metal pattern 60 is covered with a protective film provided with an opening that is included in the first metal pattern 60 when viewed from above. The first metal pattern 60 exposed within the opening provided in the protective film is utilized as a soldering pad 60P for wire bonding. Both ends of each of the plurality of metal wires 66 are soldered to the soldering pad 60P.

[0113] Figure 11 Schematic diagram of the cross-sectional structure of the semiconductor device 20 according to the fourth embodiment. A plurality of metal lines 66 extend from one first metal pattern 60 through the interlayer insulating film 50 and reach other first metal patterns 60. A first conductive protrusion 65A protrudes from at least one first metal pattern 60.

[0114] Figure 12 This figure schematically illustrates the cross-sectional structure of a semiconductor module including the semiconductor device 20 and the module substrate 100 according to the fourth embodiment. The first conductive protrusion 65A is electrically connected to the ground conductor 117 of the module substrate 100. Consequently, a plurality of metal wires 66 are electrically connected to the ground conductor 117 of the module substrate 100 via the first metal pattern 60 and the first conductive protrusion 65A.

[0115] Next, the excellent effects of the fourth embodiment will be described.

[0116] In the fourth embodiment, the plurality of metal wires 66 function as a shielding structure. Thus, similar to the first embodiment, high-frequency interference between the shielded circuit 32 and the second electronic circuit formed in the second component 40 or other electronic circuits provided on the module substrate 100 can be suppressed.

[0117] Furthermore, portions of the plurality of metal wires 66 other than their ends are spaced apart from the surface of the interlayer insulating film 50. Specifically, the plurality of metal wires 66 are located farther from the shielded circuit 32 than the metal pattern provided on the surface of the interlayer insulating film 50. Consequently, the excellent effect of reducing parasitic capacitance between the shielding structure including the plurality of metal wires 66 and the shielded circuit 32 is achieved.

[0118] [Fifth embodiment]

[0119] Next, refer to Figure 13 、 Figure 14 as well as Figure 15 The semiconductor device of the fifth embodiment will be described. Figures 1 to 6D The same configurations as those of the semiconductor device and semiconductor module of the first embodiment described in the accompanying drawings will be omitted.

[0120] Figure 13 1 is a diagram showing the planar positional relationship of the components of the semiconductor device 20 of the fifth embodiment. Figure 1 ), in a plan view, the first metal pattern 60 encompasses the shielded circuit 32. In contrast, in the fifth embodiment, in a plan view, the first metal pattern 60 is disposed around the shielded circuit 32, and the shielded circuit 32 is encompassed by the second metal pattern 311 instead of the first metal pattern 60. The first metal pattern 60 is electrically connected to the second metal pattern 311 via the opening 63B.

[0121] Figure 14 1 is a diagram schematically showing a cross-sectional structure of a semiconductor device 20 according to the fifth embodiment. A second metal pattern 311 is arranged within the multilayer wiring structure 302 of the first member 30 .

[0122] The second metal pattern 311 is electrically connected to the first metal pattern 60 via a via 51B that penetrates the interlayer insulating film 50 in the thickness direction. A first conductive protrusion 65A protrudes from the first metal pattern 60 .

[0123] The inter-component connection wiring 61 is electrically connected to the input switch 33 via a via 51A penetrating the interlayer insulating film 50 in the thickness direction and a via 312 provided in the multilayer wiring structure 302 .

[0124] Figure 15Schematic diagram of the cross-sectional structure of a semiconductor module including the semiconductor device 20 and the module substrate 100 according to the fifth embodiment. The first conductive protrusion 65A is electrically connected to the ground conductor 117 of the module substrate 100. Therefore, the second metal pattern 311 is electrically connected to the ground conductor 117 of the module substrate 100 via the via 51B that penetrates the interlayer insulating film 50 in the thickness direction, the first metal pattern 60, the first conductive protrusion 65A, and the solder 70.

[0125] Next, the excellent effects of the fifth embodiment will be described. In the fifth embodiment, the second metal pattern 311 functions as a shielding structure. When viewed from above, the second metal pattern 311 encompasses the shielded circuit 32. As in the first embodiment, high-frequency interference between the shielded circuit 32 and the second electronic circuit formed in the second component 40, other electronic circuits provided on the module substrate 100, and the like can be suppressed.

[0126] Next, a modification of the fifth embodiment will be described.

[0127] In the fifth embodiment, in a plan view, the second metal pattern 311 encompasses the shielded circuit 32. Alternatively, the second metal pattern 311 may have a lattice or stripe pattern and be arranged so as to overlap the shielded circuit 32 in a plan view. Alternatively, the second metal pattern 311 may be arranged in multiple wiring layers within the multilayer wiring structure 302.

[0128] [Sixth embodiment]

[0129] Next, refer to Figures 16A to 17 The semiconductor module of the sixth embodiment is described with reference to FIG. The semiconductor module of the sixth embodiment is equipped with the semiconductor device ( Figure 1 、 Figure 2 3 ). In addition, instead of the semiconductor device of the first embodiment, a semiconductor device 20 according to any one of the second to fifth embodiments or a modified example thereof may be mounted.

[0130] Figure 16A as well as Figure 16B The following diagrams respectively show the positional relationship of the components of the semiconductor module of the sixth embodiment when viewed from above, and schematically illustrate the cross-sectional structure. A semiconductor device 20, a band selector switch 82, multiple duplexers 83, a low-noise amplifier 84, and an antenna switch 85 are mounted on a module substrate 100. Furthermore, an output matching circuit 81 formed using a wiring pattern or the like is provided on the module substrate 100. Alternatively, the output matching circuit 81 may be formed using an integrated passive device (IPD) or multiple surface-mount components.

[0131] The plurality of electronic components mounted on the module substrate 100 are sealed by a resin member 90. The resin member 90 covers the mounting surface of the module substrate 100, the semiconductor device 20, and other mounted components. The resin member 90 has a top surface facing the same direction as the mounting surface of the module substrate 100, and side surfaces continuous with the top surface. A metal shielding film 91 is formed on the top and side surfaces of the resin member 90, as well as on the side surfaces of the module substrate 100. The end surfaces of the plurality of ground planes 115 provided on the module substrate 100 are exposed on the side surfaces of the module substrate 100. The metal shielding film 91 is connected to the ground planes 115 on the side surfaces of the module substrate 100. The metal shielding film 91 is formed, for example, by sputtering.

[0132] Shielding wall 92 is provided in resin member 90 to surround semiconductor device 20 in a plan view. Shielding wall 92 extends from the top surface of resin member 90 to the mounting surface of module substrate 100 and is electrically connected to metal shielding film 91 and ground conductor 117 of module substrate 100.

[0133] Next, the functions of the electronic components mounted on the module substrate 100 will be described. Figure 1 ) is input to a frequency band selection switch 82. The frequency band selection switch 82 selects one of a plurality of duplexers 83 based on the frequency band to which the input high-frequency signal belongs, and transmits the high-frequency signal to the selected duplexer 83. The high-frequency signal that has passed through the duplexer 83 is output to an external antenna via an antenna switch 85.

[0134] The reception signal received by the antenna is input to a duplexer 83 via an antenna switch 85. The reception signal having passed through the duplexer 83 is amplified by a low noise amplifier 84 and output to the outside.

[0135] Figure 17 This is an enlarged cross-sectional view of the portion of the semiconductor module of the sixth embodiment where the semiconductor device 20 is mounted. In addition to first pads 110A, second pads 110B, and third pads 110C, fourth pads 110D are arranged on the mounting surface of module substrate 100. Fourth pads 110D are connected to ground conductor 117 of module substrate 100. Shielding wall 92 is connected to first pads 110A and fourth pads 110D.

[0136] Next, the excellent effects of the sixth embodiment will be described.

[0137] The metal shielding film 91 and the shielding wall 92 function as a high-frequency shielding structure. Therefore, they can suppress high-frequency interference between the semiconductor device 20 and the outside world, and can also suppress high-frequency interference between other electronic components mounted on the module substrate 100 and the output matching circuit 81 formed on the module substrate 100 and the semiconductor device 20.

[0138] Next, refer to Figure 18 A modification of the sixth embodiment will be described.

[0139] Figure 18 1 is a diagram showing the positional relationship of the components of the semiconductor module according to the modification of the sixth embodiment when viewed from above. Figure 16A ), shielding wall 92 continuously surrounds semiconductor device 20. However, in this modified example, shielding wall 92 intermittently surrounds semiconductor device 20. For example, shielding wall 92 is formed of a plurality of columnar conductive members, such as conductive pins, that penetrate resin member 90 in the thickness direction. The plurality of conductive members are arranged to surround semiconductor device 20 while being spaced apart from each other in a plan view.

[0140] In this manner, even if the shielding wall 92 is configured to intermittently surround the semiconductor device 20 , the effect of suppressing high-frequency interference can be obtained.

[0141] Next, other modified examples of the sixth embodiment will be described.

[0142] In the sixth embodiment, the shielding wall 92 ( Figure 16A ) surrounds the semiconductor device 20 on four sides, but may also surround the semiconductor device 20 on three sides or two sides. For example, the shielding wall 92 may be configured to separate the semiconductor device 20 from other electronic components and electronic circuits mounted on the module substrate 100.

[0143] In the sixth embodiment, a single-sided mounting substrate is used as the module substrate 100, but a double-sided mounting substrate may be used. In addition, at least one of the plurality of duplexers 83 may be replaced with a transmission filter and a reception filter.

[0144] The above-described embodiments are intended to be illustrative. It is naturally possible to substitute or combine components shown in different embodiments. The same functions and effects resulting from the same components in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it is clear that those skilled in the art can make various modifications, improvements, and combinations.

Claims

1. A semiconductor device comprising: a first component forming a first electronic circuit including a semiconductor element; a second member bonded to a portion of the first surface, which is one surface of the first member, and forming a second electronic circuit, the second electronic circuit including a semiconductor element made of a semiconductor material different from that of the semiconductor element of the first electronic circuit; an interlayer insulating film covering a region of the first surface not bonded to the second member and the second member; an inter-component connection wiring arranged on the interlayer insulating film and connecting the first electronic circuit and the second electronic circuit via an opening provided in the interlayer insulating film; and The shield structure includes a first metal pattern disposed on the interlayer insulating film and shields a shielded circuit that is a part of the first electronic circuit at high frequencies.

2. The semiconductor device according to claim 1, wherein The device further includes a first conductive protrusion protruding from the first metal pattern.

3. The semiconductor device according to claim 1 or 2, wherein: The shielding structure further includes a plurality of vias arranged between the region where the shielded circuit is arranged and the region where the second electronic circuit is arranged when viewed from above. The plurality of vias penetrate the interlayer insulating film in a thickness direction and are connected to the first metal pattern.

4. The semiconductor device according to any one of claims 1 to 3, wherein The first metal pattern is arranged to overlap the shielded circuit in a plan view.

5. The semiconductor device according to any one of claims 1 to 4, wherein The first metal pattern is a metal film including the shielded circuit in a plan view.

6. The semiconductor device according to any one of claims 1 to 3, wherein The shielding structure further includes a plurality of metal lines arranged to pass through a region where the shielded circuit is arranged in a plan view, and the plurality of metal lines are fixed to the first metal pattern.

7. The semiconductor device according to any one of claims 1 to 6, wherein The first member further includes a metal region at an interface with the second member, and the metal region is electrically connected to the first metal pattern.

8. The semiconductor device according to any one of claims 1 to 7, wherein The first component includes a multilayer wiring structure arranged on the first electronic circuit, The multilayer wiring structure includes a second metal pattern that overlaps with a region where the shielded circuit is disposed when viewed from above. The interlayer insulating film is disposed on the multilayer wiring structure, and the first metal pattern is connected to the second metal pattern through an opening provided in the interlayer insulating film.

9. A semiconductor module comprising: module substrate; as well as A semiconductor device mounted on the mounting surface of the module substrate, The semiconductor device includes: a first component forming a first electronic circuit including a semiconductor element; a second member bonded to a portion of the first surface, which is one surface of the first member, and forming a second electronic circuit, the second electronic circuit including a semiconductor element made of a semiconductor material different from that of the semiconductor element of the first electronic circuit; an interlayer insulating film covering the first surface and the second component; inter-component connection wiring, arranged on the interlayer insulating film, connecting the first electronic circuit and the second electronic circuit via an opening provided in the interlayer insulating film; a shielding structure including a first metal pattern disposed on the interlayer insulating film and shielding a shielded circuit that is a part of the first electronic circuit at high frequencies; a first conductive protrusion protruding from the first metal pattern; and The second conductor protrusion is provided on the surface of the second component facing the module substrate and is connected to the ground line of the second electronic circuit. The module substrate includes: grounding conductor; and The first pad and the second pad are connected to the ground conductor. The first pad and the second pad are connected to the first conductive protrusion and the second conductive protrusion, respectively.

10. The semiconductor module according to claim 9, wherein The above-mentioned grounding conductors include: a multi-layer ground plane disposed on an inner layer of the module substrate and on a lower surface opposite to the mounting surface; and A plurality of ground vias connect the multi-layer ground planes in the thickness direction of the module substrate. At a position shallower than the first position in the thickness direction of the module substrate when viewed from the mounting surface, the ground plane connected to the first solder pad and the ground plane connected to the second solder pad are separated from each other, and at a position deeper than the first position, the ground plane connected to the first solder pad and the ground plane connected to the second solder pad are continuous.

11. The semiconductor module according to claim 9 or 10, wherein: Also features: a resin member covering the mounting surface of the module substrate and the semiconductor device; a metal shielding film disposed on a surface of the resin member facing the same direction as the mounting surface; and The shield wall penetrates the resin member in a thickness direction, surrounds the semiconductor device intermittently or continuously in a plan view, and is electrically connected to the metal shield film and the ground conductor.

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