Setting up integrated standard cells

Abstract

The present disclosure relates to the setting of integrated standard cells. The integrated circuit includes at least one first standard cell, which is framed by two second standard cells. The three cells are arranged adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one PMOS transistor located in and on a silicon-on-insulator (SOI) substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel, and the threshold voltage of the at least one PMOS transistor of each second standard cell is different in absolute value from the threshold voltage of the at least one PMOS transistor of the first cell.

Description

Technical Field

[0001] Embodiments and examples of the present disclosure relate to the field of microelectronics, particularly integrated circuits, and more particularly standard cells, such as those used in the design of digital logic circuits of integrated circuits. Background Art

[0002] Among the transistors used in integrated circuits (e.g., produced on a silicon-on-insulator (SOI) type substrate), it may be useful to use the following transistors:

[0003] - a low voltage threshold transistor (low VT: Voltage Threshold), having a threshold voltage of, for example, an absolute value of approximately 0.25 volts,

[0004] - a normal voltage threshold transistor (RVT) having a threshold voltage of, for example, an absolute value of approximately 0.35 volts, and

[0005] - High voltage threshold (HVT) transistors, typically having a threshold voltage of approximately 0.45 volts in absolute value.

[0006] These concepts of low voltage threshold, normal voltage threshold and high voltage threshold are known to those skilled in the art and depend on the values ​​of the technology node, and the values ​​indicated above are given for a technology node of approximately 10% less than 90 nm.

[0007] Low voltage threshold and normal voltage threshold transistors, in particular when they comprise a SiGe channel, that is, silicon and germanium, are particularly used for the production of critical paths because they have high speed and good current performance, that is, a current in the on-state (ionic current) of typically greater than 500 microamperes / micron.

[0008] On the other hand, such transistors have a significant leakage, that is to say a relatively high current Ioff in the off state of the transistor, typically in the order of 1 nanoampere / micrometer to 20 or 30 nanoamperes / micrometer.

[0009] Furthermore, the use of silicon channel high voltage threshold transistors is interesting because they have low leakage current, typically around 0.05 nanoamperes per micron.

[0010] Currently, one can find integrated circuits or parts of integrated circuits using only SiGe channel transistors and other integrated circuits or other parts of the same integrated circuits using only silicon channel transistors (such as high voltage threshold transistors) on the same technology platform.

[0011] However, such an arrangement consumes space.

[0012] Therefore, there is a need to be able to combine silicon germanium channel transistors of the low voltage threshold and normal voltage threshold types with silicon channel transistors of the high voltage threshold type within a single integrated circuit. Summary of the Invention

[0013] According to one or more embodiments, an integrated circuit is provided, which includes at least one first standard cell framed by two second standard cells.

[0014] These three cells are arranged adjacent to one another, that is to say they are directly adjacent or butted together or indirectly butted together, that is to say by means of one or more other standard cells, for example so-called filler cells as will be seen in more detail below.

[0015] Thus, two adjacent cells are separated by a distance which may be zero or less than or equal to one hundred nanometers, for example.

[0016] Each cell includes at least one NMOS transistor and at least one PMOS transistor located in and on a silicon-on-insulator type substrate.

[0017] At least one PMOS transistor of the first standard cell has a channel including silicon and germanium.

[0018] The at least one PMOS transistor of each second standard cell has a silicon channel, and a threshold voltage of the at least one PMOS transistor of each second standard cell is different from the threshold voltage of the at least one PMOS transistor of the first cell in absolute value, for example, greater than the threshold voltage of the at least one PMOS transistor of the first cell.

[0019] Therefore, the problem of surface crowding can be solved by placing standard cells including SiGe channel PMOS transistors and Si channel PMOS transistors next to each other. It is thus possible to mix transistors with different threshold voltages, in particular, mixing SiGe channel low voltage threshold and normal voltage threshold transistors with Si channel high voltage threshold transistors.

[0020] There are several solutions for placing these standard cells next to each other.

[0021] The inventors did observe that placing SiGe channel transistors and Si channel transistors next to each other can result in performance degradation, which may be inconvenient in some applications.

[0022] In addition, according to one variant, the integrated circuit may further include a semiconductor connection region connecting the active region of at least one PMOS transistor of the first standard cell (the standard cell having a SiGe channel) and the active region of the PMOS transistor of the second standard cell (the standard cell having a silicon channel).

[0023] The semiconductor connection region notably comprises an insulating gate which allows the two active regions to be insulated from one another, but the semiconductor connection region forms a continuous active region together with the active region of the transistor and thus allows avoiding active cuts which would cause stress relaxation caused by the silicon germanium, impairing the performance of the associated SiGe channel transistor.

[0024] Furthermore, in order not to excessively impair the performance of the silicon germanium channel PMOS transistor, according to an embodiment compatible with this variation, the following configuration is performed for the integrated circuit: including at least two standard cells referred to as filling cells, which frame the first standard cell, are respectively arranged between the first standard cell and the two second standard cells, and are respectively connected to the first standard cell and the two second standard cells.

[0025] Each filling unit includes:

[0026] a fill region having a first portion comprising silicon and germanium in contact with the active region of the PMOS transistor of a first standard cell and a second portion comprising silicon in contact with the active region of the PMOS transistor of a corresponding second standard cell, and

[0027] - Two first polysilicon lines (forming an insulating gate), respectively located above the boundary between the filling cell and the first standard cell or the second standard cell, and intended to be biased with the supply voltage VDD.

[0028] These filling regions form the semiconductor connection regions.

[0029] The fact of adding these filled SiGe regions allows the stress in the SiGe channel of the PMOS transistor not to be excessively relaxed and thus limits the performance losses of the SiGe channel PMOS transistor.

[0030] However, in order not to unduly impair the performance of the silicon channel transistor, it is particularly advantageous to disconnect this continuous semiconductor region and provide a cut between the active area of ​​the silicon channel transistor and the active area of ​​the silicon germanium channel transistor, while still using a filling cell containing silicon and germanium so as not to impair the performance of the SiGe channel PMOS transistor.

[0031] Therefore, according to one embodiment, the integrated circuit includes at least two standard cells called filler cells, which frame the first standard cell, are respectively arranged between the first standard cell and two second standard cells, and are respectively connected to the first standard cell and the two second standard cells.

[0032] Each filling cell includes a filling region containing silicon and germanium, which is adjacent to the active area of ​​the PMOS transistor of the first standard cell, and at least one first polysilicon line, which is located above the filling region and is intended to remain electrically floating.

[0033] Furthermore, the filling region is separated from the active region of the at least one PMOS transistor (ie, silicon channel PMOS transistor) of each second standard cell by an insulating region.

[0034] Regardless of the embodiment, the at least one PMOS transistor of the first standard cell may be a low voltage threshold transistor, and the at least one PMOS transistor of the second standard cell may be a high voltage threshold transistor.

[0035] At least one PMOS transistor of the first standard cell may be a normal voltage threshold transistor and at least one PMOS transistor of the second standard cell may be a high voltage threshold transistor.

[0036] However, the embodiments just mentioned occupy a certain space on the silicon due to the presence of the filling cells, and in certain applications it may be advantageous to further reduce this surface crowding.

[0037] This is why, in a further variant, it is planned to eliminate these standard filling cells and to interrupt the continuity of the active zone.

[0038] Thus, according to another variant, the at least one NMOS transistor of the first standard cell has a silicon channel and a threshold voltage, e.g. a normal voltage threshold, which is equal to or preferably greater in absolute value than the threshold voltage (of the at least one PMOS transistor of the first standard cell), e.g. a low voltage threshold.

[0039] Furthermore, the active region of the at least one PMOS transistor of the first standard cell is electrically insulated from the active region of the at least one PMOS transistor of each second standard cell.

[0040] Thus, in this variant, for example, a hybrid of transistors with a high voltage threshold and a silicon channel and transistors with a conventional voltage threshold is obtained using a standard cell that does not include a conventional voltage threshold NMOS transistor and a conventional voltage threshold PMOS transistor but uses a conventional voltage threshold NMOS transistor and a low voltage threshold silicon germanium channel PMOS transistor.

[0041] The fact of using low voltage threshold transistors on a silicon germanium channel allows compensating (particularly in terms of leakage current) the performance degradation caused by the disconnection between the active area of ​​the PMOS transistor of the second cell and the active area of ​​the PMOS transistor of the first cell.

[0042] In such a variant, a first standard cell may advantageously be adjacent to each second standard cell.

[0043] As described above, at least one NMOS transistor of the first cell may be a normal voltage threshold transistor, at least one PMOS transistor of the first cell may be a low voltage threshold transistor, and at least one PMOS transistor of each second cell may be a high voltage threshold transistor.

[0044] According to a further embodiment, the integrated circuit may further comprise a set of three additional standard cells forming a combination having good performance in terms of current flow in the on-state (ionic current).

[0045] The set of additional cells may be added to at least one of the above defined combinations of standard cells, eg in an integrated circuit.

[0046] Therefore, in this embodiment, the integrated circuit further includes another group of first additional standard cells, and the another group of first additional standard cells is framed by two second additional standard cells.

[0047] The three additional cells are abutted (butted) and each additional cell includes at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel containing silicon and germanium.

[0048] The active regions of all PMOS transistors form a continuous semiconductor region.

[0049] A threshold voltage of at least one PMOS transistor of the first additional cell is different in absolute value from a threshold voltage of a PMOS transistor of the second additional cell.

[0050] The integrated circuit further comprises two polysilicon lines intended to be biased with a power supply voltage and respectively arranged above the boundaries between the active areas of at least one PMOS transistor of the first additional unit and at least one PMOS transistor of each second additional unit.

[0051] The at least one PMOS transistor of the first additional cell may be a low voltage threshold transistor, and the PMOS transistor of the second additional cell may be a normal voltage threshold transistor.

[0052] Regardless of the variants and embodiments, the silicon-on-insulator type substrate may be a fully depleted silicon-on-insulator (FDSOI) type substrate.

[0053] According to another embodiment, there is provided a method of manufacturing an integrated circuit, comprising:

[0054] - storing a standard cell library in a memory, the standard cell library being intended to be generated on a silicon-on-insulator type substrate and comprising at least one first standard cell and a second standard cell, each cell comprising at least one NMOS transistor and at least one PMOS transistor, the at least one PMOS transistor of the first standard cell having a channel comprising silicon and germanium, the at least one PMOS transistor of the second standard cell having a silicon channel, and a threshold voltage of the at least one PMOS transistor of the second standard cell being different from the threshold voltage of the at least one PMOS transistor of the first cell, for example being greater in absolute value than the threshold voltage of the at least one PMOS transistor of the first cell.

[0055] - extracting the standard cells from the memory and placing the cells so that they are located adjacent to each other, a first standard cell being framed by two second standard cells,

[0056] - and based on the placement of said cells, an integrated circuit is generated.

[0057] According to one embodiment,

[0058] - the first standard cell comprises an insulating region surrounding the active region of the at least one NMOS transistor and the active region of the at least one PMOS transistor,

[0059] - a second standard cell comprising an insulating region at least partially surrounding the active region of the at least one NMOS transistor and the active region of the at least one PMOS transistor,

[0060] each NMOS transistor of the first standard cell has a silicon channel, a threshold voltage of each NMOS transistor of the first standard cell being equal to and preferably greater than a threshold voltage of each PMOS transistor of the first standard cell in absolute value, and

[0061] The threshold voltage of each PMOS transistor of the second standard cell is greater in absolute value than the threshold voltage of each NMOS transistor of the first cell.

[0062] Furthermore, the following arrangement is made: a first standard cell is framed by two second standard cells, and the first standard cell is placed so that an active region of a PMOS transistor of the first standard cell is electrically insulated from active regions of PMOS transistors of the two second cells.

[0063] According to one embodiment, at least one NMOS transistor of the first cell is a normal voltage threshold transistor, at least one PMOS transistor of the first cell is a low voltage threshold transistor and at least one PMOS transistor of the second cell is a high voltage threshold transistor.

[0064] According to one embodiment, the standard cell library further comprises a first additional standard cell and a second additional standard cell, each additional cell comprising at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel comprising silicon and germanium, and the threshold voltage of the at least one PMOS transistor of the first additional cell is different in absolute value from the threshold voltage of the at least one PMOS transistor of the second additional cell, and the placement further comprises arranging the additional cells so that the first additional cell is framed in an adjacent manner by the two second additional cells, the active areas of the PMOS transistors of all the additional cells form a continuous semiconductor region, and at least one of the first additional cell or the second additional cell has a polysilicon line on its edge above the corresponding active area, the polysilicon line being intended to be biased with a power supply voltage.

[0065] According to one embodiment, at least one PMOS transistor of the first additional unit is a low voltage threshold transistor and at least one PMOS transistor of the second additional unit is a normal voltage threshold transistor.

[0066] According to another embodiment, a standard cell is provided, which is intended to be generated on a silicon-on-insulator type substrate and includes: at least one NMOS transistor having a silicon channel; at least one PMOS transistor having a channel including silicon and germanium, and the threshold voltage of the at least one PMOS transistor is lower in absolute value than the threshold voltage of the at least one NMOS transistor; and an insulating region surrounding the active area of ​​the at least one NMOS transistor and the active area of ​​the at least one PMOS transistor.

[0067] According to one embodiment, the at least one NMOS transistor is a normal voltage threshold transistor and the at least one PMOS transistor is a transistor with a low voltage threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Other advantages and features of the present disclosure will become apparent upon examination of the detailed description of examples and embodiments, which are in no way limiting, and of the accompanying drawings, in which:

[0069] Figures 1 to 6 NMOS and PMOS transistors with different threshold voltages generated on a silicon-on-insulator type (eg, fully depleted silicon-on-insulator type) substrate according to one or more embodiments are schematically illustrated.

[0070] Figure 7 An integrated circuit including a first standard cell framed by two second standard cells by means of two filling cells according to one or more embodiments is schematically illustrated.

[0071] Figure 8 An integrated circuit including a first standard cell including two silicon-germanium channel PMOS transistors with polysilicon lines forming their gates is schematically illustrated according to one or more embodiments.

[0072] Figure 9 An integrated circuit comprising a first standard cell framed by two second standard cells in an abutting manner is schematically illustrated according to some embodiments.

[0073] Figure 10 An integrated circuit including a first additional standard cell framed in an abutting manner by two second additional standard cells according to one or more embodiments is schematically illustrated.

[0074] Figure 11 A method of manufacturing an integrated circuit according to one or more embodiments is schematically illustrated. DETAILED DESCRIPTION

[0075] Figures 1 to 6 NMOS and PMOS transistors with different threshold voltages generated on a silicon-on-insulator type (eg, fully depleted silicon-on-insulator type) substrate are schematically shown.

[0076] An NMOS transistor used in a standard cell to be described below has a silicon channel.

[0077] In addition to the high voltage threshold PMOS transistor having a silicon channel, the PMOS transistor used in the standard cell to be described below has a silicon germanium channel.

[0078] exist Figure 1 In FIG. 1 , reference TNLVT denotes a low voltage threshold NMOS transistor, typically a low voltage threshold NMOS transistor of about 0.25 volts.

[0079] This NMOS transistor is generated in and on the semiconductor film FLM provided over a buried insulating region BX (known to those skilled in the art as BOX: Buried OXyde).

[0080] The buried insulating layer BX is located over the N-type doped semiconductor well CSN formed in the semiconductor substrate SB.

[0081] The portion of the well CSN situated below the buried layer BX forms a back gate BG which is biased here by an N+ contact arranged between two insulating regions STI.

[0082] The transistor TNLVT further comprises elevated regions of the source S and the drain D, and a gate GRN which here comprises a metal having an N-type output function.

[0083] The transistor TNLVT has an all-silicon channel.

[0084] The semiconductor film FLM is intrinsic silicon, that is, it has a 11 atoms / cm 3 doping concentration.

[0085] Figure 2 The transistor TNRVT shown in FIG. 5 is a normal voltage threshold NMOS transistor, that is, a normal voltage threshold NMOS transistor of approximately 0.35 volts.

[0086] The transistor TNRVT can be connected to the semiconductor film FLM by doping Figure 1 The transistor TNLVT is distinguished.

[0087] In fact, for the transistor TNRVT, the doping concentration of the film FLM is about 10 18 atoms / cm 3 .

[0088] The transistor TNRVT may be a silicon channel transistor.

[0089] Figure 3 An NMOS transistor TNHVT having a high voltage threshold, typically about 0.45 volts, is shown.

[0090] This transistor TNHVT may also have a silicon channel.

[0091] It is related to Figure 2 The transistor TNRVT in FIG. 1 is different in that it includes a gate GRP including a metal having a P-type output work function, whereas the transistor TNRVT has a GRN including a metal having an N-type output work function.

[0092] The doping concentration of the thin film FLM of the transistor TNHVT can be Figure 2 The doping concentration of the thin film FLM of the transistor TNRVT is the same.

[0093] Figures 4 to 6PMOS transistors with different threshold voltages are shown.

[0094] Figure 4 A PMOS transistor TPLVT with a low voltage threshold is shown, whose channel comprises silicon and germanium, such as Si 1-x Ge x Alloys wherein x is between 0.1 (10%) and 0.4 (40%), preferably equal to 0.2 (20%).

[0095] Its structure is similar to Figure 1 The structure of the NMOS transistor TNLVT can be distinguished by the type of dopant.

[0096] More specifically, for the transistor TPLVT, the semiconductor well where the rear gate BG is located is a P-type doped well CSP, which can be biased through a P+ contact.

[0097] The source region S and the drain region D are P-doped. In contrast, the gate GRN comprises a metal having an N-type output power.

[0098] Since the threshold voltage is low, the film FLM is intrinsic silicon germanium.

[0099] Figure 5 The transistor TPRVT is a conventional voltage threshold PMOS transistor with a silicon germanium channel and can be controlled by adjusting the doping concentration of the thin film FLM. Figure 4 The doping concentration of the thin film FLM can be equal to Figure 2 The doping concentration of the thin film FLM of the transistor TNRVT.

[0100] Figure 6 The transistor TPHVT shown is a silicon channel high voltage threshold PMOS transistor.

[0101] The transistor TPHVT is Figure 5 The transistor TPRVT differs from the transistor TPHVT in that, on the one hand, the fact that the gate GRP of this transistor TPHVT contains a metal with P-type output work function and, on the other hand, the fact that the channel of the transistor TPHVT contains intrinsic silicon instead of silicon germanium (SiGe) allows the threshold voltage of the PMOS transistor to be increased by 250 mV or 300 mV in absolute value.

[0102] In the remainder of this document, transistors whose reference numbers end with LVT are low voltage threshold transistors, transistors whose reference numbers end with RVT are normal voltage threshold transistors, and transistors whose reference numbers end with HVT are high voltage threshold transistors.

[0103] exist Figure 7, reference sign IC denotes an integrated circuit which, in this example, includes a first standard cell STD1 framed by two second standard cells STD2 by means of two fill cells STDFL1 .

[0104] More specifically, the first standard cell STD1 herein includes two SiGe channel PMOS transistors TPLVT(SiGe) and two Si channel NMOS transistors TNLVT(Si).

[0105] The polysilicon lines forming the gates GRN of these transistors are higher than the active regions ZA of the two transistors TPLVT (SiGe).

[0106] Each second standard cell STD2 here includes two silicon-channel PMOS transistors TPHVT(Si) and two silicon-channel NMOS transistors TNHVT(Si).

[0107] The polysilicon lines forming the gates GRP of these transistors TPHVT also rise above the active areas ZA of these transistors TPHVT(Si).

[0108] Each filling cell STDFL1 includes a filling region FLRG1 including a first portion P1 formed of silicon germanium contacting the active region ZA of the transistor TPLVT(SiGe) and a second portion P2 including silicon contacting the active region ZA of the transistor TPHVT(Si) to form a continuous semiconductor region.

[0109] The two sections P1 and P2 form two buffer zones (SiGe on the TPLVT side and Si on the TPHVT side) allowing absorption of Si / SiGe transitions.

[0110] The integrated circuit further comprises two polysilicon lines GRI.

[0111] Each line GRI overlaps with a boundary between the filling cell STDFL1 and the cell STD1 or STD2, respectively.

[0112] These polysilicon lines GRI are connected to a power supply voltage VDD (for example, approximately 1 volt) in order to form insulating gates allowing the transistors TPHVT(Si) to be electrically isolated from the transistors TPLVT(SiGe).

[0113] The polysilicon line GRI located between the two insulated gates may be left floating.

[0114] Figure 8 Examples and Figure 7 The embodiment of FIG. 1 differs in particular in that there is no longer a continuous semiconductor region between the silicon channel transistor TPHVT(Si) and the silicon germanium channel transistor TPLVT(SiGe).

[0115] In practice, this continuity is broken at the edge of the transistor TPHVT(Si) in order not to degrade the performance of this transistor.

[0116] More specifically, the integrated circuit IC1 here comprises a first standard cell STD10 , which again comprises two silicon-germanium channel PMOS transistors TPLVT(SiGe), the polysilicon lines GRN forming their gates being higher than their active zones ZA.

[0117] The first standard cell STD10 further includes two silicon-channel NMOS transistors TNLVT(Si).

[0118] The first standard cell STD10 is framed by two second standard cells STD20 by means of two filling cells STDFL10 .

[0119] Each second unit STD20 here includes two silicon channel PMOS transistors TPHVT(Si) and two silicon channel NMOS transistors TNHVT(Si).

[0120] Two polysilicon lines forming the gates GRP of these PMOS transistors are higher than the active areas ZA of the PMOS transistors.

[0121] Each filling cell STDFL10 includes a filling region FLRG10 formed of silicon and germanium of the active region ZA of the extension transistor TPLVT (SiGe).

[0122] On the other hand, each filling cell includes the insulating region RIS allowing the filling region FLRG10 to be insulated from the active region ZA of the transistor TPHVT(Si) corresponding to the second standard cell STD20 .

[0123] In order to maintain the silicon line spacing, a floating silicon line LPL may be inserted between the gates of different transistors.

[0124] In order to save space, the filling cells may be eliminated and the continuous semiconductor region including all active regions of the PMOS transistors may be omitted, that is, the continuity is destroyed.

[0125] In this regard, the following can be provided: a first standard cell comprising an NMOS transistor and a PMOS transistor having the same threshold voltage (e.g., a normal voltage threshold transistor), the first standard cell being framed in a butt-jointed manner by two second standard cells having silicon channel PMOS transistors (e.g., having a high voltage threshold).

[0126] However, in this case, the performance of the PMOS transistor of the first standard cell is degraded, especially with respect to ion current, which may be inconvenient in some applications.

[0127] To overcome this performance loss, a first “mixed” standard cell can also be used, that is to say with NMOS and PMOS transistors having different threshold voltages, the PMOS transistor generally having a lower threshold voltage in absolute terms than the threshold voltage of the NMOS transistor.

[0128] An example of such a configuration is Figure 9 shown.

[0129] In this Figure 9 In the embodiment, the integrated circuit IC2 includes a first standard cell STD100 , which is framed by two second standard cells STD200 in a butt-jointed manner.

[0130] The first unit STD100 includes a silicon channel NMOS transistor TNRVT(Si) and a silicon germanium channel PMOS transistor TPLVT(SiGe).

[0131] An insulating region RIS (eg, including silicon dioxide) surrounds each active area ZA of the transistors TNRVT and TPLVT.

[0132] Therefore, it can be seen here that, unlike a normal standard cell, the threshold voltage of the NMOS transistor is different from that of the PMOS transistor.

[0133] More specifically, the NMOS transistor TNRVT(Si) is a normal voltage threshold transistor, and the PMOS transistor TPLVT(SiGe) is a low voltage threshold transistor, but actually has a normal type voltage threshold due to the disconnection of the active region as shown below.

[0134] Each second standard cell STD200 here includes two silicon channel NMOS transistors TNHVT(Si) and two silicon channel PMOS transistors TPHVT(Si).

[0135] The polysilicon lines forming the gates GRP of these transistors are raised above the active areas ZA of these transistors.

[0136] Likewise, the active zones ZA of these transistors are at least partially surrounded by the insulating region RIS.

[0137] Due to the discontinuity of the active region between the PMOS transistors of the first and second standard cells, the threshold voltage of the transistor TPLVT will increase in absolute value, and the Ion current performance of the PMOS transistor TPLVT (SiGe) is affected and the ion current is reduced.

[0138] Therefore, the transistor TPLVT will operate like a regular voltage threshold transistor and have the same threshold voltage level.

[0139] Thus, this embodiment is notable in that it provides a mix of transistors with high voltage thresholds and silicon channels and transistors with normal voltage thresholds and SiGe channels while limiting crowding due to unfilled cells.

[0140] Thus, there are combinations of standard cells that provide a mix of transistors with different threshold voltages and low leakage (low current Ioff).

[0141] exist Figure 10 Other combinations of standard cells may be present in the integrated circuit shown. For example, these other combinations may be added to the integrated circuit. Figure 9 The unit combination in .

[0142] Figure 10 The integrated circuit IC3 includes a first additional standard cell STDS1 framed by two second additional standard cells STDS2 in a butted manner.

[0143] The first cell STDS1 includes a silicon-germanium channel PMOS transistor TPRVT(SiGe) and a silicon channel NMOS transistor TNRVT(Si).

[0144] The polysilicon lines GRN forming the gates of these transistors are raised above the active areas of these transistors.

[0145] Each second additional cell STDS2 includes a silicon germanium channel PMOS transistor TPLVT (SiGe) and a silicon channel NMOS transistor TNLVT (Si). Here again, the polysilicon line GRN forming the gates of these transistors is higher than the active area ZA of these transistors.

[0146] The active regions ZA of the PMOS transistors of these additional cells are in contact with each other to form a continuous semiconductor region.

[0147] In order to electrically insulate the transistor TPLVT (SiGe) from the transistor TPRVT (SiGe), a polysilicon line GRI biased with the power supply voltage VDD overlaps the boundary between the transistors TPRVT (SiGe) and the active area ZA of TPLVT (SiGe).

[0148] Here, a set of standard cells is thus obtained which provides a mix of transistors with different threshold voltages and high performance in terms of ion current.

[0149] Now more specifically refer to Figure 11 An example of an implementation of the method is described below.

[0150] A library LBR of standard cells is stored in the memory MM, which library LBR comprises in particular the cells STD1, STD2, STD10, STD20, STD100, STD200, STDS1, STDS2, STDFL1 and STDFL10 mentioned above.

[0151] It should be noted here that, even if all these cells are represented in the memory MM, the cells STDS2, STD1 and STD10 are identical in terms of basic cell characteristics (LVT type cells), and only their adjacencies will be different.

[0152] The same is true for the cells STD20 and STD200 which are identical in terms of basic cell characteristics (HVT type cells).

[0153] Then, in step ST110, extraction of some of these standard cells is performed, followed by placement ST111 of these extracted cells in order to obtain the desired configuration of the integrated circuit component to be generated, such as, for example, in Figures 7 to 10 The configuration shown in .

[0154] Then, depending on this placement of the cells, an integrated circuit IC, IC1, IC2 or IC3 is produced in a conventional manner known per se (step ST112).

[0155] The integrated circuit can be summarized as including at least one first standard cell (STD100), the first standard cell (STD100) being framed by two second standard cells (STD200), the three cells being placed adjacent to each other, each cell including at least one NMOS transistor (TNRVT) and at least one PMOS transistor (TPLVT) located in and on a silicon-on-insulator substrate, the at least one PMOS transistor (TPLVT) of the first standard cell (STD100) having a channel including silicon and germanium, the at least one PMOS transistor (TPHVT) of each second standard cell having a silicon channel, and the threshold voltage of the at least one PMOS transistor (TPHVT) of each second standard cell being different in absolute value from the threshold voltage of the at least one PMOS transistor (TPLVT) of the first cell.

[0156] The integrated circuit may further include a semiconductor connection region (FLRG1) connecting an active region of at least one PMOS transistor of the first standard cell (STD1) and an active region of a PMOS transistor of the second standard cell (STD2).

[0157] The integrated circuit may include at least two standard cells (STDFL1) referred to as fill cells, the two fill cells framing a first standard cell, being respectively arranged between the first standard cell (STD1) and two second standard cells (STD2), and respectively docking with the first standard cell and the two second standard cells, each fill cell including a fill region (FLRG1) and two first polysilicon lines (GRI), the fill region having a first portion (P1) containing silicon and germanium and a second portion (P2) containing silicon, the first portion (P1) containing silicon and germanium being in contact with the active region of the PMOS transistor of the first standard cell, and the second portion (P2) containing silicon being in contact with the active region of the PMOS transistor of the corresponding second standard cell, and the two first polysilicon lines (GRI) being respectively located above the boundary between the fill cell and the first standard cell (STD1) or the second standard cell (STD2) and being intended to be biased with a power supply voltage, the fill region forming the semiconductor connection region.

[0158] An integrated circuit may include at least two standard cells (STDFL10) referred to as fill cells, the two fill cells framing a first standard cell (STD10), being respectively arranged between the first standard cell (STD10) and two second standard cells (STD20), and being respectively connected to the first standard cell and the two second standard cells, each fill cell including a fill region containing silicon and germanium and at least one first polysilicon line, the fill region containing silicon and germanium being adjacent to the active region of the PMOS transistor of the first standard cell, and the at least one first polysilicon line being located above the fill region and intended to remain electrically floating, the fill region being separated from the active region of the at least one PMOS transistor of each second standard cell by an insulating region (RIS).

[0159] At least one PMOS transistor of the first standard cell may be a low voltage threshold transistor (TPLVT) and at least one PMOS transistor of the second standard cell may be a high voltage threshold transistor (TPHVT). At least one PMOS transistor of the first standard cell may be a normal voltage threshold transistor (TPVRT) and at least one PMOS transistor of the second standard cell may be a high voltage threshold transistor (TPHVT). At least one NMOS transistor of the first standard cell (STD100) may have a silicon channel, a threshold voltage of the at least one NMOS transistor of the first standard cell (STD100) being equal to or preferably greater than a threshold voltage of the at least one PMOS transistor of the first standard cell in absolute value, and an active region of the at least one PMOS transistor of the first standard cell may be electrically insulated from an active region of the at least one PMOS transistor of each second standard cell (STD200). The first standard cell (STD100) may be adjacent to each second standard cell (STD200). At least one NMOS transistor of the first unit (STD100) may be a normal voltage threshold transistor (TNRVT), at least one PMOS transistor of the first unit (STD100) may be a low voltage threshold transistor (TPLVT), and at least one PMOS transistor of each second unit (STD200) may be a high voltage threshold transistor (TPHVT).

[0160] The integrated circuit may also include another group of first additional standard cells (STDS1) framed by two second additional standard cells (STDS2), the three additional cells being adjacent and each additional cell including at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel containing silicon and germanium, the active regions of all PMOS transistors forming a continuous semiconductor region, the threshold voltage of at least one PMOS transistor of the first additional cell being different in absolute value from the threshold voltage of the PMOS transistor of the second additional cell, and the integrated circuit also including two polysilicon lines, which are intended to be biased with a power supply voltage and are respectively arranged above the boundary between the active region of at least one PMOS transistor of the first additional cell and the at least one PMOS transistor of each of the second additional cells.

[0161] At least one PMOS transistor of the first additional cell (STDS1) may be a low voltage threshold transistor (TPLVT) and the PMOS transistor of the second additional cell (STDS2) may be a normal voltage threshold transistor (TPRVT).The silicon-on-insulator substrate may be a fully depleted silicon-on-insulator substrate.

[0162] A method for manufacturing an integrated circuit can be summarized as comprising: storing a standard cell library (LBR) in a memory (MM), the standard cell library (LBR) being intended to be generated on a silicon-on-insulator type substrate and comprising at least one first standard cell and a second standard cell, each cell comprising at least one NMOS transistor and at least one PMOS transistor, the at least one PMOS transistor of the first standard cell having a channel comprising silicon and germanium, the at least one PMOS transistor of the second standard cell having a silicon channel, the threshold voltage of the at least one PMOS transistor of the second standard cell being different in absolute value from the threshold voltage of the at least one PMOS transistor of the first cell; extracting (ST110) these standard cells from the memory and placing (ST111) these cells so that they are arranged adjacent to each other, the first standard cell being framed by two second standard cells; and generating (ST112) an integrated circuit based on the placement of these cells.

[0163] The first standard cell may include an insulating region surrounding the active area of ​​the at least one NMOS transistor and the active area of ​​the at least one PMOS transistor, the second standard cell may include an insulating region at least partially surrounding the active area of ​​the at least one NMOS transistor and the active area of ​​the at least one PMOS transistor, each NMOS transistor of the first standard cell may have a silicon channel, each NMOS transistor of the first standard cell has a threshold voltage that is greater in absolute value than the threshold voltage of each PMOS transistor of the first standard cell, and the threshold voltage of each PMOS transistor of the second standard cell is greater in absolute value than the threshold voltage of each NMOS transistor of the first cell, and wherein the placement of the cells may include placing the first standard cell (STD100) so that the active area of ​​the PMOS transistor of the first standard cell is electrically insulated from the active areas of the PMOS transistors of the two second cells, the first standard cell (STD100) being framed in an adjacent manner by the two second standard cells (STD200). At least one NMOS transistor of the first cell may be a normal voltage threshold transistor (TNRVT), at least one PMOS transistor of the first cell may be a low voltage threshold transistor (TPLVT), and at least one PMOS transistor of the second cell may be a high voltage threshold transistor (TPHVT). The standard cell library may further include a first additional standard cell (STDS1) and a second additional standard cell (STDS2), each additional cell including at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel containing silicon and germanium, and the threshold voltage of the at least one PMOS transistor of the first additional cell is different from the threshold voltage of the at least one PMOS transistor of the second additional cell in absolute value, and the placement may further include arranging the additional cells so that the first additional cell is framed by the two second additional cells, the active regions of the PMOS transistors of all the additional cells form a continuous semiconductor region, and at least one of the first additional cell or the second additional cell has a polysilicon line on its edge above the corresponding active region, the polysilicon line being intended to be biased with a power supply voltage. At least one PMOS transistor of the first additional cell may be a low voltage threshold transistor (TPLVT) and at least one PMOS transistor of the second additional cell may be a normal voltage threshold transistor (TPRVT).

[0164] The standard cell can be summarized as being intended to be generated on a silicon-on-insulator substrate and comprising: at least one NMOS transistor (TNRVT) having a silicon channel; at least one PMOS transistor (TPLVT) having a channel comprising silicon and germanium, and the threshold voltage of the at least one PMOS transistor (TPLVT) being equal to or preferably lower in absolute value than the threshold voltage of the at least one NMOS transistor; and an insulating region surrounding the active area of ​​the at least one NMOS transistor and the active area of ​​the at least one PMOS transistor.

[0165] The at least one NMOS transistor may be a normal voltage threshold transistor (TNRVT) and the at least one PMOS transistor may be a transistor with a low voltage threshold (TPLVT).

[0166] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally speaking, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments required by the claims and the full scope of equivalents thereto. Therefore, the claims are not limited by this disclosure.

Claims

1. An integrated circuit comprising: Silicon-on-insulator substrate; At least one first standard cell is framed by two second standard cells, the first standard cell and the two second standard cells are arranged adjacent to each other, and each cell includes: At least one NMOS transistor and at least one PMOS transistor are located in and on the silicon-on-insulator substrate, the at least one PMOS transistor of the first standard cell having a channel including silicon and germanium, the at least one NMOS transistor of each second standard cell having a silicon channel, and a threshold voltage of the at least one NMOS transistor of each second standard cell being different in absolute value from a threshold voltage of the at least one PMOS transistor of the first standard cell. 2 . The integrated circuit according to claim 1 , further comprising a semiconductor connection region connecting an active area of ​​the at least one PMOS transistor of the first standard cell and an active area of ​​the PMOS transistor of the second standard cell.

3. The integrated circuit according to claim 2, comprising at least two filler cells, the at least two filler cells framing the first standard cell, being respectively arranged between the first standard cell and the two second standard cells, and respectively docking with the first standard cell and the two second standard cells, each filler cell comprising a filler region and two first polysilicon lines, the filler region having a first portion comprising silicon and germanium and a second portion comprising silicon, the first portion contacting an active region of at least one PMOS transistor of the first standard cell, and the second portion contacting an active region of at least one PMOS transistor of a corresponding second standard cell, the two first polysilicon lines being respectively located above boundaries between the filler cells and the first and second standard cells, and being configured to be biased with a power supply voltage, the filler region forming the semiconductor connection region.

4. The integrated circuit according to claim 1 , comprising at least two filler cells, the at least two filler cells framing the first standard cell, being respectively disposed between the first standard cell and the two second standard cells, and respectively docking with the first standard cell and the two second standard cells, each filler cell comprising a filler region containing silicon and germanium and at least one first polysilicon line, the filler region being adjacent to the active region of the at least one PMOS transistor of the first standard cell, the at least one first polysilicon line being located above the filler region and being configured to remain electrically floating, the filler region being separated from the active region of the at least one PMOS transistor of each second standard cell by an insulating region. 5 . The integrated circuit of claim 2 , wherein at least one PMOS transistor of the first standard cell is a low voltage threshold transistor, and at least one PMOS transistor of the second standard cell is a high voltage threshold transistor. 6 . The integrated circuit of claim 2 , wherein at least one PMOS transistor of the first standard cell is a normal voltage threshold transistor, and at least one PMOS transistor of the second standard cell is a high voltage threshold transistor.

7. The integrated circuit of claim 1 , wherein the at least one NMOS transistor of the first standard cell has a silicon channel, a threshold voltage of the at least one NMOS transistor of the first standard cell is equal to or greater than a threshold voltage of the at least one PMOS transistor of the first standard cell in absolute value, and an active area of ​​the at least one PMOS transistor of the first standard cell is electrically insulated from an active area of ​​the at least one PMOS transistor of each second standard cell.

8. The integrated circuit of claim 7, wherein the first standard cell is adjacent to each second standard cell.

9. The integrated circuit of claim 7, wherein at least one NMOS transistor of the first standard cell is a normal voltage threshold transistor, at least one PMOS transistor of the first standard cell is a low voltage threshold transistor, and at least one PMOS transistor of each second standard cell is a high voltage threshold transistor.

10. The integrated circuit according to claim 7 , further comprising another group of first additional standard cells, the another group of first additional standard cells being framed by two second additional standard cells, the first additional standard cell and the two second additional standard cells being adjacent, and each additional standard cell comprising at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel comprising silicon and germanium, active regions of all PMOS transistors forming a continuous semiconductor region, a threshold voltage of the at least one PMOS transistor of the first additional standard cell being different in absolute value from a threshold voltage of the at least one PMOS transistor of the second additional standard cell, and the integrated circuit further comprising two polysilicon lines, the two polysilicon lines being configured to be biased at a power supply voltage and being respectively disposed above a boundary between the active region of the at least one PMOS transistor of the first additional standard cell and the at least one PMOS transistor of each second additional standard cell. 11 . The integrated circuit of claim 10 , wherein the at least one PMOS transistor of the first additional standard cell is a low voltage threshold transistor, and the PMOS transistor of the second additional standard cell is a normal voltage threshold transistor.

12. The integrated circuit of claim 1, wherein the silicon-on-insulator substrate is a fully depleted silicon-on-insulator substrate.

13. A method for manufacturing an integrated circuit, comprising: Storing a standard cell library in a memory, the standard cell library being intended to be generated on a silicon-on-insulator substrate, the standard cell library comprising at least one first standard cell and at least one second standard cell, each cell comprising at least one NMOS transistor and at least one PMOS transistor, the at least one PMOS transistor of the first standard cell having a channel comprising silicon and germanium, the at least one NMOS transistor of the second standard cell having a silicon channel, and a threshold voltage of the at least one NMOS transistor of the second standard cell being different in absolute value from a threshold voltage of the at least one PMOS transistor of the first standard cell; extracting the standard cells from the memory and placing the standard cells so that the standard cells are disposed adjacent to each other, the first standard cell being framed by two second standard cells; as well as The integrated circuit is generated according to the placement of the standard cells.

14. The method of claim 13 , wherein the first standard cell includes an insulating region surrounding an active area of ​​the at least one NMOS transistor and an active area of ​​the at least one PMOS transistor, the second standard cell includes an insulating region at least partially surrounding the active area of ​​the at least one NMOS transistor and the active area of ​​the at least one PMOS transistor, each NMOS transistor of the first standard cell having a silicon channel and a threshold voltage, the threshold voltage of each NMOS transistor of the first standard cell being greater in absolute value than the threshold voltage of each PMOS transistor of the first standard cell, and the threshold voltage of each PMOS transistor of the second standard cell being greater in absolute value than the threshold voltage of each NMOS transistor of the first standard cell, and wherein placing the standard cell includes placing the first standard cell, the first standard cell being framed in an abutting manner by two second standard cells, such that the active area of ​​the at least one PMOS transistor of the first standard cell is electrically insulated from the active area of ​​the at least one PMOS transistor of the two second standard cells.

15. The method of claim 14, wherein at least one NMOS transistor of the first standard cell is a normal voltage threshold transistor, at least one PMOS transistor of the first standard cell is a low voltage threshold transistor, and at least one PMOS transistor of the second standard cell is a high voltage threshold transistor.

16. The method of claim 13 , wherein the standard cell library comprises a first additional standard cell and a second additional standard cell, each of the additional standard cells comprising at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel comprising silicon and germanium, and a threshold voltage of the at least one PMOS transistor of the first additional standard cell is different in absolute value from a threshold voltage of the at least one PMOS transistor of the second additional standard cell, and wherein the placing further comprises arranging the additional standard cells such that the first additional standard cell is framed by two second additional standard cells, active regions of the PMOS transistors of all the additional standard cells form a continuous semiconductor region, and at least one of the first additional standard cell or the second additional standard cell has, on an edge thereof, a polysilicon line over the corresponding active region, the polysilicon line being configured to be biased with a power supply voltage. 17 . The method of claim 16 , wherein at least one PMOS transistor of the first additional standard cell is a low voltage threshold transistor, and at least one PMOS transistor of the second additional standard cell is a normal voltage threshold transistor.

18. A standard cell comprising: Silicon-on-insulator (SOI) type substrates; At least one first standard cell is framed by two second standard cells, the three cells are arranged adjacent to each other, and each cell includes: at least one NMOS transistor, the at least one NMOS transistor having a silicon channel, the at least one NMOS transistor being located in and on the silicon-on-insulator type substrate; at least one PMOS transistor having a channel including silicon and germanium, and a threshold voltage of the at least one NMOS transistor of each second standard cell being different in absolute value from a threshold voltage of the at least one PMOS transistor of the first standard cell; as well as An insulating region surrounds the active region of the at least one NMOS transistor and the active region of the at least one PMOS transistor.

19. The standard cell of claim 18, wherein the at least one NMOS transistor is a normal voltage threshold transistor, and the at least one PMOS transistor is a transistor with a low voltage threshold.

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