Three-dimensional memory element and method for manufacturing the same

Abstract

The present invention discloses a three-dimensional memory element and a manufacturing method thereof, wherein the three-dimensional memory element comprises a plurality of blocks, each of which comprises a plurality of sections, and each section comprises a gate stack structure, a conductor layer, a plurality of first annular channel columns, a plurality of source / drain columns, and a plurality of charge storage structures. The gate stack structure is disposed on a substrate and comprises a plurality of gate layers electrically insulated from each other. The conductor layer is disposed between the substrate and the gate stack structure. The first annular channel column is disposed on the substrate and is located in the gate stack structure. The source / drain column is disposed on the substrate and two source / drain columns are disposed in each first annular channel column. Each charge storage structure is disposed between a corresponding gate layer and a corresponding first annular channel column. The conductor layer of one of the plurality of blocks is isolated from the conductor layer of another of the plurality of blocks.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology and relates to a three-dimensional memory element and a manufacturing method thereof. Background Art

[0002] Non-volatile memory is widely used in personal computers and other electronic devices because it has the advantage that the stored data will not disappear after power failure. The three-dimensional memories commonly used in the industry include NOR memory and NAND memory. In addition, another three-dimensional memory is AND memory, which can be used in multi-dimensional memory arrays and has high integration and high area utilization, and has the advantages of fast operation speed. Therefore, the development of three-dimensional memory elements has gradually become the current trend. Summary of the invention

[0003] The present invention provides a three-dimensional memory element, in which a conductor layer of one of the memory blocks is designed to be isolated from another conductor layer of the memory block, so that the bias voltage applied to the conductor layer can be well controlled.

[0004] One embodiment of the present invention provides a three-dimensional memory element, which includes a plurality of tiles, and each tile includes a plurality of blocks. Each block includes a gate stack structure, a conductor layer, a plurality of first annular channel columns, a plurality of source / drain columns, and a plurality of charge storage structures. The gate stack structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The conductor layer is disposed between the substrate and the gate stack structure. The first annular channel column is disposed on the substrate and is located in the gate stack structure. The source / drain column is disposed on the substrate and two source / drain columns are configured in each first annular channel column. The charge storage structure is disposed between the corresponding gate layer and the corresponding first annular channel column. The conductor layer of one of the plurality of tiles is isolated from the conductor layer of another of the plurality of tiles.

[0005] In one embodiment of the present invention, the conductor layers in two adjacent blocks are spaced apart from each other.

[0006] In one embodiment of the present invention, the conductive layers of the multiple blocks within the block are spaced apart from each other.

[0007] In one embodiment of the present invention, the conductive layers of a plurality of blocks within a block are electrically connected to each other.

[0008] In one embodiment of the present invention, the conductor layers of multiple blocks in each block element are integrally connected together.

[0009] In one embodiment of the present invention, the three-dimensional memory device further includes a plurality of dummy gate stack structures disposed on the substrate and respectively arranged on two opposite sides of the arrangement direction of the plurality of blocks of each unit.

[0010] In one embodiment of the present invention, the three-dimensional memory element further includes a plurality of dummy channel columns. The dummy channel columns are respectively located in corresponding dummy gate stack structures and extend into the substrate, each dummy channel column includes a second annular channel column and a conductive column located in the second annular channel column, and at least one of the plurality of conductor layers is connected to a driver located in the substrate through the corresponding conductive column.

[0011] In one embodiment of the present invention, the first annular channel column and the source / drain column extend into the conductive layer to form a bottom parasitic transistor in the conductive layer.

[0012] In one embodiment of the present invention, the bottom parasitic transistor is kept in an off state.

[0013] In one embodiment of the present invention, the three-dimensional memory element further includes an insulating pillar disposed between the two source / drain pillars.

[0014] A method for manufacturing a three-dimensional memory element according to an embodiment of the present invention comprises the following steps. A conductor material layer is formed on a substrate. A stacking structure is formed on the conductor material layer, wherein the stacking structure comprises a plurality of insulating material layers and a plurality of sacrificial material layers alternately stacked on the substrate. A plurality of first annular channel columns are formed in the stacking structure. A plurality of source / drain columns are formed in the stacking structure, and two source / drain columns are configured in each first annular channel column. The stacking structure and the conductor material layer are subjected to a patterning process to form a plurality of first channels that penetrate the stacking structure and the conductor material layer. The first channel defines a plurality of patterned stacking structures and a plurality of conductor layers. Each patterned stacking structure comprises a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the substrate, and the conductor layer is located between the substrate and the patterned stacking structure. The sacrificial layer is removed to form a horizontal opening between two adjacent insulating layers. A charge storage structure and a gate layer are sequentially formed in the horizontal opening, wherein the charge storage structure is disposed between the gate layer and the corresponding first annular channel column.

[0015] In one embodiment of the present invention, a plurality of first trenches define a plurality of blocks and a plurality of regions included in each block, wherein each region includes a patterned stacked structure and a conductor layer, and the conductor layers of the plurality of blocks in the block are spaced apart from each other.

[0016] In one embodiment of the present invention, the conductive layers of a plurality of blocks within a block are electrically connected to each other.

[0017] In one embodiment of the present invention, a plurality of first trenches define a plurality of blocks, each of which includes a plurality of patterned stacked structures and a conductor layer, wherein a second trench is formed between two adjacent patterned stacked structures to define a plurality of blocks on the conductor layer.

[0018] In one embodiment of the present invention, the method for manufacturing a three-dimensional memory device further includes forming a dummy channel column in the patterned stacked structure and the conductor layer, wherein the dummy channel column includes a second annular channel column and a conductive column in the second annular channel column.

[0019] In one embodiment of the present invention, at least one of the conductor layers is connected to a driver located in the substrate via a conductive pillar.

[0020] In one embodiment of the present invention, the gate layer or the source / drain column is connected to the active device located in the substrate via a dummy channel column.

[0021] In one embodiment of the present invention, the first annular channel column and the source / drain column extend into corresponding conductive layers respectively to form bottom parasitic transistors in the corresponding conductive layers.

[0022] In one embodiment of the present invention, the bottom parasitic transistor is kept in an off state.

[0023] In one embodiment of the present invention, an insulating column is formed between the two source / drain columns.

[0024] Based on the above, in the three-dimensional memory element of the present invention, the conductor layer of at least one of the multiple blocks is isolated from the conductor layers in other blocks. Therefore, when a bias is applied to the conductor layer, the capacitance generated between the conductor layer in other blocks and the corresponding gate layer can be ignored, so that the bias applied to the conductor layer can be well controlled.

[0025] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. 4 is a schematic top view of a three-dimensional memory device according to an embodiment of the present invention.

[0027] Figure 2 for Figure 1 A side view of region C in the X direction.

[0028] Figure 3A for Figure 1 A three-dimensional schematic diagram of area C observed from a certain viewing angle.

[0029] Figure 3B for Figure 1Schematic diagram of the cross section along the tangent line AA'.

[0030] Figure 4 FIG. 4 is a circuit diagram of a block of a three-dimensional memory device according to an embodiment of the present invention.

[0031] FIG. 5A to FIG. 5H FIG. 1 is a schematic diagram of a manufacturing process of a three-dimensional memory according to an embodiment of the present invention, wherein FIG. 5A to FIG. 5H for Figure 1 Manufacturing process along the tangent line A-A'.

[0032] 6A to 6H FIG. 1 is a schematic diagram of a manufacturing process of a three-dimensional memory according to an embodiment of the present invention, wherein 6A to 6H for Figure 1 Manufacturing process along the tangent line BB'.

[0033]

Explanation of symbols

[0034] 10: Three-dimensional memory element

[0035] 100: Base

[0036] 105: Conductor material layer

[0037] 110, 114: Conductor layer

[0038] 112: Conductive plug

[0039] 115: Stacked structure

[0040] 115a, 116: insulating material layer

[0041] 115b: Sacrificial material layer

[0042] 117: Patterned stacking structure

[0043] 120: Gate stack structure

[0044] 130, 132: Channel columns

[0045] 130H: Channel column opening

[0046] 140a, 140b: source / drain posts

[0047] 140aH, 140bH: Source / drain column openings

[0048] 142: Insulation column

[0049] 150: Charge storage structure

[0050] 160: Driver

[0051] 170: Active components

[0052] C: Region

[0053] B1, B2, B3, B4: Blocks

[0054] BL: Bit Line

[0055] CR: Storage unit area

[0056] CP: Conductive Column

[0057] DL1, DL2: Dielectric layer

[0058] DGS: Dummy Gate Stack

[0059] DVC: Dummy Channel Column

[0060] DVCH: Virtual channel column opening

[0061] GL: Gate layer

[0062] IL1, IL2, IL3: Insulation layer

[0063] PT: Transistor

[0064] SCL: Sacrificial Layer

[0065] SCLH: Horizontal opening

[0066] SL: Source Line

[0067] SR: Step Area

[0068] T1, T2, T3, T4: Block element

[0069] T: Channel

[0070] WL: Word Line DETAILED DESCRIPTION

[0071] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0072] Figure 1 FIG. 1 is a schematic top view of a three-dimensional memory element according to an embodiment of the present invention. For the convenience of explanation, Figure 1 Only the top view schematic diagram of the substrate 100, the conductive layer 110, the conductive layer 114, the gate layer GL in the gate stack structure, the dielectric layers DL1, DL2, the channel column 130, the source / drain columns 140a, 140b, the insulating column 142, the dummy gate stack structure DGS, and the sacrificial layer SCL in the patterned stack structure is drawn to clearly understand the corresponding relationship between the various components. Figure 2 for Figure 1 A side view of region C in the X direction. For the sake of convenience, Figure 2 The portion indicated by the dotted line frame in the figure represents the bottom parasitic transistor PT in a top view, so as to clearly understand the corresponding relationship between the components constituting the bottom parasitic transistor PT. Figure 3A for Figure 1 A three-dimensional schematic diagram of area C at a certain viewing angle. Figure 3B for Figure 1 Schematic diagram of the cross section along the tangent line AA'. Figure 4 FIG. 4 is a circuit diagram of a block of a three-dimensional memory device according to an embodiment of the present invention.

[0073] Please refer to Figures 1 to 4 The three-dimensional memory element 10 may include a plurality of blocks T1-T4, and each block T1-T4 may include a plurality of blocks B1-B4, and each block B1-B4 may include a conductor layer 110 disposed on a substrate 100, a gate stack structure 120, a plurality of annular channel columns 130, a plurality of source / drain columns 140a, 140b and a plurality of charge storage structures 150. Figure 1 The exemplary embodiment shows four blocks T1 - T4 and four blocks B1 - B4 included in each block T1 - T4 , but the number of blocks of the three-dimensional memory device 10 and the number of blocks included in each block are not limited thereto.

[0074] The conductor layer 110 may be disposed between the substrate 100 and the gate stack structure 120. The substrate 100 may include a dielectric layer formed on a semiconductor substrate, that is, the substrate 100 may include components such as an inner dielectric layer and / or a contact window, an interlayer dielectric layer and / or a via window (e.g., an inner wiring structure), an active element (e.g., a PMOS, NMOS, CMOS, JFET, BJT, or a diode) or a driver (e.g., a driver). However, for the sake of convenience, these components are not shown in the drawings. The material of the conductor layer 110 may include doped polysilicon. For example, the material of the conductor layer 110 may include P-type doped polysilicon.

[0075] The gate stack structure 120 may be disposed on the substrate 100 and include a plurality of gate layers GL electrically insulated from each other. The gate stack structure 120 may include a plurality of insulating layers IL1, and the gate layer GL may be disposed between two adjacent insulating layers IL1. The gate stack structure 120 may include a step region SR and a memory cell region CR. In some embodiments, the step region SR may be disposed on opposite sides of the memory cell region CR. In some embodiments, the gate layer GL may be connected to the word line WL (e.g., Figure 4 The material of the gate layer GL may include tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix) or cobalt silicide (CoSix). The material of the insulating layer IL1 may include silicon oxide.

[0076] The conductor layer 110 of at least one of the multiple blocks T1-T4 can be isolated from the conductor layers 110 in other blocks T1-T4 (for example, one of the conductor layers 110 is structurally and electrically isolated from the other conductor layers 110 to present a closed block). Therefore, when a bias is applied to the conductor layer 110, the capacitance generated between the conductor layer 110 in other blocks and the gate layer GL can be ignored, thereby enabling the bias applied to the conductor layer 110 to be well controlled.

[0077] In some embodiments, the conductor layers 110 in two adjacent blocks T1-T4 may be spaced apart from each other. In some embodiments, the conductor layer 110 of at least one of the multiple blocks B1-B4 in the block T1-T4 may be isolated from the conductor layers 110 in other blocks B1-B4. In some embodiments, the conductor layers 110 of the multiple blocks B1-B4 in the block T1-T4 may be spaced apart from each other. In other embodiments, the conductor layers 110 of the multiple blocks B1-B4 in the block T1-T4 may be connected or integrated to form a block conductor layer, and the block conductor layers in each block T1-T4 may be spaced apart from each other.

[0078] In some embodiments, the conductor layer 110 of at least one of the plurality of blocks T1-T4 may be electrically isolated from the conductor layers 110 in other blocks T1-T4. In some embodiments, the conductor layers 110 in two adjacent blocks B1-B4 in the block T1-T4 may be electrically isolated from each other, but the present invention is not limited thereto. In other embodiments, the conductor layers 110 in two adjacent blocks B1-B4 in the block T1-T4 may be electrically connected to each other to save space occupied by a driver configured to apply voltage to the conductor layer 110.

[0079] The annular channel column 130 may be disposed on the substrate 100 and located in the gate stack structure 120. The channel column 130 may be configured in the memory cell region CR of the gate stack structure 120. A plurality of channel columns 130 may be configured in the memory cell region CR of each gate stack structure 120. In some embodiments, the channel column 130 may penetrate the gate stack structure 120 and the conductor layer 110 and extend into the substrate 100. Since the conductor layer 110 of at least one of the plurality of blocks T1-T4 is isolated from the conductor layer 110 in the other blocks T1-T4, when a bias is applied to the conductor layer 110, the capacitance generated between the conductor layer 110 in the other blocks and the channel column 130 may not be considered, so that the bias applied to the conductor layer 110 can be well controlled.

[0080] In some embodiments, the channel column 130 may be continuous in its extension direction (e.g., in a direction perpendicular to the substrate 100). That is, the channel column 130 is integral in its extension direction and is not divided into a plurality of unconnected parts. In some embodiments, the channel column 130 may have a circular profile when viewed from above, but the present invention is not limited thereto. In other embodiments, the channel column 130 may also have a profile of other shapes (e.g., a polygon) when viewed from above. In some embodiments, the radial dimension of the channel column 130 in the substrate 100 may be smaller than the radial dimension of the channel column 130 in the gate stack structure 120. In some embodiments, the radial dimension of the channel column 130 in the conductor layer 110 may gradually decrease from the portion of the conductor layer 110 adjacent to the substrate 100 toward the substrate 100. The material of the channel column 130 may be a semiconductor material, such as undoped polysilicon.

[0081] In some embodiments, a dielectric layer DL1 may be disposed between the channel pillar 130 and the gate stack structure 120. In some embodiments, the dielectric layer DL1 may extend into the conductor layer 110. In some embodiments, the dielectric layer DL1 may penetrate the conductor layer 110 and be located in the substrate 100. In some embodiments, the dielectric layer DL1 between the channel pillar 130 and the gate layer GL may serve as a tunneling dielectric layer. The material of the dielectric layer DL1 may include silicon oxide.

[0082] The source / drain pillars 140a and 140b may be disposed on the substrate 100 and penetrate the gate stack structure 120, wherein two source / drain pillars 140a and 140b are disposed in each of the annular channel pillars 130. In this way, the three-dimensional memory element 10 may be capable of performing 1-bit operation or 2-bit operation through different operation methods. For example, when a voltage is applied to the source / drain pillars 140a and 140b, since the source / drain pillars 140a and 140b are connected to the channel pillar 130, electrons may be transmitted along the channel pillar 130 and stored in the entire charge storage structure 150, so that the three-dimensional memory element 10 may be operated by 1-bit. In addition, for operations using Fowler-Nordheim tunneling, source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons or holes can be locally captured in the charge storage structure 150 adjacent to one of the two source / drain pillars 140a, 140b, so that the three-dimensional memory device 10 can be operated as a single-level cell (SLC, 1 bit) or a multi-level cell (MLC, greater than or equal to 2 bits). The source / drain pillars 140a, 140b can be connected to the source line SL / bit line BL (such as BL) through other conductive layers. Figure 4 The material of the source / drain pillars 140a, 140b may include doped polysilicon.

[0083] In some embodiments, the source / drain pillars 140a and 140b may extend into the conductive layer 110, so that a bottom parasitic transistor PT may be formed in the conductive layer 110 together with the channel pillar 130 extending into the conductive layer 110, so that the two source / drain pillars 140a and 140b are less likely to generate leakage current at the bottom. For example, the conductive layer 110 may serve as the gate of the bottom parasitic transistor PT (e.g., Figure 4 The bottom parasitic transistor PT is shown as a gate line GP); the dielectric layer DL1 extending into the conductor layer 110 can be used as the gate dielectric layer of the bottom parasitic transistor PT; the channel column 130 extending into the conductor layer 110 can be used as the channel layer of the bottom parasitic transistor PT; and the source / drain columns 140a, 140b extending into the conductor layer 110 can be used as the source and drain of the bottom parasitic transistor PT, respectively. In other words, the bottom parasitic transistor PT can be a transistor with a wrap-around gate structure (gate-all-around, GAA). The bottom parasitic transistor PT can be kept in an off state. For example, the bottom parasitic transistor PT can be a transistor that is in an off state when no voltage is applied or a transistor that is in an off state when a voltage is applied.

[0084] In some embodiments, the two source / drain pillars 140a and 140b configured in the channel pillar 130 may be arranged to be staggered with each other, for example, the connection direction of the center points of the source / drain pillar 140a and the source / drain pillar 140b may be at an angle (for example, 45 degrees) less than 90 degrees with the extension direction (for example, the X direction) of the gate layer GL, so as to provide a good process margin for the wires (for example, the lines connected to the source line SL or the bit line BL) overlying the source / drain pillars 140a and 140b. In addition, the staggered source / drain pillars 140a and 140b help reduce gate induced drain leakage (GIDL).

[0085] In some embodiments, the extension direction of the source / drain pillars 140a, 140b in the gate stack structure 120 may be the same as the extension direction of the channel pillar 130, while the extension direction of the source / drain pillars 140a, 140b adjacent to the substrate 100 in the conductive layer 110 may be different from the extension direction of the channel pillar 130.

[0086] In some embodiments, an insulating column 142 may be disposed between the two source / drain columns 140a and 140b disposed in the channel column 130 to separate the two source / drain columns 140a and 140b, so as to provide a good process margin to avoid a punch through phenomenon between the two source / drain columns 140a and 140b. In some embodiments, the insulating column 142 may penetrate the gate stack structure 120 and extend into the conductor layer 110. The material of the insulating column 142 may include silicon nitride.

[0087] The charge storage structure 150 may be disposed between each of the gate layers GL and the corresponding channel pillar 130. In some embodiments, the charge storage structure 150 may be an oxide-nitride-oxide (ONO) composite layer. The dielectric layer DL1 may be an oxide layer adjacent to the channel in the ONO composite layer or a bandgap engineered tunneling oxide layer, that is, the dielectric layer DL1 may be a tunneling dielectric layer composed of a single oxide layer or a tunneling dielectric layer composed of an ONO composite layer (e.g., a tunneling composite layer portion of BE-SONOS). The charge storage layer (i.e., the nitride layer in the ONO composite layer) and the blocking layer (i.e., the oxide layer adjacent to the gate layer GL in the ONO composite layer) in the charge storage structure 150 may be located between the channel pillar 130 and the gate layer GL and between the gate layer GL and the insulating layer IL1.

[0088] In some embodiments, a buffer layer and a barrier layer may be disposed between the gate layer GL and the charge storage structure 150. The material of the buffer layer is, for example, a high dielectric constant material having a dielectric constant greater than 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxides, lanthanide oxides, or a combination thereof. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0089] In some embodiments, the three-dimensional memory element 10 may further include a plurality of dummy channel pillars DVC. The dummy channel pillar DVC may refer to a channel pillar in which the source / drain pillars 140a, 140b are not configured. In some embodiments, the dummy channel pillar DVC may be disposed in the step region SR of the gate stack structure 120, and the dummy channel pillar DVC may penetrate the gate stack structure 120 and extend into the substrate 100 to connect the signals of each gate layer GL in the gate stack structure 120 to the active elements located in the substrate 100. In some embodiments, the dummy channel pillar DVC may include a dielectric layer DL1, an annular channel pillar 132, a conductive pillar CP, and a dielectric layer DL2 between the annular channel pillar 132 and the conductive pillar CP. In some embodiments, the radial dimension of the dummy channel pillar DVC is greater than the radial dimension of the annular channel pillar 130. The material of the channel pillar 132 may include undoped polysilicon. The material of the conductive pillar CP may include tungsten (W), cobalt (Co), aluminum (Al), tungsten silicide (WSix) or cobalt silicide (CoSix). The material of the dielectric layer DL2 may include silicon oxide.

[0090] In some embodiments, the three-dimensional memory element 10 may further include a plurality of dummy gate stack structures DGS. The dummy gate stack structures DGS may be disposed on the substrate 100 and respectively configured on opposite sides of each block T1-T4 (e.g., opposite sides in the arrangement direction of the plurality of blocks B1-B4). In some embodiments, the dummy channel pillars DVC may penetrate the corresponding dummy gate stack structures DGS, and the conductor layer 110 of each block B1-B4 may be connected to the driver 160 via the corresponding dummy channel pillars DVC. In some embodiments, the conductor layer 110 of each block B1-B4 may be connected to the same driver 160 via the line configuration of the back-end of line (BEOL). For example, the conductor layer 110 of each block B1-B4 may be connected to the same conductor layer 114 via the conductive plug 112 and connected to the same driver 160 via the dummy channel pillars DVC, but the present invention is not limited thereto. In other embodiments, the conductor layer 110 of each block B1-B4 may also be connected to different drivers 160. In some embodiments, the dummy gate stack structure DGS and the gate stack structure 120 may be formed simultaneously in the same process.

[0091] In some embodiments, the insulating layer IL3 may be disposed between two adjacent gate stack structures 120 and / or between the gate stack structure 120 and the dummy gate stack structure DGS. The material of the insulating layer IL3 may include an organic insulating material, an inorganic insulating material, or a combination thereof.

[0092] Based on the above, the three-dimensional memory element 10 can be designed such that the conductor layer 110 of at least one of the multiple blocks T1-T4 is isolated from the conductor layers 110 in other blocks T1-T4. Therefore, when a bias is applied to the conductor layer 110, the capacitance generated between the conductor layer 110 and the gate layer GL in other blocks T1-T4 and / or the capacitance between the conductor layer 110 and the channel column 130 can be ignored. In this way, the bias of the conductor layer 110 can be well controlled.

[0093] The following will be FIG. 5A to FIG. 5H The manufacturing method of the three-dimensional memory device is described as an example, but the manufacturing method of the three-dimensional memory device of the present invention is not limited to this. In addition, the same or similar components are represented by the same or similar component numbers, and will not be repeated here.

[0094] FIG. 5A to FIG. 5H FIG. 1 is a schematic diagram of a manufacturing process of a three-dimensional memory according to an embodiment of the present invention, wherein FIG. 5A to FIG. 5H for Figure 1 Manufacturing process along the tangent line A-A'.

[0095] First, please refer to Figure 5A , a conductor material layer 105 is formed on the substrate 100 . The material of the conductor material layer 105 may include doped polysilicon. In some embodiments, the driver 160 may be disposed in the substrate 100 .

[0096] Next, a stepped stacked structure 115 is formed on the conductive material layer 105. In some embodiments, the stacked structure 115 may include a plurality of insulating material layers 115a and a plurality of sacrificial material layers 115b alternately stacked on the conductive material layer 105. In some embodiments, the insulating material layer 115a may be a silicon oxide layer, and the sacrificial material layer 115b may be a silicon nitride layer.

[0097] Then, the step-shaped stacked structure 115 is covered with an insulating material layer 116. The top surface of the insulating material layer 116 is coplanar with the top surface of the step-shaped stacked structure 115. The insulating material layer 116 may include an organic material, an inorganic material or a combination thereof.

[0098] Next, please refer to Figure 5A and Figure 5B, a channel column opening 130H and a dummy channel column opening DVCH are formed in the stacked structure 115. Then, a dielectric layer DL1 and a channel material layer (not shown) are sequentially formed on the sidewalls and bottom of the channel column opening 130H and the dummy channel column opening DVCH. Next, the channel material layer at the bottom of the channel column opening 130H and the dummy channel column opening DVCH can be removed by etching back to form channel columns 130 and channel columns 132. In some embodiments, the radial dimension of the dummy channel column opening DVCH can be larger than the radial dimension of the channel column opening 130H.

[0099] In some embodiments, in the process of removing the insulating material layer 115a and / or the sacrificial material layer 115b, the conductive material layer 105 may be used as an etching stop layer, so that the depth of the channel column opening 130H and the dummy channel column opening DVCH can be well controlled. For example, the channel column opening 130H and the dummy channel column opening DVCH may first be formed by removing the insulating material layer 115a and the sacrificial material layer 115b on the conductive material layer 105 through an etching process to form an opening that exposes the conductive material layer 105. Then, another etching process may be used to remove the conductive material layer 105 exposed by the opening to form the channel column opening 130H and the dummy channel column opening DVCH that expose the substrate 100.

[0100] Then, please refer to Figure 5B and Figure 5C A dielectric layer DL2 is formed on the sidewalls of the channel pillars 130 and 132 and on the dielectric layer DL1 exposed by the channel pillars 130 and 132, wherein the dielectric layer DL2 does not fill the channel pillar opening 130H and the dummy channel pillar opening DVCH, but reserves the central portion of the channel pillar opening 130H and the dummy channel pillar opening DVCH. Thereafter, an insulating material is filled in the central portion of the channel pillar opening 130H and the dummy channel pillar opening DVCH to form an insulating pillar 142.

[0101] Then, please refer to Figure 5C and Figure 5D , source / drain column openings 140aH and 140bH are formed in the dielectric layer DL2 on opposite sides of the insulating column 142 in the channel column 130, and a material such as doped polysilicon is filled in the source / drain column openings 140aH and 140bH to form source / drain columns 140a and 140b. Two source / drain columns 140a and 140b may be configured in each channel column 130.

[0102] Then, please refer to Figure 5D and 5EThe stacked structure 115 and the conductor material layer 105 are patterned to form a plurality of trenches T penetrating the stacked structure 115 and the conductor material layer 105. The trenches T can divide the stacked structure 115 and the conductor material layer 105 into a plurality of patterned stacked structures 117 and a plurality of conductor layers 110 to define a plurality of blocks (such as Figure 1 The blocks T1-T4 shown in FIG. 1 and the multiple blocks in each block (such as Figure 1 The patterned stacked structures 117 may include a plurality of insulating layers IL1 and a plurality of sacrificial layers SCL alternately stacked on the substrate 100. The conductive layer 110 may be located between the substrate 100 and the plurality of patterned stacked structures 117. In some embodiments, during the patterning process, a portion of the substrate 100 may be slightly removed so that the trench T extends into the substrate 100. In some embodiments, during the patterning process, a portion of the insulating material layer 116 may also be removed to form the insulating layer IL2.

[0103] In some embodiments, the patterning process includes the following steps. First, a first patterning process is performed on the stacked structure 115 using the conductive material layer 105 as an etch stop layer to form a plurality of patterned stacked structures 117 on the conductive material layer 105. Next, a second patterning process is performed on the conductive material layer 105 to form a plurality of conductive layers 110. The etching masks used in the first patterning process and the second patterning process may be the same or different, and the present invention is not limited thereto.

[0104] In some embodiments, the plurality of trenches T may be integrated together to form a continuous trench T, but the present invention is not limited thereto. In other embodiments, the plurality of trenches T may be spaced apart from each other. Figure 1 As shown, the trench T may be located between two adjacent blocks T1-T4 and two adjacent blocks B1-B4. In other embodiments, the trench T used to define the multiple blocks T1-T4 may penetrate the stacking structure 115 and the conductor material layer 105; and the trench (not shown) used to define the multiple blocks B1-B4 in each block T1-T4 may penetrate the stacking structure 115 and be disposed on the conductor layer 110. In this way, the conductor layers 110 of the multiple blocks B1-B4 in the blocks T1-T4 may be connected or integrated to form a block conductor layer 110, and the block conductor layers 110 in each block T1-T4 may be spaced apart from each other.

[0105] Then, please refer to Figure 5E and Fig. 5F, remove the sacrificial layer SCL in the patterned stack structure 117 to form a horizontal opening SCLH between two adjacent insulating layers IL1. In some embodiments, the channel T may be connected to the horizontal opening SCLH. In some embodiments, the sacrificial layer SCL may be removed by hot phosphoric acid. In some embodiments, during the process of removing the sacrificial layer SCL in the patterned stack structure 117, the dielectric layer DL2 in the channel column 130 and the channel column 132 in the memory cell region CR, the source / drain columns 140a, 140b, the insulating column 142, and the channel column 132 and the dielectric layer DL2 and the insulating column 142 in the channel column 132 in the step region SR may serve as support columns to maintain the stability of the structure. It should be noted that the area for removing the sacrificial layer SCL by hot phosphoric acid is limited, that is, the sacrificial layer SCL adjacent to the channel T will be removed, while the sacrificial layer SCL away from the channel T will be retained. For example, if Figure 1 As shown, the patterned stacked structure 117 where the sacrificial layer SCL is not removed is disposed between the dummy gate stacked structure DGS on one side of the block T1 and the dummy gate stacked structure DGS on the other side of the block T3. In other words, the dummy gate stacked structure DGS can be disposed on one side of the patterned stacked structure 117 where the sacrificial layer SCL is not removed.

[0106] Afterwards, please refer to Fig. 5F and Figure 5G , a charge storage structure 150 and a gate layer GL are sequentially formed in the horizontal opening SCLH. The charge storage structure 150 may be disposed between the gate layer GL and the corresponding channel pillar 130. In some embodiments, the charge storage structure 150 may be an oxide-nitride-oxide (ONO) composite layer. In the case where the dielectric layer DL1 may be an oxide layer adjacent to the channel in the ONO composite layer, a nitride layer and an oxide layer adjacent to the gate layer GL may be sequentially formed in the horizontal opening SCLH to form the charge storage structure 150 between the channel pillar 130 and the gate layer GL. In this embodiment, the nitride layer in the ONO composite layer and the oxide layer adjacent to the gate layer GL may be located between the gate layer GL and the insulating layer IL1. In some embodiments, the charge storage structure 150 and the gate layer GL may be formed by the following steps. First, a charge storage material layer (not shown) is conformally formed on the surface of the horizontal opening SCLH and the channel T, wherein the charge storage material layer does not fill the horizontal opening SCLH but retains the central portion of the horizontal opening SCLH. Next, a gate material layer (not shown) is formed on the charge storage material layer, wherein the gate material layer fills the central portion of the horizontal opening SCLH and is formed on the surface of the trench T. Then, the charge storage material layer and the gate material layer on the surface of the trench T are removed by, for example, an anisotropic etch back process, to form a charge storage structure 150 and a gate layer GL in the horizontal opening SCLH.

[0107] Next, please refer to Figure 5G and Figure 5H , an insulating material is filled in the trench T to form an insulating layer IL3. The insulating layer IL3 may fill the trench T. That is, the insulating layer IL3 may be located between two adjacent gate stack structures 120 and / or between the gate stack structure 120 and the dummy gate stack structure DGS.

[0108] Then, please refer to Figure 5H , the insulating pillar 142 in the channel pillar 132 can be removed, and a conductive pillar CP is formed that penetrates the dummy gate stack structure DGS and the conductor layer 110 and extends into the substrate 100, so that a dummy channel pillar DVC including the conductive pillar CP, the dielectric layers DL1, DL2 and the channel pillar 132 can be formed. The conductive pillar CP can be connected to an internal connection structure (not shown) in the substrate 100 to connect to the driver 160 located in the substrate 100. That is, in the case where the driver 160 is disposed in the substrate 100, the dummy channel pillar DVC can connect the signal of the gate line GP of the conductor layer 110 to the driver 160 in the substrate 100.

[0109] The following will be 6A to 6H The manufacturing method of the three-dimensional memory device is described as an example, but the manufacturing method of the three-dimensional memory device of the present invention is not limited to this. In addition, the same or similar components are represented by the same or similar component numbers, and will not be repeated here.

[0110] 6A to 6H FIG. 1 is a schematic diagram of a manufacturing process of a three-dimensional memory according to an embodiment of the present invention, wherein 6A to 6H for Figure 1 Manufacturing process along the tangent line BB'.

[0111] First, please refer to Fig. 6A , a conductor material layer 105 is formed on the substrate 100. In some embodiments, an active element 170 may be disposed in the substrate 100. Then, a stepped stacking structure 115 is formed on the conductor material layer 105. In some embodiments, the stacking structure 115 may include a plurality of insulating material layers 115a and a plurality of sacrificial material layers 115b alternately stacked on the conductor material layer 105.

[0112] Next, please refer to Fig. 6A and Figure 6B, a channel column opening 130H and a dummy channel column opening DVCH are formed in the stack structure 115. Then, a dielectric layer DL1 and a channel material layer (not shown) are sequentially formed on the sidewalls and bottom of the channel column opening 130H and the dummy channel column opening DVCH. Next, the channel material layer at the bottom of the channel column opening 130H and the dummy channel column opening DVCH can be removed by etching back to form channel columns 130 and channel columns 132.

[0113] Then, please refer to Figure 6B and Figure 6C A dielectric layer DL2 is formed on the sidewalls of the channel pillars 130 and 132 and on the dielectric layer DL1 exposed by the channel pillars 130 and 132, wherein the dielectric layer DL2 does not fill the channel pillar opening 130H and the dummy channel pillar opening DVCH, but reserves the central portion of the channel pillar opening 130H and the dummy channel pillar opening DVCH. Thereafter, an insulating material is filled in the central portion of the channel pillar opening 130H and the dummy channel pillar opening DVCH to form an insulating pillar 142.

[0114] Then, please refer to Figure 6C and Fig.6D , source / drain column openings 140aH and 140bH are formed in the dielectric layer DL2 on opposite sides of the insulating column 142 in the channel column 130, and a material such as doped polysilicon is filled in the source / drain column openings 140aH and 140bH to form source / drain columns 140a and 140b. Two source / drain columns 140a and 140b may be configured in each channel column 130.

[0115] Then, please refer to Fig.6D and 6E The stacked structure 115 and the conductor material layer 105 are patterned to form a plurality of trenches T penetrating the stacked structure 115 and the conductor material layer 105. The trenches T can divide the stacked structure 115 and the conductor material layer 105 into a plurality of patterned stacked structures 117 and a plurality of conductor layers 110 to define a plurality of blocks (such as Figure 1 The blocks T1-T4 shown in FIG. 1 and the multiple blocks in each block (such as Figure 1 The conductive layers 110 are separated from each other by a plurality of patterned stacked structures 117, and at least one of the conductive layers 110 is isolated from the other conductive layers 110. Each patterned stacked structure 117 may include a plurality of insulating layers IL1 and a plurality of sacrificial layers SCL alternately stacked on the substrate 100. The conductive layer 110 may be located between the substrate 100 and the plurality of patterned stacked structures 117.

[0116] Then, please refer to Fig. 6E and Fig. 6F, the sacrificial layer SCL in the patterned stack structure 117 is removed to form a horizontal opening SCLH between two adjacent insulating layers IL1. In some embodiments, the trench T may be connected to the horizontal opening SCLH. In some embodiments, the sacrificial layer SCL may be removed by hot phosphoric acid. It should be noted that the area of ​​the sacrificial layer SCL removed by hot phosphoric acid is limited, that is, the sacrificial layer SCL adjacent to the trench T will be removed, while the sacrificial layer SCL away from the trench T will be retained. For example, Figure 1 As shown, the patterned stacked structure 117 where the sacrificial layer SCL is not removed is disposed between the dummy gate stacked structure DGS on one side of the block T1 and the dummy gate stacked structure DGS on the other side of the block T3. In other words, the dummy gate stacked structure DGS can be disposed on one side of the patterned stacked structure 117 where the sacrificial layer SCL is not removed.

[0117] Afterwards, please refer to Fig. 6F and Figure 6G , a charge storage structure 150 and a gate layer GL are sequentially formed in the horizontal opening SCLH. The charge storage structure 150 may be disposed between the gate layer GL and the corresponding annular channel column 130. In some embodiments, the charge storage structure 150 and the gate layer GL may be formed by the following steps. First, a charge storage material layer (not shown) is conformally formed on the surface of the horizontal opening SCLH and the trench T, wherein the charge storage material layer does not fill the horizontal opening SCLH but retains the central portion of the horizontal opening SCLH. Next, a gate material layer (not shown) is formed on the charge storage material layer, wherein the gate material layer fills the central portion of the horizontal opening SCLH and is formed on the surface of the trench T. Then, the charge storage material layer and the gate material layer located on the surface of the trench T are removed by, for example, etching back, to form the charge storage structure 150 and the gate layer GL in the horizontal opening SCLH. In some embodiments, the charge storage structure 150 may be an oxide-nitride-oxide (ONO) composite layer. When the dielectric layer DL1 may be used as an oxide layer adjacent to the channel in the ONO composite layer, a nitride layer and an oxide layer adjacent to the gate layer GL may be sequentially formed in the horizontal opening SCLH to form a charge storage structure 150 between the channel pillar 130 and the gate layer GL.

[0118] Next, please refer to Figure 6G and Figure 6H , an insulating material is filled in the trench T to form an insulating layer IL3. The insulating layer IL3 may fill the trench T. That is, the insulating layer IL3 may be located between two adjacent gate stack structures 120 and / or between the gate stack structure 120 and the dummy gate stack structure DGS.

[0119] Then, please refer to Figure 6H, the insulating pillar 142 in the channel pillar 132 can be removed, and a conductive pillar CP is formed that penetrates the dummy gate stack structure DGS and the conductor layer 110 and extends into the substrate 100, so that a dummy channel pillar DVC including the conductive pillar CP, the dielectric layers DL1, DL2 and the channel pillar 132 can be formed. The conductive pillar CP can be connected to an internal connection structure (not shown) in the substrate 100 to be connected to the active element 170 located in the substrate 100. That is, in the case where the active element 170 is disposed in the substrate 100, the dummy channel pillar DVC can connect the signal of the word line WL and / or the bit line BL to the active element 170 in the substrate 100.

[0120] Based on the above, when the driver 160 and / or the active device 170 are disposed in the substrate 100, the dummy channel column DVC can be used to connect the signal of the gate line GP of the conductor layer 110 and / or the signal of the word line WL and the bit line BL to the driver 160 and / or the active device 170 in the substrate 100. In some embodiments, the dummy channel column DVC can be disposed in the step region SR of the gate stack structure 120 and electrically connected to the gate layer GL respectively. In this way, the dummy channel column DVC can connect the signal of the word line WL to the active device 170 in the substrate 100. In other embodiments, the dummy channel column DVC can also be disposed in the storage cell region CR of the dummy gate stack structure DGS and electrically connected to the source / drain columns 140a, 140b respectively, so that the signal of the bit line BL or the source line SL can be connected to the active device 170 in the substrate 100. In other embodiments, the dummy channel column DVC may also be disposed in the step region SR of the dummy gate stack structure DGS and electrically connected to the conductive layer 110 , so that the signal of the gate line GP of the conductive layer 110 may be connected to the driver 160 in the substrate 100 .

[0121] In summary, in the three-dimensional memory element of the present invention, the conductor layer of at least one of the multiple blocks is isolated from the conductor layers in other blocks, so that when a bias is applied to the conductor layer, the capacitance generated between the conductor layer and the gate layer in other blocks can be ignored, thereby making it easy to control the bias of the conductor layer.

[0122] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any technician with common knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims.

[0123] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A three-dimensional memory element, characterized in that: The method comprises a plurality of block elements, each of which comprises a plurality of blocks, each of which comprises: A gate stack structure is disposed on the substrate and includes a plurality of gate layers electrically insulated from each other; A conductor layer, disposed between the substrate and the gate stack structure; A plurality of first annular channel columns are disposed on the substrate and located in the gate stack structure; A plurality of source / drain columns are disposed on the substrate and two of the source / drain columns are disposed in each of the first annular channel columns; and A plurality of charge storage structures, each of which is disposed between a corresponding gate layer and a corresponding first annular channel column, wherein the conductor layer of one of the plurality of blocks is isolated from the conductor layer of another of the plurality of blocks, and Wherein, the plurality of source / drain columns extend into the conductor layer, so that parts of the plurality of source / drain columns are embedded in the conductor layer.

2. The three-dimensional memory device according to claim 1, characterized in that The conductor layers in two adjacent blocks are spaced apart from each other.

3. The three-dimensional memory element according to claim 2, characterized in that The conductor layers of a plurality of the blocks within the block are spaced apart from each other.

4. The three-dimensional memory device according to claim 1, characterized in that Also includes: A plurality of dummy gate stack structures are disposed on the substrate and are respectively arranged on two opposite sides of the arrangement direction of the plurality of blocks of each of the blocks.

5. The three-dimensional memory device according to claim 4, characterized in that Also includes: A plurality of dummy channel columns are respectively located in the corresponding dummy gate stack structures and extend into the substrate, each of the dummy channel columns includes a second annular channel column and a conductive column located in the second annular channel column, and at least one of the plurality of conductor layers is connected to a driver located in the substrate through the corresponding conductive column.

6. The three-dimensional memory device according to claim 1, characterized in that The first plurality of annular channel pillars extend into the conductor layer to form a plurality of bottom parasitic transistors in the conductor layer together with portions of the plurality of source / drain pillars embedded in the conductor layer.

7. A method for manufacturing a three-dimensional memory element, characterized in that: include: forming a conductor material layer on a substrate; forming a stacking structure on the conductor material layer, the stacking structure comprising a plurality of insulating material layers and a plurality of sacrificial material layers alternately stacked on the substrate; forming a plurality of first annular channel columns in the stacked structure; Forming a plurality of source / drain columns in the stacked structure, and two of the source / drain columns are disposed in each of the first annular channel columns; The stacked structure is subjected to a first patterning process to form a plurality of first trenches penetrating the stacked structure and the conductor material layer, and then the conductor material layer is subjected to a second patterning process to form a plurality of conductor layers, wherein the plurality of first trenches define a plurality of patterned stacked structures and a plurality of conductor layers, each of the patterned stacked structures comprises a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the substrate, and the plurality of conductor layers are located between the substrate and the plurality of patterned stacked structures; wherein the plurality of first trenches define a plurality of blocks; removing a plurality of the sacrificial layers to form a horizontal opening between two adjacent insulating layers; and forming a charge storage structure and a gate layer in the horizontal opening in sequence, wherein the charge storage structure is formed between the gate layer and the corresponding first annular channel column; Wherein, the plurality of source / drain columns extend into the conductor layer, so that parts of the plurality of source / drain columns are embedded in the conductor layer.

8. The method for manufacturing a three-dimensional memory device according to claim 7, characterized in that: The plurality of first channels further define a plurality of blocks included in each of the blocks, each of the blocks comprising the patterned stacked structure and the conductor layer, and the conductor layers of the plurality of blocks in the block are spaced apart from each other.

9. The method for manufacturing a three-dimensional memory device according to claim 7, characterized in that: A plurality of the first trenches define a plurality of blocks, each of the blocks includes a plurality of the patterned stacked structures and the conductor layer, wherein a second trench is formed between two adjacent patterned stacked structures to define a plurality of blocks on the conductor layer.

10. The method for manufacturing a three-dimensional memory device according to claim 7, wherein: Also includes: A dummy channel column is formed in the patterned stack structure and the conductor layer, wherein the dummy channel column includes a second annular channel column and a conductive column in the second annular channel column.

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