Display substrate and manufacturing method thereof, and display panel

Abstract

The present application provides a display substrate and its manufacturing method, and a display panel, which belong to the field of display technology. The display substrate of the present application includes: a semiconductor layer is arranged on a base substrate, and the active layer of the first thin film transistor is located in the semiconductor layer; an insulating layer is arranged on the side of the semiconductor layer away from the base substrate; a first conductive layer is arranged on the side of the insulating layer away from the semiconductor layer, and the source and drain of the first thin film transistor are both located in the first conductive layer, and the source and drain of the first thin film transistor are both transparent electrodes, and are connected to the active layer of the first thin film transistor through interlayer vias penetrating the insulating layer; a display electrode is arranged on the side of the first conductive layer away from the base substrate, and is electrically connected to the source or drain of the first thin film transistor. The embodiments of the present application can greatly improve the aperture ratio and transmittance of the display substrate, thereby greatly improving the display performance of the display product.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] Augmented reality technology and virtual reality technology are new technologies that "seamlessly" integrate real-world information and virtual-world information. Compared with conventional display products, the most obvious feature of augmented reality and virtual reality display products is their ultra-high resolution. With the development of optoelectronic technology and semiconductor manufacturing technology, in display devices, for example, low-temperature polysilicon (LTPS) thin-film transistor liquid crystal displays are different from traditional amorphous silicon thin-film transistor liquid crystal displays. Their electron mobility can reach more than 200cm2 / V-sec, which can effectively reduce the area of thin-film transistor devices, thereby increasing the aperture ratio, and while increasing the brightness of the display, it can also reduce the overall power consumption. However, since augmented reality and virtual reality display products have a higher resolution, it will lead to an increase in metal wiring density and other reasons, resulting in a significant reduction in their aperture ratio and transmittance compared to conventional display products. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a manufacturing method thereof, and a display panel.

[0004] In a first aspect, embodiments of the present application provide a display substrate having a display area, the display substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate and located in the display area; the pixel units comprising a first thin film transistor and a display electrode; wherein the display substrate comprises:

[0005] a semiconductor layer, disposed on the base substrate, wherein the active layer of the first thin film transistor is located on the semiconductor layer;

[0006] an insulating layer, disposed on a side of the semiconductor layer facing away from the substrate;

[0007] a first conductive layer, disposed on a side of the insulating layer facing away from the semiconductor layer, wherein the source and drain of the first thin film transistor are both located in the first conductive layer, and both the source and drain of the first thin film transistor are transparent electrodes and are connected to the active layer of the first thin film transistor via an interlayer via penetrating the insulating layer;

[0008] The display electrode is arranged on a side of the first conductive layer away from the base substrate and is electrically connected to a source electrode or a drain electrode of the first thin film transistor.

[0009] In one embodiment of the present application, the insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer; wherein, the first insulating layer is arranged on the side of the semiconductor layer away from the substrate, the second insulating layer is arranged on the side of the first insulating layer away from the semiconductor layer, and the third insulating layer is arranged on the side of the second insulating layer away from the first insulating layer.

[0010] In one embodiment of the present application, the display substrate further includes a second conductive layer, which is disposed on a side of the first insulating layer away from the base substrate, and the gate of the first thin film transistor is located in the second conductive layer.

[0011] In one embodiment of the present application, it has a non-display area, and the display substrate further includes a driving circuit disposed on the base substrate and located in the non-display area; the driving circuit includes a second thin film transistor; wherein,

[0012] The active layer of the second thin film transistor is located in the semiconductor layer, and the gate is located in the second conductive layer.

[0013] In one embodiment of the present application, the display substrate also includes a third conductive layer, which is arranged on the side of the second insulating layer away from the first insulating layer, the source and drain of the second thin film transistor are both located in the third conductive layer, and the source and drain of the first thin film transistor are electrically connected to the third conductive layer.

[0014] In one embodiment of the present application, the display substrate further includes a planarization layer disposed on a side of the third insulating layer facing away from the base substrate, the planarization layer having a through hole, and an orthographic projection of the through hole on the base substrate overlaps with an orthographic projection of the first thin-film transistor active layer on the base substrate;

[0015] The display electrode includes a first sub-display electrode and a second sub-display electrode. The first sub-display electrode covers the inner wall of the through hole and is electrically connected to the drain of the first thin film transistor. The second sub-display electrode is stacked and spaced apart and arranged on the side of the first sub-display electrode and the planarization layer away from the base substrate.

[0016] In one embodiment of the present application, the display substrate further includes a passivation layer, and the passivation layer is located between the first sub-display electrode and the second sub-display electrode, and between the planarization layer and the second sub-display electrode.

[0017] In one embodiment of the present application, the display substrate further includes a supporting structure, wherein the supporting structure is located on a side of the second sub-display electrode facing away from the passivation layer and is partially located in the through hole.

[0018] In one embodiment of the present application, the display substrate further includes a buffer layer and a light shielding layer disposed between the semiconductor layer and the base substrate;

[0019] The buffer layer is arranged on a side of the semiconductor layer close to the substrate;

[0020] The light shielding layer is arranged on a side of the buffer layer close to the base substrate, and an orthographic projection of the light shielding layer on the base substrate covers an orthographic projection of the active layer on the base substrate.

[0021] In one embodiment of the present application, the semiconductor layer includes a low-temperature polysilicon material, and the first conductive layer includes a transparent metal material or a transparent metal oxide semiconductor material.

[0022] In a second aspect, an embodiment of the present application discloses a method for preparing a display substrate, wherein the display substrate has a plurality of pixel units located in a display area, the pixel units including a first thin film transistor, including:

[0023] providing a substrate;

[0024] forming a semiconductor layer on one side of the base substrate, wherein the active layer of the first thin film transistor is located in the semiconductor layer;

[0025] forming an insulating layer on a side of the semiconductor layer facing away from the substrate;

[0026] forming a first conductive layer made of a transparent metal or a transparent metal oxide semiconductor material on a side of the insulating layer facing away from the semiconductor layer; wherein the first conductive layer includes a source electrode and a drain electrode of a first thin film transistor, and the source electrode and the drain electrode are electrically connected to the active layer of the first thin film transistor;

[0027] A planarization layer and a passivation layer are sequentially formed on the side of the first conductive layer away from the base substrate, and display electrodes are formed on opposite sides of the passivation layer. The display electrodes are electrically connected to the source or drain of the first thin film transistor through a through hole penetrating the planarization layer.

[0028] In one embodiment of the present application, the method for preparing a display substrate further includes: when the first conductive layer is made of a transparent metal oxide semiconductor material, further including a step of conducting the transparent metal oxide semiconductor.

[0029] In a third aspect, an embodiment of the present application provides a display panel, comprising the display substrate provided in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic cross-sectional view of a display substrate provided in an embodiment of the present application;

[0031] Figure 2 A partially enlarged diagram of a display substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0033] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0034] It should be noted that in the embodiments of the present disclosure, the "composition process" refers to the step of forming a structure with a specific pattern, which may be a photolithography process, which includes one or more steps of forming a material layer, coating a photoresist, exposing, developing, etching, and photoresist stripping; of course, the "composition process" may also be other processes such as an imprinting process and an inkjet printing process.

[0035] In order to solve at least one of the above-mentioned technical problems, the embodiment of the present disclosure provides a display substrate and a manufacturing method thereof, and a display panel. The display substrate and a manufacturing method thereof, and the display panel provided by the embodiment of the present disclosure will be further described in detail below in combination with the drawings and specific implementation methods.

[0036] In a first aspect, embodiments of the present application provide a display substrate having a display area, the display substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate and located in the display area; the pixel units comprising a first thin film transistor and a display electrode; the display substrate comprising:

[0037] A semiconductor layer is provided on the base substrate, and the active layer of the first thin film transistor is located in the semiconductor layer;

[0038] an insulating layer, disposed on a side of the semiconductor layer facing away from the substrate;

[0039] a first conductive layer, disposed on a side of the insulating layer facing away from the semiconductor layer, wherein the source and drain of the first thin film transistor are both located in the first conductive layer, and both the source and drain of the first thin film transistor are transparent electrodes and are connected to the active layer of the first thin film transistor via an interlayer via penetrating the insulating layer;

[0040] The display electrode is arranged on a side of the first conductive layer away from the base substrate and is electrically connected to the source electrode or the drain electrode of the first thin film transistor.

[0041] like Figure 1 As shown, the display substrate has a display area AA and a non-display area NA. The display substrate includes a base substrate 21 and a plurality of pixel units located on the base substrate 21, each pixel unit including at least one first thin film transistor T1.

[0042] The display substrate includes a base substrate 21, a semiconductor layer 22, an insulating layer 23, and a first conductive layer 24. The semiconductor layer 22 is disposed on the base substrate 21, and the active layer of the first thin-film transistor T1 is located on the semiconductor layer 22. The insulating layer 23 includes a layer disposed on a side of the active layer of the first thin-film transistor T1 facing away from the base substrate 21. The first conductive layer 24 is disposed on a side of the insulating layer 23 facing away from the active layer of the first thin-film transistor T1. The source and drain of the first thin-film transistor T1 can both be transparent electrodes and are located on the first conductive layer 24. The source and drain of the first thin-film transistor T1 are both connected to the active layer of the first thin-film transistor T1. The display electrode 3 can be disposed on a side of the first conductive layer 24 facing away from the base substrate 21. For example, a conductive layer is formed on the side of the first conductive layer 24 facing away from the base substrate 21. The display electrode 3 is formed on the conductive layer and is electrically connected to the source or drain of the first thin-film transistor T1, but the embodiments of the present application are not limited to this.

[0043] The base substrate 21 can be a flexible base substrate to enhance the flexibility of the display substrate, enabling the display substrate to have bendable and foldable properties, thereby expanding the application range of the display substrate. However, the base substrate 21 is not limited to this and can also be rigid. The specific performance of the base substrate 21 can be determined based on the actual requirements of the display product. In addition, the base substrate 21 can have a single-layer structure or a multi-layer structure. It should be noted that the structure of the base substrate 21 is not limited to this and can be determined based on actual requirements.

[0044] The insulating layer 23 may be a single-layer structure or a multi-layer structure, which is not specifically limited herein. The material of the insulating layer 23 includes, but is not limited to, silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), or a multilayer film composed of two or three of these.

[0045] The first conductive layer 24 can be a single-layer structure or a multi-layer structure, which is not specifically limited here. The first conductive layer 24 can be made of a transparent metal material or a transparent metal oxide semiconductor (such as indium gallium zinc oxide or tin dioxide) material to avoid dense metal wiring and thus reduce the aperture ratio and transmittance, thereby improving the aperture ratio and transmittance of the embodiment of the present application, and further improving the performance of the display product.

[0046] The material of the semiconductor layer 22 (i.e., the material of the active layer of the first thin-film transistor T1) can be selected according to the circumstances. For example, the material of the semiconductor layer 22 is low-temperature polycrystalline silicon, so that the embodiment of the present application can be applied to augmented reality and virtual reality display products. However, the embodiment of the present application is not limited to this. For example, the material of the semiconductor layer 22 can also be polycrystalline silicon, amorphous silicon, oxide semiconductor, etc.

[0047] In the embodiment of the present application, a transparent metal material or a transparent metal oxide semiconductor material is used, so that the source and drain of the first thin film transistor are both transparent electrodes. Compared with the method of directly using metal wiring in the prior art, the aperture ratio and transmittance of the display substrate can be greatly improved, thereby greatly improving the display performance of the display product.

[0048] In one embodiment of the present application, Figure 1 As shown, the insulating layer 23 includes a first insulating layer 231, a second insulating layer 232, and a third insulating layer 233; wherein the first insulating layer 231 is disposed on the side of the semiconductor layer 22 facing away from the substrate 21, the second insulating layer 232 is disposed on the side of the first insulating layer 231 facing away from the semiconductor layer 22, and the third insulating layer 233 is disposed on the side of the second insulating layer 232 facing away from the first insulating layer 231. Specifically, the insulating layer 23 can have a multilayer structure and specifically include the first insulating layer 231, the second insulating layer 232, and the third insulating layer 233. For example, the first insulating layer 231, the second insulating layer 232, and the third insulating layer 233 are sequentially formed on the side of the semiconductor layer 22 facing away from the substrate 21, but the embodiment of the present application is not limited to this. Optionally, the gate of the first thin-film transistor T1 is disposed between the first insulating layer 231 and the second insulating layer 232, thereby simplifying the structure of the embodiment of the present application and significantly reducing the number of process steps, thereby saving manufacturing costs. Optionally, materials of the first insulating layer 231 , the second insulating layer 232 and the third insulating layer 233 include but are not limited to acrylic acid, transparent resin and the like.

[0049] In one embodiment of the present application, Figure 1As shown, the display substrate further includes a second conductive layer 25, which is disposed on the side of the first insulating layer 231 facing away from the base substrate 21. The gate of the first thin-film transistor T1 is located in the second conductive layer 25. Specifically, the first insulating layer 231 is located on the side of the semiconductor layer 22 facing away from the base substrate 21. The second insulating layer 232 and the third insulating layer 233 are sequentially located on the side of the first insulating layer 231 facing away from the base substrate 21. The second conductive layer 25 is formed on the side of the first insulating layer 231 facing away from the base substrate 21, that is, the second conductive layer 25 is located between the first insulating layer 231 and the second insulating layer 232. The second conductive layer 25 includes the gate of the first thin-film transistor T1. The material of the second conductive layer 25 can be a single layer or a multi-layer composite laminate formed of one or more materials selected from molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti), and copper (Cu).

[0050] In one embodiment of the present application, Figure 1 As shown, the display substrate further has a non-display area NA, and the display substrate further includes a driving circuit disposed on the base substrate 21 and located in the non-display area NA; the driving circuit includes a second thin-film transistor T2; wherein the active layer of the second thin-film transistor T2 is located in the semiconductor layer 22, and the gate is located in the second conductive layer 25. Specifically, the active layer of the second thin-film transistor T2 is located in the semiconductor layer 22, i.e., the active layer of the second thin-film transistor T2 is located in the same layer and made of the same material as the active layer of the first thin-film transistor T1. The gate of the second thin-film transistor T2 is located in the second conductive layer 25, i.e., the gate of the second thin-film transistor T2 is located in the same layer and made of the same material as the gate of the first thin-film transistor T1. Optionally, the driving circuit includes, but is not limited to, a gate driving circuit. Furthermore, because the active layer and gate of the second thin-film transistor T2 are in the same layer and made of the same material as the active layer and gate of the first thin-film transistor T1, the active layer of the second thin-film transistor T2 and the active layer of the first thin-film transistor T1 can be formed simultaneously through a single patterning process, and a first insulating layer 231 is formed on both. Then, a single patterning process is used to simultaneously form the gate of the second thin-film transistor T2 and the gate of the first thin-film transistor T1. This design can reduce process steps and save manufacturing costs. However, the embodiments of the present application are not limited to this, and those skilled in the art may adjust the configuration based on actual conditions.

[0051] In one embodiment of the present application, Figure 1As shown, the display substrate further includes a third conductive layer 26, which is disposed on the side of the second insulating layer 232 facing away from the first insulating layer 231. The source and drain of the second thin-film transistor T2 are both located in the third conductive layer 26, and the source and drain of the first thin-film transistor T1 are electrically connected to the third conductive layer 26. Specifically, the third conductive layer 26 is disposed on the side of the second insulating layer 232 facing away from the first insulating layer 231, that is, the third conductive layer 26 can be located between the second insulating layer 232 and the third insulating layer 233. The source and drain of the second thin-film transistor T2 are both located in the third conductive layer 26, and the data line 213 located on the base substrate 21 is also located in the third conductive layer 26. With this design, the source and drain of the second thin-film transistor T2 are located in the same layer and made of the same material. Therefore, the source and drain of the second thin-film transistor T2 and the data line 213 can be formed simultaneously in a single patterning process, thereby reducing process steps and saving manufacturing costs. The material of the third conductive layer 26 can be a single layer or a multi-layer composite laminate formed by one or more materials selected from molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (Al), aluminum-neodymium alloy (AlNd), titanium (Ti) and copper (Cu). Figure 2 As shown, the active layer 51 of the first thin film transistor T1 is located between two parallel data lines 213, wherein the source 52 of the first thin film transistor T1 can be connected to the data line 213 on the left. Since the source 52 of the first thin film transistor T1 is made of a transparent metal material or a transparent metal oxide material, the aperture ratio and transmittance of the embodiment of the present application can be improved.

[0052] In one embodiment of the present application, Figure 1 As shown, the display substrate also includes a planarization layer 27 arranged on the side of the third insulating layer 233 away from the base substrate 21, and the planarization layer 27 has a through hole H. The orthographic projection of the through hole H on the base substrate 21 overlaps with the orthographic projection of the active layer of the first thin film transistor T1 on the base substrate 21; the display electrode 3 includes a first sub-display electrode 31 and a second sub-display electrode 32, the first sub-display electrode 31 covers the inner peripheral wall of the through hole H and is electrically connected to the drain of the first thin film transistor T1, and the second sub-display electrode 32 is stacked and spaced apart and arranged on the side of the first sub-display electrode 31 and the planarization layer 27 away from the base substrate 21.

[0053] like Figure 1As shown, the display substrate also includes a planarization layer 27, which is located on the side of the third insulating layer 233 away from the base substrate 21, and a through hole H is opened in the third insulating layer 233 corresponding to the first thin film transistor T1, that is, the orthographic projection of the through hole H on the base substrate 21 overlaps with the orthographic projection of the active layer of the first thin film transistor T1 on the base substrate 21. The planarization layer 27 can be a single-layer structure or a multi-layer structure, which is not specifically limited here. The material of the planarization layer 27 includes but is not limited to silicon oxide (SiOx), silicon nitride (SiNx), hafnium oxide (HfOx), silicon oxynitride (SiON), aluminum oxide (AlOx), etc., or a multilayer film composed of two or three of them. The display electrode 3 includes a first sub-display electrode 31 and a second sub-display electrode 32. The first sub-display electrode 31 has a layered structure and covers the outer periphery and inner wall of the top of the through-hole H. The bottom surface of the first sub-display electrode 31 located within the through-hole H is directly electrically connected to the top surface of the drain electrode of the first thin-film transistor T1. The second sub-display electrode 32 covers the planarization layer 27 and the side of the first sub-display electrode 31 facing away from the base substrate 21, and the second sub-display electrode 32 is electrically connected to the first sub-display electrode 31. Optionally, the material of the display electrode 3 is ITO (indium tin oxide). This design can effectively ensure display uniformity, thereby improving display efficiency.

[0054] In one embodiment of the present application, Figure 1 As shown, the display substrate also includes a passivation layer 28, which is located between the first sub-display electrode 31 and the second sub-display electrode 32, and between the planarization layer 27 and the second sub-display electrode 32. Specifically, the display substrate also includes a passivation layer 28, which is made of an insulating material and is located on the side of the planarization layer 27 facing away from the base substrate 21. Because the first sub-display electrode 31 is relatively short, the passivation layer 28 covers the planarization layer 27 and the first sub-display electrode 31, and is located between the second sub-display electrode 32 and the planarization layer 27 and the first sub-display electrode 31. During operation of the display panel, a voltage is applied to the display electrode 3 to generate an electric field, thereby controlling the deflection of the liquid crystal and achieving the display function. The above design can save process steps and thus reduce manufacturing costs.

[0055] In one embodiment of the present application, Figure 1As shown, the display substrate further includes a support structure 4, which is located on the side of the second sub-display electrode 32 away from the passivation layer 28, and is partially located in the through hole H. Specifically, the support structure 4 can be formed on the side of the second sub-display electrode 32 away from the passivation layer 28, and the bottom of the support structure 4 is filled in the groove formed in the through hole H of the second sub-display electrode 32, that is, the support structure 4 can be partially located in the through hole H. The support structure 4 serves as a columnar spacer supporting the opposing substrate. The shape of the support structure 4 can be selected according to the situation and is not specifically limited here. Preferably, the shape of the support structure 4 is block-shaped. The support structure 4 can be formed using a one-time patterning process, thereby saving process steps and saving manufacturing costs.

[0056] In one embodiment of the present application, Figure 1 As shown, the display substrate further includes a buffer layer 211 and a light shielding layer 212 disposed between the semiconductor layer 22 and the base substrate 21. The buffer layer 211 is disposed on the side of the semiconductor layer 22 closest to the base substrate 21. The light shielding layer 212 is disposed on the side of the buffer layer 211 closest to the base substrate 21, and the orthographic projection of the light shielding layer 212 on the base substrate 21 covers the orthographic projection of the active layer on the base substrate 21. Specifically, the display substrate further includes the buffer layer 211 and the light shielding layer 212. The buffer layer 211 covers the base substrate 21, and the semiconductor layer 22 is disposed on the side of the buffer layer 211 facing away from the base substrate 21 to prevent harmful substances from affecting the performance of the semiconductor layer 22. The light shielding layer 212 can be disposed between the base substrate 21 and the buffer layer 211. The orthographic projection of the light shielding layer 212 on the base substrate 21 completely covers the orthographic projection of the active layer of the first thin film transistor T1 on the base substrate 21. In this embodiment, a light shielding layer 212 is formed on the side of the buffer layer 211 near the base substrate 21 to prevent light emitted by the backlight from reaching the active layer of the first thin-film transistor T1, thereby preventing damage to the performance of the first thin-film transistor T1 and further preventing display abnormalities. The light shielding layer 212 can be made of a material with light shielding properties, such as copper metal or molybdenum metal, and this embodiment of the application is not limited to this.

[0057] In one embodiment of the present application, Figure 1As shown, the semiconductor layer 22 includes a low-temperature polysilicon material, and the first conductive layer 24 includes a transparent metal material or a transparent metal oxide semiconductor material. Since the semiconductor layer 22 is made of low-temperature polysilicon material, the active layers of the first thin-film transistor T1 and the second thin-film transistor T2 are both made of low-temperature polysilicon material, thereby significantly reducing the thickness of the display substrate of the embodiment of the present application and reducing power consumption. Since the first conductive layer 24 is made of a transparent metal material or a transparent metal oxide semiconductor material, the source electrode of the first thin-film transistor T1 can be made of a conductive transparent metal oxide semiconductor material. Since the conductive transparent metal oxide semiconductor material itself has transparent properties, it can improve the transmittance of high-resolution display products, thereby improving the performance of the display product. Optionally, the transparent metal oxide semiconductor material is, for example, indium gallium zinc oxide (IGZO), so that during sputtering film formation, only a small amount of oxygen needs to be introduced to avoid oxidation of the active layer of the first thin-film transistor T1, thereby preventing the contact resistance between the source and drain electrodes of the first thin-film transistor T1 and the active layer from being affected, thereby improving the performance of the display product.

[0058] In a second aspect, an embodiment of the present application provides a method for manufacturing a display substrate, wherein the display substrate includes a plurality of pixel units in a display area, the pixel units including a first thin film transistor T1, including:

[0059] S1. Provide a substrate.

[0060] S2. Form a semiconductor layer on one side of the base substrate, wherein the active layer of the first thin film transistor is located in the semiconductor layer.

[0061] S3. Form an insulating layer on the side of the semiconductor layer facing away from the substrate.

[0062] S4. Form a first conductive layer made of transparent metal or transparent metal oxide semiconductor material on the side of the insulating layer away from the semiconductor layer; wherein the first conductive layer includes a source and a drain of a first thin film transistor, and the source and the drain are electrically connected to the active layer of the first thin film transistor.

[0063] S5. A planarization layer and a passivation layer are sequentially formed on the side of the first conductive layer facing away from the base substrate, and display electrodes are formed on opposite sides of the passivation layer. The display electrodes are electrically connected to the source or drain of the first thin film transistor through a through hole penetrating the planarization layer.

[0064] In the embodiment of the present application, a transparent metal material or a transparent metal oxide semiconductor material is used, so that the source and drain of the first thin film transistor are both transparent electrodes. Compared with the method of directly using metal wiring in the prior art, the aperture ratio and transmittance of the display substrate can be greatly improved, thereby greatly improving the display performance of the display product.

[0065] In one embodiment of the present application, Figure 1 As shown, when the first conductive layer uses a transparent metal oxide semiconductor material, the process also includes a step of conducting the transparent metal oxide semiconductor. The transparent metal oxide semiconductor material, for example, is indium gallium zinc oxide (IGZO). By conducting the material, the transparent metal oxide semiconductor material becomes transparent. Since the conductive transparent metal oxide semiconductor material is transparent, the transmittance of high-resolution display products can be increased, thereby improving the performance of the display products.

[0066] In a third aspect, embodiments of the present application provide a display panel comprising the display substrates provided in the aforementioned embodiments. The display panel can be applied to any product or component with a display function, such as augmented reality displays, virtual reality displays, mobile phones, tablet computers, televisions, laptop computers, and navigation systems.

[0067] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate having a display area, the display substrate comprising a base substrate and a plurality of pixel units disposed on the base substrate and located in the display area; The pixel unit includes a first thin film transistor and a display electrode; characterized in that: The display substrate comprises: a semiconductor layer, disposed on the base substrate, wherein the active layer of the first thin film transistor is located on the semiconductor layer; an insulating layer, disposed on a side of the semiconductor layer facing away from the substrate; the insulating layer comprises a first insulating layer, a second insulating layer, and a third insulating layer; wherein the first insulating layer is disposed on a side of the semiconductor layer facing away from the substrate, the second insulating layer is disposed on a side of the first insulating layer facing away from the semiconductor layer, and the third insulating layer is disposed on a side of the second insulating layer facing away from the first insulating layer; a first conductive layer, disposed on a side of the insulating layer facing away from the semiconductor layer, wherein the source and drain of the first thin film transistor are both located in the first conductive layer, and both the source and drain of the first thin film transistor are transparent electrodes and are connected to the active layer of the first thin film transistor via an interlayer via penetrating the insulating layer; a third conductive layer, disposed on a side of the second insulating layer facing away from the first insulating layer; The display electrode is provided on a side of the first conductive layer away from the base substrate and is electrically connected to one of the source electrode or the drain electrode of the first thin film transistor; The display substrate further comprises a non-display area, a data line, and a driving circuit located in the non-display area, wherein the driving circuit comprises a second thin film transistor; a source electrode, a drain electrode, and the data line of the second thin film transistor are all located in the third conductive layer; the other of the source electrode and the drain electrode of the first thin film transistor is connected via a via hole penetrating the third insulating layer; The display substrate further comprises a planarization layer provided on a side of the third insulating layer facing away from the base substrate, the planarization layer having a through hole, an orthographic projection of the through hole on the base substrate overlapping with an orthographic projection of the first thin film transistor active layer on the base substrate; The display electrode includes a first sub-display electrode and a second sub-display electrode, the first sub-display electrode covers the inner peripheral wall of the through hole and is electrically connected to the drain of the first thin film transistor, and the second sub-display electrode is stacked and spaced apart and arranged on a side of the first sub-display electrode and the planarization layer away from the base substrate; The display substrate further includes a passivation layer, wherein the passivation layer is located between the first sub-display electrode and the second sub-display electrode, and between the planarization layer and the second sub-display electrode; The display substrate further includes a supporting structure, which is located on a side of the second sub-display electrode facing away from the passivation layer and is partially located in the through hole.

2. The display substrate according to claim 1, wherein The display substrate further includes a second conductive layer, which is arranged on a side of the first insulating layer away from the base substrate, and the gate of the first thin film transistor is located in the second conductive layer.

3. The display substrate according to claim 2, wherein: The active layer of the second thin film transistor is located in the semiconductor layer, and the gate is located in the second conductive layer.

4. The display substrate according to claim 1, wherein The display substrate further includes a buffer layer and a light shielding layer disposed between the semiconductor layer and the base substrate; The buffer layer is arranged on a side of the semiconductor layer close to the substrate; The light shielding layer is arranged on a side of the buffer layer close to the base substrate, and an orthographic projection of the light shielding layer on the base substrate covers an orthographic projection of the active layer on the base substrate.

5. The display substrate according to any one of claims 1 to 4, wherein: The semiconductor layer includes a low-temperature polysilicon material, and the first conductive layer includes a transparent metal material or a transparent metal oxide semiconductor material.

6. A method for preparing a display substrate, wherein the display substrate is the display substrate according to any one of claims 1 to 5; the display substrate comprises a plurality of pixel units located in a display area, the pixel units comprising a first thin film transistor, wherein: The preparation method comprises: providing a substrate; forming a semiconductor layer on one side of the base substrate, wherein the active layer of the first thin film transistor is located in the semiconductor layer; forming an insulating layer on a side of the semiconductor layer facing away from the substrate; forming a first conductive layer made of a transparent metal or a transparent metal oxide semiconductor material on a side of the insulating layer facing away from the semiconductor layer; wherein the first conductive layer includes a source electrode and a drain electrode of a first thin film transistor, and the source electrode and the drain electrode are electrically connected to the active layer of the first thin film transistor; A planarization layer and a passivation layer are sequentially formed on the side of the first conductive layer away from the base substrate, and display electrodes are formed on opposite sides of the passivation layer. The display electrodes are electrically connected to the source or drain of the first thin film transistor through a through hole penetrating the planarization layer.

7. The method for preparing a display substrate according to claim 6, wherein: The display substrate preparation method further includes: When the first conductive layer is made of a transparent metal oxide semiconductor material, the method further includes a step of conducting the transparent metal oxide semiconductor.

8. A display panel, characterized in that: The display substrate comprises the display substrate according to any one of claims 1 to 5.

Images