Resistive memory cell and related memory cell array structure

Abstract

The present invention discloses a resistive memory cell and a related memory cell array structure, wherein the memory cell array structure has a first resistive memory cell. The first resistive memory cell includes: a well region, a first doped region, a merged region, a first gate structure, a second gate structure and a first metal layer. The first doped region and the merged region are formed below the surface of the well region, and the first gate structure is formed above the surface of the well region between the doped region and the merged region. The first gate structure includes a first insulating layer located on a first conductive layer. The second gate structure is formed above the merged region. The second gate structure includes a second insulating layer located on the second conductive layer. The first metal layer is connected to the first doped region.

Description

Technical Field

[0001] The present invention relates to a memory cell, and in particular to a bipolar operation mode resistive memory cell and a related memory cell array structure. Background Art

[0002] Resistive random-access memory (ReRAM) is a non-volatile memory that consists of multiple ReRAM cells. Since ReRAM has fewer manufacturing steps and faster write speed, it is very suitable to replace embedded flash memory in system-on-chip (SOC).

[0003] Please refer to Figure 1 , which shows a conventional resistive memory cell. Figure 1 As shown, the resistive memory cell 100 includes a stacked lower electrode 106, an insulating layer 104, and an upper electrode 102. After the resistive memory is manufactured, it is in an initial state.

[0004] Before the resistive memory cell 100 begins to operate, a forming action is required. During the forming action, the upper electrode 102 and the lower electrode 106 receive a first voltage Va and a second voltage Vb respectively, and the voltage difference Vab is the forming voltage. The voltage difference Vab is equal to the first voltage Va minus the second voltage Vb (Vab=Va-Vb). When the upper electrode 102 and the lower electrode 106 receive the forming voltage, the oxygen vacancies gathered in the insulating layer 104 will form a conducting filament 108, and the conducting filament 108 is connected between the upper electrode 102 and the lower electrode 106.

[0005] After the resistive memory cell 100 is formed, multiple bias voltages lower than the forming voltage are further provided, so that the resistive memory cell 100 can be switched between a set state and a reset state at will. The resistive memory cell 100 has a smaller resistance value in the set state and a larger resistance value in the reset state. This is described below.

[0006] In the set state of low resistance value, the resistive memory cell 100 can be changed to the reset state of high resistance value through a reset action. During the reset action, a reset voltage is provided between the upper electrode 102 and the lower electrode 106. At this time, the crack 108 in the insulating layer 104 undergoes a redox process, and the crack 108 is almost not connected between the upper electrode 102 and the lower electrode 106. That is, after the reset action is completed, the upper electrode 102 and the lower electrode 106 are in the reset state of high resistance value.

[0007] In the reset state of the high resistance value, the resistive memory cell 100 can be changed to the set state of the low resistance value through a set action. During the set action, a set voltage is provided between the upper electrode 102 and the lower electrode 106. At this time, the crack 108 in the insulating layer 104 will be completely connected between the upper electrode 102 and the lower electrode 106. That is, after the set action is completed, the upper electrode 102 and the lower electrode 104 are in the set state of the low resistance value.

[0008] As can be seen from the above description, during a program action in a program cycle, the resistive memory cell 100 can be in a set state or a reset state through a set action or a reset action. The set state and the reset state are two storage states of the resistive memory cell 100.

[0009] Basically, according to the method of providing the set voltage and the reset voltage, the resistive memory cell 100 can be divided into a resistive memory cell 100 in a unipolar operation mode and a resistive memory cell 100 in a bipolar operation mode. The so-called unipolar operation mode is to use a positive voltage difference Vab to perform a set operation and a reset operation on the resistive memory cell 100, or to use a negative voltage difference Vab to perform a set operation and a reset operation on the resistive memory cell 100. In addition, the so-called bipolar operation mode is to use a positive voltage difference Vab to perform a set operation on the resistive memory cell 100 and use a negative voltage difference Vab to perform a reset operation on the resistive memory cell 100, or to use a negative voltage difference Vab to perform a set operation on the resistive memory cell 100 and use a positive voltage difference Vab to perform a reset operation on the resistive memory cell 100. The positive voltage difference Vab represents that the first voltage Va minus the second voltage Vb is greater than zero (Vab=Va-Vb>0), and the negative voltage difference Vab represents that the first voltage Va minus the second voltage Vb is less than zero (Vab=Va-Vb<0).

[0010] Please refer to Figure 2A and Figure 2B , which is a schematic diagram of bias voltages of a resistive memory cell in a unipolar operation mode and a resistive memory cell in a bipolar operation mode.

[0011] like Figure 2A As shown by the dotted line in FIG. 1 , when the resistive memory cell 100 is in the reset state, after the setting voltage of about 1.88V is provided, the current flowing through the resistive memory cell 100 increases, that is, the resistance value of the resistive memory cell 100 decreases and becomes the set state. Figure 2A As shown by the solid line in FIG, when the resistive memory cell 100 is in the set state, after the reset voltage of about 1.78V is provided, the current flowing through the resistive memory cell 100 decreases, that is, the resistance value of the resistive memory cell 100 increases and becomes the reset state. Figure 2A In the embodiment, two different positive voltage differences Vab (ie, 1.78V and 1.88V) are used to perform a reset operation and a set operation on the resistive memory cell 100 , which is the resistive memory cell 100 in a unipolar operation mode.

[0012] like Figure 2BAs shown by the dotted line in , when the resistive memory cell 100 is in the reset state, after the setting voltage of about -2.4V is provided, the current flowing through the resistive memory cell 100 increases, the resistance value of the resistive memory cell 100 decreases, and becomes the set state. Figure 2B As shown by the solid line in FIG, when the resistive memory cell 100 is in the set state, after the reset voltage of about 1.5V is provided, the current flowing through the resistive memory cell 100 decreases, that is, the resistance value of the resistive memory cell 100 increases and becomes the reset state. Figure 2B In the embodiment, a positive voltage difference Vab (ie, 1.5V) and a negative voltage difference Vab (ie, -2.4V) are used to perform a reset operation and a set operation on the resistive memory cell 100. This is the resistive memory cell 100 in a bipolar operation mode.

[0013] Depend on Figure 2A and Figure 2B It can be seen from the contents of FIG. 1 that the reset voltage of the resistive memory cell 100 in the unipolar operation mode is very close to the set voltage and is not easy to control. The reset voltage of the resistive memory cell 100 in the bipolar operation mode is far away from the set voltage and is easy to control. Summary of the invention

[0014] The main purpose of the present invention is to provide a resistive memory cell with bipolar operation. In addition, in the resistive memory cell, the lower electrode below the insulating layer is implemented by an implanted region. Furthermore, the present invention further utilizes the resistive memory cell to form a memory cell array structure.

[0015] The present invention relates to an array structure of a resistive memory cell. The array structure has a first resistive memory cell. The first resistive memory cell includes: a first-type well region; a first doped region formed below a surface of the first-type well region, and the first doped region is a second-type doped region; a second-type merged region formed below the surface of the first-type well region; a first gate structure formed above the surface of the first-type well region between the first doped region and the second-type merged region, wherein the first gate structure includes a first insulating layer stacked on a first conductive layer, and the first conductive layer serves as a first character line; a second gate structure formed above the second-type merged region, wherein the second gate structure includes a second insulating layer stacked on a second conductive layer, and the second conductive layer serves as a A first source line; and a first metal layer connected to the first doped region, and the first metal layer serves as a first bit line; wherein, in a forming action, the first source line receives a forming voltage, the first character line receives a turn-on voltage, the first bit line receives a ground voltage, and the second insulating layer forms a conductive crack; wherein, in a reset action, the first source line receives a reset voltage, the first character line receives the turn-on voltage, and the first bit line receives a first voltage less than the reset voltage, so that the first resistive memory unit is in a reset state; wherein, in a setting action, the first character line receives the turn-on voltage, the first bit line receives a setting voltage, and the first source line receives a second voltage less than the setting voltage, so that the first resistive memory unit is in a setting state.

[0016] In order to better understand the above and other aspects of the present invention, the following is a detailed description of the preferred embodiments with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a conventional resistive memory cell;

[0018] Figure 2A and Figure 2B A schematic diagram of bias voltages of a resistive memory cell in a unipolar operation mode and a resistive memory cell in a bipolar operation mode;

[0019] FIG. 3A to FIG. 3C is a flow chart of a method for manufacturing a resistive memory cell according to a first embodiment of the present invention;

[0020] Figure 3D is an equivalent circuit diagram of a resistive memory cell according to a first embodiment of the present invention;

[0021] Figure 4 is a structural diagram of an array composed of resistive memory cells according to the first embodiment;

[0022] FIG. 5A to FIG. 5CSchematic diagram of bias voltage for various actions of the array structure of the present invention;

[0023] FIG. 6A to FIG. 6C is a flow chart of a method for manufacturing a resistive memory cell according to a second embodiment of the present invention;

[0024] FIG. 7A to FIG. 7C is a flow chart of a method for manufacturing a resistive memory cell according to a third embodiment of the present invention;

[0025] Figure 8 is a schematic diagram of a resistive memory cell according to a fourth embodiment of the present invention;

[0026] Fig.9A and Fig. 9B A resistive memory cell and its equivalent circuit diagram according to a fifth embodiment of the present invention;

[0027] Fig.10 is a structural diagram of an array composed of resistive memory cells according to the fifth embodiment; and

[0028] FIG. 11A to FIG. 11C Schematic diagram of bias voltage when the array structure of the present invention performs various actions.

[0029] Explanation of symbols

[0030] 100,200,600,700,701,800,801,900: Resistive memory cell

[0031] 102: Upper electrode

[0032] 104,252,262,652,662,752,762,772,952,962,972: Insulation layer

[0033] 106: Lower electrode

[0034] 108: Conductive Cracks

[0035] 210,710,712: N-type injection area

[0036] 221,222,223,621,622,623,721,722,723,724,921,922,923,924: Doped regions

[0037] 229,629,728,729,929:Metal layer

[0038] 250,260,650,660,750,760,770,860,890,950,960,970: Gate structure

[0039] 255,265,655,665,755,765,775,865,895,955,965,975: Conductive layer

[0040] 300,999: Storage cell array structure

[0041] 624,625: Lightly doped drain region

[0042] 702: Isolation Structure DETAILED DESCRIPTION

[0043] Please refer to FIG. 3A to FIG. 3C , which is a flow chart of a method for manufacturing a resistive memory cell according to a first embodiment of the present invention. In addition, Figure 3D FIG. 4 is an equivalent circuit of the resistive memory cell according to the first embodiment of the present invention.

[0044] like Figure 3A As shown, an N-type implanted region 210 is formed in the P-type well region PW.

[0045] Then, if Figure 3B As shown, two gate structures 250 and 260 are formed, the first gate structure 250 is formed on the surface of the P-type well region PW, and the second gate structure 260 is formed on the surface of the N-type implant region 210. Each gate structure 250 and 260 has the same structure.

[0046] Furthermore, the first gate structure 250 includes an insulating layer 252 and a conductive layer 255, and the second gate structure 260 includes an insulating layer 262 and a conductive layer 265. Taking the second gate structure 260 as an example, the insulating layer 262 is located above the surface of the N-type implantation region 210, and the conductive layer 265 is located above the insulating layer 262. Basically, the conductive layer 265 located above the insulating layer 262 is the upper electrode, and the N-type implantation region 210 located below the insulating layer 262 is the lower electrode. Furthermore, the conductive layer 255 can be used as a word line WL, and the conductive layer 265 can be used as a source line SL.

[0047] According to an embodiment of the present invention, the insulating layer 262 is formed by stacking multiple material layers, and the conductive layer 265 is formed by stacking multiple material layers. For example, the insulating layer 262 includes a silicon dioxide layer (SiO 2 ) and the hafnium dioxide layer (HfO 2 ); the conductive layer 265 includes a titanium layer (Ti), a titanium nitride layer (TiN) and a tungsten layer (W). Among them, hafnium dioxide (HfO 2 ) is a high-k material layer, which is suitable for resistive memory.2 ) is located above the surface of the N-type implantation region 210, and the hafnium dioxide layer (HfO 2 ) is located in the silicon dioxide layer (SiO 2 ), the titanium layer (Ti) is located above the hafnium dioxide layer (HfO 2 ), a titanium nitride layer (TiN) is located above the titanium layer (Ti), and a tungsten layer (W) is located above the titanium nitride layer (TiN).

[0048] Of course, the present invention is not limited to the gate structure of the above-mentioned material stack. Those skilled in the art can also modify the above-mentioned material layer and achieve the purpose of the present invention. For example, the high dielectric constant material layer in the insulating layer 262 can be made of tantalum oxide (Ta 2 O 5 In addition, the conductive layer 265 can also be modified to be formed by stacking a titanium layer (Ti) and a tungsten layer (W).

[0049] like Figure 3C As shown, a doping process is performed to form an N-type first doping region 221, a second doping region 222, and a third doping region 223 below the exposed surface of the P-type well region PW. Therefore, the first gate structure 250 is located above the surface of the P-type well region PW between the first doping region 221 and the second doping region 222, and the second gate structure 260 is located above the surface of the N-type injection region 210 between the second doping region 222 and the third doping region 223. In other words, the insulating layer 262 of the second gate structure 260 is formed between the conductive layer 265 and the N-type injection region 210, and the insulating layer 262 contacts the N-type injection region 210. In addition, the second doping region 222, the third doping region 223 and the N-type injection region 210 overlap with each other and form an N-type merged region. In other words, the second gate structure 260 is located above the N-type merged region, the insulating layer 262 contacts the N-type merged region, and the N-type merged region located below the insulating layer 262 is the lower electrode.

[0050] Next, a metal layer 229 is formed to connect to the first doped region 221 via a contact hole, and the resistive memory cell 200 of the present invention is completed. The metal layer 229 serves as the bit line BL of the resistive memory cell 200 .

[0051] like Figure 3CAs shown, in the P-type well region PW, the first doping region 221, the second doping region 222 and the first gate structure 250 form a first transistor T1; the second doping region 222, the third doping region 223 and the second gate structure 260 form a second transistor T2. Furthermore, since the second doping region 222, the third doping region 223 and the N-type injection region 210 form an N-type merged region, the two drain / source terminals and the body terminal of the second transistor T2 can be regarded as being connected to each other. In addition, a PN junction (pn junction) is formed between the N-type merged region and the P-type well region PW, which can be regarded as a diode.

[0052] like Figure 3D As shown, the resistive memory cell 200 includes two transistors T1 and T2 and a diode D. The first drain / source terminal of the first transistor T1 is connected to the bit line BL, and the gate terminal of the first transistor T1 is connected to the word line WL. Furthermore, the first drain / source terminal, the second drain / source terminal and the body terminal of the second transistor T2 are connected to each other, the first drain / source terminal of the second transistor T2 is connected to the second drain / source terminal of the first transistor T1, and the gate terminal of the second transistor T2 is connected to the source line SL. In addition, the first terminal of the diode D is connected to the body terminal of the second transistor T2, and the second terminal of the diode D is connected to the body terminal of the first transistor T1.

[0053] Furthermore, a plurality of resistive memory cells can form an array structure of resistive memory cells. Figure 4 , which shows an array structure composed of resistive memory cells. The memory cell array structure 300 is composed of 2×2 resistive memory cells c11-c22. The structure of each resistive memory cell c11-c22 is the same as Figure 3C and Figure 3D Of course, the present invention is not limited to the memory cell array structure 300 of 2×2 resistive memory cells c11-c22. A person skilled in the art can form an array structure of m×n resistive memory cells according to the description of the present invention, where m and n are positive integers.

[0054] like Figure 4 As shown, in the memory cell array structure 300, the two resistive memory cells c11-c12 in the first column are connected to the word line WL1 and the source line SL1, and the two resistive memory cells c11-c12 in the first column are connected to the corresponding bit lines BL1 and BL2. Furthermore, the two resistive memory cells c21-c22 in the second column are connected to the word line WL2 and the source line SL2, and the two resistive memory cells c11-c12 in the second column are connected to the corresponding bit lines BL1 and BL2.

[0055] Furthermore, by providing appropriate bias voltages to the word lines WL1-WL2, source lines SL1-SL2, and bit lines BL1-BL2 of the memory cell array structure 300, the resistive memory cells c21-c22 can be formed, reset, and set, as described in detail below.

[0056] Please refer to FIG. 5A to FIG. 5C , which is a schematic diagram of bias voltages for various actions of the array structure of the present invention. In which, each time the memory cell array structure 300 is operated, one word line will be operated to determine a selected row, and the other word lines are unselected rows.

[0057] After the memory cell array structure 300 is manufactured, the resistive memory cells c11-c22 are all in an initial state, so a forming action is required first. Figure 5A As shown, it is a schematic diagram of the bias voltage of the array structure during the forming action.

[0058] During the forming operation, the word line WL1 receives the on voltage (Von), the word line WL2 receives the off voltage (Voff), the source line SL1 receives the forming voltage (Vform), the source line SL2 receives the ground voltage (0V), the bit line BL1 receives the ground voltage (0V), and the bit line BL2 receives the inhibit voltage (Vinh_r). Therefore, in the memory cell array structure 300, the first column connected to the word line WL1 is the selected column, and the second column connected to the word line WL2 is the unselected column. Among them, the forming voltage (Vform), the on voltage (Von) and the inhibit voltage (Vinh_r) are all positive voltages, the forming voltage (Vform) is greater than the on voltage (Von), and the forming voltage (Vform) is greater than or equal to the inhibit voltage (Vinh_r). For example, the forming voltage (Vform) is 4V, the on voltage (Von) is 2V, the inhibit voltage (Vinh_r) is 2V, and the off voltage (Voff) is the ground voltage (0V).

[0059] In the selected column, since the source line SL1 receives the forming voltage (Vform) and the bit line BL1 is at the ground voltage (0V), the memory cell c11 is the selected memory cell. In addition, since the bit line BL2 receives the inhibiting voltage (Vinh_r), the memory cell c12 is the unselected memory cell. Furthermore, in the unselected column, since the word line WL2 receives the off voltage (Voff), the memory cells c21 and c22 are the unselected memory cells.

[0060] In the selected memory cell c11, the first transistor T1 is turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the forming voltage (Vform), and a forming current I is generated between the source line SL1 and the bit line BL1. f When the current I f When the second transistor T2 passes through the insulating layer, a conductive crack can be formed in the insulating layer. Similarly, other resistive memory cells c12 to c22 can also be formed using a similar biasing method. This will not be repeated here.

[0061] Furthermore, if the forming current I generated by the forming action f If it is too large, the insulating layer in the selected memory cell c11 may be burned out. When the insulating layer in the selected memory cell c11 is burned out, the selected memory cell c11 will no longer be able to switch its state. In order to prevent the current I f The current I is too large to cause the insulating layer in the selected memory cell c11 to burn out. The present invention can connect a current limiter to the source line SL1 or the bit line BL1 of the selected memory cell c11 to limit the current I f to prevent the insulating layer in the selected memory cell c11 from being burned.

[0062] like Figure 5B , which is a bias diagram of the array structure performing a reset operation. In this example, in order to comply with the bipolar operation mode, the selected memory cell c11 uses a positive voltage difference to perform a reset operation, so the voltage on the source line SL1 (V SL1 ) minus the voltage on bit line BL1 (V BL1) is greater than zero. For example, during a reset operation, the word line WL1 receives an on voltage (Von), the word line WL2 receives an off voltage (Voff), the source line SL1 receives a reset voltage (Vreset), the source line SL2 receives a ground voltage (0V), the bit line BL2 receives an inhibit voltage (Vinh_r), and the bit line BL1 receives a first voltage less than the reset voltage (Vreset), for example, the first voltage is a ground voltage (0V). Therefore, the resistive memory cell c11 is a selected memory cell, and the other resistive memory cells c12 to c22 are non-selected memory cells.

[0063] Among them, the reset voltage (Vreset), the turn-on voltage (Von) and the inhibition voltage (Vinh_r) are all positive voltages, so the voltage (Vreset) on the source line SL1 minus the voltage (0V) on the bit line BL1 is greater than zero, that is, the selected memory cell c11 receives a positive voltage difference to perform a reset operation. In addition, the reset voltage (Vreset) is greater than the turn-on voltage (Von), and the reset voltage (Vreset) is greater than or equal to the inhibition voltage (Vinh_r). For example, the reset voltage (Vreset) is 1.5V, the turn-on voltage (Von) is 0.8V, the inhibition voltage (Vinh_r) is 0.8V, and the turn-off voltage (Voff) is the ground voltage (0V).

[0064] In the selected memory cell c11, the first transistor T1 is turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the reset voltage Vreset, so that the second transistor T2 presents a reset state with a high resistance value, that is, the selected memory cell c11 presents a reset state with a high resistance value. Similarly, other resistive memory cells c12 to c22 can also use a similar biasing method to perform a reset action. No further details are given here.

[0065] like Figure 5C , which is a schematic diagram of the bias voltage of the array structure for setting operation. In this example, in order to comply with the bipolar operation mode, the selected memory cell c11 is set using a negative voltage difference, so the voltage on the source line SL1 (V SL1 ) minus the voltage on bit line BL1 (V BL1) is less than zero. For example, during the setting operation, the word line WL1 receives the on voltage (Von), the word line WL2 receives the off voltage (Voff), the source line SL2 receives the ground voltage (0V), the bit line BL1 receives the set voltage (Vset), the bit line BL2 receives the ground voltage (0V), and the source line SL1 receives a second voltage less than the set voltage (Vset), for example, the second voltage is equal to the ground voltage (0V). Therefore, the resistive memory cell c11 is a selected memory cell, and the other resistive memory cells c12 to c22 are non-selected memory cells.

[0066] Among them, the set voltage (Vset) and the turn-on voltage (Von) are both positive voltages, and the set voltage (Vset) is greater than the turn-on voltage (Von), so the voltage (0V) on the source line SL1 minus the voltage (Vset) on the bit line BL1 is less than zero, that is, the selected memory cell c11 receives a negative voltage difference to perform a setting operation. For example, the set voltage (Vset) is 2.4V, the turn-on voltage (Von) is 2.8V, and the turn-off voltage (Voff) is the ground voltage (0V). Of course, in other embodiments, other biasing methods can also be used to perform the setting operation, such as providing the source line SL1 with a voltage of -2.5V and providing the bit line BL1 with a voltage of 0V, so that the selected memory cell c11 complies with the bipolar operation mode in which a negative voltage difference is used to perform the setting operation.

[0067] In the selected memory cell c11, the first transistor T1 is turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the set voltage Vset, so that the second transistor T2 presents a set state with a low resistance value, that is, the selected memory cell c11 presents a set state with a low resistance value. Similarly, other resistive memory cells c12 to c22 can also use a similar biasing method to perform setting operations. No further details are given here.

[0068] Depend on Figure 5B and Figure 5C It can be seen that during the reset action, the gate terminal of the second transistor T2 receives the positive reset voltage Vreset, and the body terminal of the second transistor T2 receives the ground voltage (0V). During the set action, the gate terminal of the second transistor T2 receives the ground voltage (0V), and the body terminal of the second transistor T2 receives the positive set voltage Vset. In other words, the resistive memory cell c11 of the present invention is a resistive memory cell in a bipolar operation mode.

[0069] In the above description, the first transistor T1 and the second transistor T2 are both described as N-type transistors. Of course, technicians in this field can also design the first transistor T1 and the second transistor T2 as P-type transistors. That is, in the N-type well region NW, the first transistor T1 includes a P-type first doping region, a P-type second doping region and a first gate structure. Furthermore, the second transistor T2 includes a P-type second doping region, a P-type third doping region, a P-type injection region and a second gate structure. Among them, the P-type second doping region, the P-type third doping region, and the P-type injection region overlap with each other and form a P-type merged region (P-typemerged region).

[0070] In addition, in the first embodiment, the N-type merged region in the second transistor T2 can also be formed by other methods. For example, in the semiconductor CMOS manufacturing process, a lightly doped drain (LDD) region can be formed in the doped region. The N-type merged region can also be formed by the step of forming the lightly doped drain region. This is explained below.

[0071] Please refer to FIG. 6A to FIG. 6C , which is a flow chart of a method for manufacturing a resistive memory cell according to a second embodiment of the present invention.

[0072] like Fig. 6A As shown, two gate structures 650 and 660 are formed on the surface of the P-type well region PW, the first gate structure 650 includes an insulating layer 652 and a conductive layer 655, and the second gate structure 660 includes an insulating layer 662 and a conductive layer 665. Among them, the conductive layer 655 can be used as a word line WL, and the conductive layer 665 can be used as a source line SL. Furthermore, the structures and materials of the two gate structures 650 and 660 are the same as the two gate structures 250 and 260 of the first embodiment, and are not repeated here.

[0073] like Figure 6B As shown, a doping process is performed to form an N-type first doping region 621, a second doping region 622, and a third doping region 623 below the exposed surface of the P-type well region PW. Therefore, the first gate structure 650 is located above the surface of the P-type well region PW between the first doping region 621 and the second doping region 622. The second gate structure 660 is located above the surface of the P-type well region PW between the second doping region 622 and the third doping region 623.

[0074] Furthermore, if Figure 6CAs shown, the two doped regions 622 and 623 on both sides of the second gate structure 660 form extended lightly doped drain regions (extended LDD) 624 and 625. The extended lightly doped drain region 624 is located below the gate structure 660 and contacts the second doped region 622, and the extended lightly doped drain region 625 is located below the gate structure 660 and contacts the third doped region 623. Furthermore, the extended lightly doped drain region 624 overlaps with the extended lightly doped drain region 625 and forms an N-type merged region. In other words, the second gate structure 660 is located above the N-type merged region.

[0075] Next, a metal layer 629 is formed to connect to the first doped region 621 via a contact hole, and the resistive memory cell 600 of the present invention is completed. The metal layer 629 serves as the bit line BL of the resistive memory cell 600 .

[0076] like Figure 6C As shown, in the P-type well region PW, the first doping region 621, the second doping region 622 and the first gate structure 650 form a first transistor T1; the second doping region 622, the third doping region 623, the lightly doped drain regions 624, 625 and the second gate structure 660 form a second transistor T2. Furthermore, since the second doping region 622, the third doping region 623 and the lightly doped drain regions 624, 625 form an N-type merged region, it can be regarded as that the two drain / source terminals and the body terminal of the second transistor T2 are connected to each other. In addition, a PN junction is formed between the N-type merged region and the P-type well region PW, which can be regarded as a diode.

[0077] In addition, the equivalent circuit of the resistive memory cell 600 of the second embodiment is the same as Figure 3D Similarly, the array structure and various operations of the resistive memory cell 600 of the second embodiment are also the same as those of FIG. 5A to FIG. 5C That is, the resistive memory cell 600 of the second embodiment is a resistive memory cell in a bipolar operation mode. Of course, the resistive memory cell 600 of the second embodiment can also be implemented using a P-type transistor.

[0078] Please refer to FIG. 7A to FIG. 7C , which is a flow chart of a method for manufacturing a resistive memory cell according to a third embodiment of the present invention.

[0079] like Fig. 7AAs shown, an isolation structure 702 is formed in the P-type well region PW. Next, N-type implanted regions 710 and 712 are formed on both sides of the isolation structure 702. The isolation structure 702 is a shallow trench isolation structure (STI for short). Of course, when manufacturing the resistive memory cell of the third embodiment, an N-type implanted region can also be formed on the surface of the P-type well region PW. Next, an isolation structure is formed and the N-type implanted region is divided into two parts.

[0080] Then, if Figure 7B As shown, three gate structures 750, 760, and 770 are formed. The first gate structure 750 is formed on the first side of the isolation structure 702, above the surface of the P-type well region PW. The second gate structure 760 is formed on the two N-type implant regions 710 and 712 and above the surface of the isolation structure 702. The third gate structure 770 is formed on the second side of the isolation structure 702, above the surface of the P-type well region PW.

[0081] In addition, the first gate structure 750 includes an insulating layer 752 and a conductive layer 755, the second gate structure 760 includes an insulating layer 762 and a conductive layer 765, and the third gate structure 770 includes an insulating layer 772 and a conductive layer 775. Among them, the conductive layer 755 can be used as a word line WL, the conductive layer 765 can be used as a source line SL, and the conductive layer 775 can be used as another word line WL'. Furthermore, the structures and materials of the three gate structures 750, 760, and 770 are the same as those of the two gate structures 250 and 260 of the first embodiment, and are not repeated here.

[0082] like Figure 7C As shown, a doping process is performed to form an N-type first doping region 721, a second doping region 722, a third doping region 723, and a fourth doping region 724 below the exposed surface of the P-type well region PW. Therefore, the first gate structure 750 is located above the surface of the P-type well region PW between the first doping region 721 and the second doping region 722. The second gate structure 760 is located above the surface of the N-type implantation regions 710, 712 and the isolation structure 702 between the second doping region 722 and the third doping region 723. The third gate structure 770 is located above the surface of the P-type well region PW between the third doping region 723 and the fourth doping region 724. Furthermore, the second doping region 722 and the N-type implantation region 710 overlap with each other to form an N-type merged region. The third doping region 723 and the N-type implantation region 712 overlap with each other to form another N-type merged region.

[0083] Next, a metal layer 729 is formed to be connected to the first doped region 721 via a contact hole, and the resistive memory cell 700 of the present invention is completed. In addition, a metal layer 728 is formed to be connected to the fourth doped region 724 via a contact hole, and another resistive memory cell 701 of the present invention is completed. The metal layer 729 serves as the bit line BL of the resistive memory cell 700, and the metal layer 728 serves as the bit line BL' of the other resistive memory cell 701.

[0084] exist Figure 7C The present invention includes two resistive memory cells 700 and 701, and the two resistive memory cells 700 and 701 share a source line (SL). In the resistive memory cell 700, the first doping region 721, the second doping region 722 and the first gate structure 750 form a first transistor T1; the second doping region 722 and the second gate structure 760 form a second transistor T2. Furthermore, the second doping region 722 and the N-type implantation region 710 form an N-type merged region, and a PN junction is formed between the N-type merged region and the P-type well region PW, which can be regarded as a diode.

[0085] Similarly, the resistive memory cell 701 also includes two transistors T1 ′ and T2 ′, and the structure thereof is the same as that of the resistive memory cell 700 , which will not be described again.

[0086] In addition, the equivalent circuits of the resistive memory cells 700 and 701 of the third embodiment are the same as Figure 3D Similarly, the array structure and various operations of the resistive memory cells 700 and 701 of the third embodiment are also the same as those of FIG. 5A to FIG. 5C That is, the resistive memory cells 700 and 701 of the third embodiment are resistive memory cells in a bipolar operation mode. Of course, the resistive memory cells 700 and 701 of the third embodiment can also be implemented using P-type transistors.

[0087] Please refer to Figure 8, which is a resistive memory cell of the fourth embodiment of the present invention. Compared with the resistive memory cells 700 and 701 of the third embodiment, the only difference is that the resistive memory cells 800 and 801 of the fourth embodiment do not share a source line. That is, the N-type implanted region 710 is located between the isolation structure 702 and the second doping region 722, and the N-type implanted region 712 is located between the isolation structure 702 and the third doping region 723. Furthermore, in the resistive memory cell 800, the gate structure 860 is formed on the surface of the N-type implanted region 710, and the conductive layer 865 can serve as the source line SL. In the resistive memory cell 801, the gate structure 890 is formed on the surface of the N-type implanted region 712, and the conductive layer 895 can serve as another source line SL'.

[0088] In addition, the equivalent circuits of the resistive memory cells 800 and 801 of the fourth embodiment are the same as Figure 3D Similarly, the array structure and various operations of the resistive memory cells 800 and 801 of the fourth embodiment are also the same as those of FIG. 5A to FIG. 5C That is, the resistive memory cells 800 and 801 of the fourth embodiment are resistive memory cells in a bipolar operation mode. Of course, the resistive memory cells 800 and 801 of the fourth embodiment can also be implemented using P-type transistors.

[0089] Please refer to Fig.9A and Fig. 9B , which illustrates a resistive memory cell and its equivalent circuit according to the fifth embodiment of the present invention.

[0090] like Fig.9A As shown, an N-type implanted region 910 is formed in the P-type well region PW. Next, three gate structures 950, 960, and 970 are formed, wherein the first gate structure 950 is formed above the surface of the P-type well region PW, the second gate structure 960 is formed above the surface of the N-type implanted region 910, and the third gate structure 970 is formed above the surface of the P-type well region PW. Each gate structure 950, 960, and 970 has the same structure.

[0091] In addition, the first gate structure 950 includes an insulating layer 952 and a conductive layer 955, the second gate structure 960 includes an insulating layer 962 and a conductive layer 965, and the third gate structure 970 includes an insulating layer 972 and a conductive layer 975. The conductive layers 955 and 975 can be used as word lines WL, and the conductive layer 965 can be used as source lines SL. Furthermore, the structures and materials of the three gate structures 950, 960, and 970 are the same as those of the two gate structures 250 and 260 of the first embodiment, and are not described again here.

[0092] Furthermore, an N-type first doping region 921, a second doping region 922, a third doping region 923, and a fourth doping region 924 are formed below the exposed surface of the P-type well region PW. Therefore, the first gate structure 950 is located above the surface of the P-type well region PW between the first doping region 921 and the second doping region 922, the second gate structure 960 is located above the surface of the N-type implantation region 910 between the second doping region 922 and the third doping region 923, and the third gate structure 970 is located above the surface of the P-type well region PW between the third doping region 923 and the fourth doping region 924. Furthermore, the second doping region 922, the third doping region 923 and the N-type implantation region 910 overlap with each other and form an N-type merged region. In other words, the second gate structure 960 is located above the N-type merged region.

[0093] Next, a metal layer 929 is formed to connect to the first doping region 921 and the fourth doping region 924 via contact holes, and the resistive memory cell 900 of the present invention is completed. The metal layer 929 serves as the bit line BL of the resistive memory cell 900 .

[0094] like Fig.9A As shown, in the P-type well region PW, the first doping region 921, the second doping region 922 and the first gate structure 950 form a first transistor T1; the second doping region 922, the third doping region 923 and the second gate structure 960 form a second transistor T2; the third doping region 923, the fourth doping region 924 and the third gate structure 970 form a third transistor T3. Furthermore, since the second doping region 922, the third doping region 923 and the N-type implantation region 910 form an N-type merged region, it can be regarded as that the two drain / source terminals and the body terminal of the second transistor T2 are connected to each other. In addition, a PN junction is formed between the N-type merged region and the P-type well region PW, which can be regarded as a diode.

[0095] like Fig. 9BAs shown, the resistive memory cell 900 includes three transistors T1, T2, T3 and a diode D. The first drain / source terminal of the first transistor T1 is connected to the bit line BL, and the gate terminal of the first transistor T1 is connected to the word line WL. The first drain / source terminal, the second drain / source terminal and the body terminal of the second transistor T2 are connected to each other, the first drain / source terminal of the second transistor T2 is connected to the second drain / source terminal of the first transistor T1, and the gate terminal of the second transistor T2 is connected to the source line SL. The first drain / source terminal of the third transistor T3 is connected to the second drain / source terminal of the second transistor T2, the gate terminal of the third transistor T3 is connected to the word line WL, and the second drain / source terminal of the third transistor T3 is connected to the bit line BL. Furthermore, the first end of the diode D is connected to the body terminal of the second transistor T2, and the second end of the diode D is connected to the body terminals of the first transistor T1 and the third transistor T3.

[0096] In the fifth embodiment, the first transistor T1, the second transistor T2 and the third transistor T3 are all described as N-type transistors. Of course, those skilled in the art can also design the first transistor T1, the second transistor T2 and the third transistor T3 as P-type transistors. Similarly, in the fifth embodiment, the N-type merged region in the second transistor T2 can also be formed by other methods. For example, by Fig. 6A , Figure 6B and Figure 6C The disclosed step of forming the lightly doped drain region is used to form an N-type merging region and is applied to the second transistor T2 in the resistive memory cell 600 .

[0097] Furthermore, a plurality of resistive memory cells can form an array structure of resistive memory cells. Fig.10 , which shows an array structure composed of resistive memory cells. The memory cell array structure 999 is composed of 2×2 resistive memory cells c11-c22. The structure of each resistive memory cell c11-c22 is the same as Fig.9A and Fig. 9B Of course, the present invention is not limited to the memory cell array structure 999 of 2×2 resistive memory cells c11-c22. A person skilled in the art can form an array structure of m×n resistive memory cells according to the description of the present invention, where m and n are positive integers.

[0098] like Fig.10As shown, in the memory cell array structure 999, the two resistive memory cells c11-c12 in the first column are connected to the word line WL1 and the source line SL1, and the two resistive memory cells c11-c12 in the first column are connected to the corresponding bit lines BL1 and BL2. Furthermore, the two resistive memory cells c21-c22 in the second column are connected to the word line WL2 and the source line SL2, and the two resistive memory cells c11-c12 in the second column are connected to the corresponding bit lines BL1 and BL2.

[0099] Furthermore, by providing appropriate bias voltages to the word lines WL1-WL2, source lines SL1-SL2, and bit lines BL1-BL2 of the memory cell array structure 999, the resistive memory cells c21-c22 can be formed, reset, and set, as described in detail below.

[0100] Please refer to FIG. 11A to FIG. 11C , which is a schematic diagram of the bias voltage of the array structure of the present invention performing various actions.

[0101] like Fig.11A As shown, it is a bias schematic diagram of the array structure performing a forming action. During the forming action, the word line WL1 receives a turn-on voltage (Von), the word line WL2 receives a turn-off voltage (Voff), the source line SL1 receives a forming voltage (Vform), the source line SL2 receives a ground voltage (0V), the bit line BL1 receives a ground voltage (0V), and the bit line BL2 receives an inhibit voltage (inhibit voltage, Vinh_r). Therefore, in the memory cell array structure 999, the first column connected to the word line WL1 is a selected column, and the second column connected to the word line WL2 is a non-selected column. Among them, the forming voltage (Vform), the turn-on voltage (Von) and the inhibit voltage (Vinh_r) are all positive voltages, the forming voltage (Vform) is greater than the turn-on voltage (Von), and the forming voltage (Vform) is greater than or equal to the inhibit voltage (Vinh_r). For example, the forming voltage (Vform) is 4V, the opening voltage (Von) is 2V, the inhibiting voltage (Vinh_r) is 2V, and the closing voltage (Voff) is the ground voltage (0V).

[0102] In the selected column, since the source line SL1 receives the forming voltage (Vform) and the bit line BL1 is at the ground voltage (0V), the memory cell c11 is the selected memory cell. In addition, since the bit line BL2 receives the inhibiting voltage (Vinh_r), the memory cell c12 is the unselected memory cell. Furthermore, in the unselected column, since the word line WL2 receives the off voltage (Voff), the memory cells c21 and c22 are the unselected memory cells.

[0103] In the selected memory cell c11, the first transistor T1 and the third transistor T3 are turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the forming voltage (Vform), and a forming current is generated between the source line SL1 and the bit line BL1. The first part of the forming current I f1 The second part of the current I flows to the bit line BL1 through the first transistor T1. f2 The current flows to the bit line BL1 through the third transistor T3. When the current passes through the insulating layer of the second transistor T2, a conductive crack can be formed in the insulating layer. Similarly, other resistive memory cells c12-c22 can also be formed using a similar biasing method. No further details will be given here.

[0104] Similarly, if the forming current generated by the forming action is too large, the insulating layer in the selected memory cell c11 may be burned out. The present invention can connect a current limiter to the source line SL1 or the bit line BL1 of the selected memory cell c11 to limit the size of the forming current to prevent the insulating layer in the selected memory cell c11 from being burned out.

[0105] like Fig. 11B As shown, it is a bias schematic diagram of the array structure performing a reset action. During the reset action, the word line WL1 receives an on voltage (Von), the word line WL2 receives an off voltage (Voff), the source line SL1 receives a reset voltage (Vreset), the source line SL2 receives a ground voltage (0V), the bit line BL2 receives an inhibit voltage (Vinh_r), and the bit line BL1 receives a first voltage less than the reset voltage (Vreset), for example, the first voltage is a ground voltage (0V). Therefore, the resistive memory cell c11 is a selected memory cell (selected cell), and the other resistive memory cells c12 to c22 are non-selected memory cells.

[0106] Among them, the reset voltage (Vreset), the turn-on voltage (Von) and the inhibition voltage (Vinh_r) are all positive voltages, the reset voltage (Vreset) is greater than the turn-on voltage (Von), and the reset voltage (Vreset) is greater than or equal to the inhibition voltage (Vinh_r). For example, the reset voltage (Vreset) is 1.5V, the turn-on voltage (Von) is 0.8V, the inhibition voltage (Vinh_r) is 0.8V, and the turn-off voltage (Voff) is the ground voltage (0V).

[0107] In the selected memory cell c11, the first transistor T1 and the third transistor T3 are turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the reset voltage Vreset, so that the second transistor T2 presents a reset state with a high resistance value, that is, the selected memory cell presents a reset state with a high resistance value. Similarly, other resistive memory cells c12 to c22 can also use a similar biasing method to perform a reset action. No further details are given here.

[0108] like Fig. 11C As shown, it is a bias schematic diagram of the array structure performing a setting action. During the setting action, the word line WL1 receives a turn-on voltage (Von), the word line WL2 receives a turn-off voltage (Voff), the source line SL2 receives a ground voltage (0V), the bit line BL1 receives a set voltage (Vset), the bit line BL2 receives a ground voltage (0V), and the source line SL1 receives a second voltage less than the set voltage (Vset), for example, the second voltage is equal to the ground voltage (0V). Therefore, the resistive memory cell c11 is a selected memory cell (selected cell), and the other resistive memory cells c12~c22 are non-selected memory cells. Among them, the set voltage (Vset) and the turn-on voltage (Von) are both positive voltages, and the set voltage (Vset) is greater than the turn-on voltage (Von). For example, the set voltage (Vset) is 2.4V, the turn-on voltage (Von) is 2.8V, and the turn-off voltage (Voff) is the ground voltage (0V).

[0109] In the selected memory cell c11, the first transistor T1 and the third transistor T3 are turned on, so that the insulating layer in the gate structure of the second transistor T2 is subjected to the set voltage Vset, so that the second transistor T2 presents a set state with a low resistance value, that is, the selected memory cell presents a set state with a low resistance value. Similarly, other resistive memory cells c12 to c22 can also use a similar bias method to perform setting operations. No further details are given here.

[0110] Depend on Fig. 11B and Fig. 11C It can be seen that during the reset action, the gate terminal of the second transistor T2 receives the positive reset voltage Vreset, and the body terminal of the second transistor T2 receives the ground voltage (0V). During the set action, the gate terminal of the second transistor T2 receives the ground voltage (0V), and the body terminal of the second transistor T2 receives the positive set voltage Vset. In other words, the resistive memory cell c11 of the present invention is a resistive memory cell in a bipolar operation mode.

[0111] From the above description, it can be seen that the present invention provides a resistive memory cell with bipolar operation. Furthermore, by providing a proper bias voltage, the resistive memory cell can be formed, reset and set.

[0112] In summary, although the present invention is disclosed in conjunction with the above preferred embodiments, it is not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the definition of the attached claims.

Claims

1. A resistive memory cell array structure, the array structure having a first resistive memory cell, the first resistive memory cell include: A first type well region; A first doped region is formed below the surface of the first-type well region, and the first doped region is a second-type doped region; A second type merging region formed below the surface of the first type well region; A first gate structure is formed above the surface of the first-type well region between the first doped region and the second-type merged region, wherein the first gate structure includes a first insulating layer and a first conductive layer stacked, and the first conductive layer serves as a first word line; A second gate structure is formed above the second-type merging region, wherein the second gate structure includes a stacked second insulating layer and a second conductive layer, and the second conductive layer serves as a first source line; as well as A first metal layer connected to the first doped region, and the first metal layer serves as a first bit line; The second type merged region includes: a second type implanted region, a second doped region and a third doped region, which are formed below the surface of the first type well region, the second type implanted region overlaps with the second doped region, and the second type implanted region overlaps with the third doped region; Wherein, the second gate structure is formed above the second type implantation region, and the second doping region and the third doping region are the second type doping regions; Wherein, during the forming action, the first source line receives a forming voltage, the first word line receives a start voltage, the first bit line receives a ground voltage, and the second insulating layer forms a conductive crack; Wherein, during the reset action, the first source line receives a reset voltage, the first word line receives the open voltage, and the first bit line receives a first voltage less than the reset voltage, so that the first resistive memory cell is in a reset state; In the setting operation, the first word line receives the start-up voltage, the first bit line receives the setting voltage, and the first source line receives a second voltage lower than the setting voltage, so that the first resistive memory unit becomes a setting state. 2 . The resistive memory cell array structure as claimed in claim 1 , wherein the second insulating layer comprises a high dielectric constant material layer. 3 . The resistive memory cell array structure as claimed in claim 2 , wherein the high dielectric constant material is a hafnium dioxide layer or a tantalum oxide layer. 4 . The array structure of the resistive memory cell as claimed in claim 1 , wherein during the forming operation, the first source line or the first bit line is connected to a current limiter to limit the forming current generated by the first resistive memory cell. 5 . The array structure of resistive memory cells as claimed in claim 1 , wherein the second insulating layer of the second gate structure contacts the second type implantation region in the second type merging region.

6. The resistive memory cell array structure as claimed in claim 1, wherein the first resistive memory cell further comprises: a fourth doping region formed below the surface of the first-type well region, and the fourth doping region is the second-type doping region; and A third gate structure is formed above the surface of the first-type well region between the fourth doped region and the second-type merged region, wherein the third gate structure includes a stacked third insulating layer and a third conductive layer, and the third conductive layer serves as the first word line; in, The first metal layer is connected to the fourth doped region.

7. The array structure of the resistive memory cell as claimed in claim 6, wherein the second-type merged region and the first-type well region form a first diode; the first doped region, the second-type merged region and the first gate structure form a first transistor; the second-type merged region and the second gate structure form a second transistor; the fourth doped region, the second-type merged region and the third gate structure form a third transistor; the first drain / source terminal of the first transistor is connected to the first bit line, the gate terminal of the first transistor is connected to the first word line, the first drain / source terminal of the second transistor is connected to the second drain / source terminal of the first transistor, the gate terminal of the second transistor is connected to the first source line, the first drain / source terminal of the third transistor is connected to the second drain / source terminal of the second transistor, the gate terminal of the third transistor is connected to the first word line, the second drain / source terminal of the third transistor is connected to the first bit line, the body terminal of the second transistor, the first drain / source terminal of the second transistor and the second drain / source terminal of the second transistor are connected to the first end of the first diode, the second end of the first diode is connected to the body terminal of the first transistor, and the second end of the first diode is connected to the body terminal of the third transistor.

8. The array structure of the resistive memory cell as claimed in claim 7 further comprises a second resistive memory cell having a fourth transistor, a fifth transistor, a sixth transistor and a second diode; wherein a first drain / source terminal of the fourth transistor is connected to a second bit line, a gate terminal of the fourth transistor is connected to the first word line, a first drain / source terminal of the fifth transistor is connected to a second drain / source terminal of the fourth transistor, a gate terminal of the fifth transistor is connected to the first source line, a first drain / source terminal of the sixth transistor is connected to a second drain / source terminal of the fifth transistor, a gate terminal of the sixth transistor is connected to the first word line, a second drain / source terminal of the sixth transistor is connected to the second bit line, a body terminal of the fifth transistor, the first drain / source terminal of the fifth transistor and the second drain / source terminal of the fifth transistor are connected to a first terminal of the second diode, a second terminal of the second diode is connected to a body terminal of the fourth transistor, and a second terminal of the second diode is connected to a body terminal of the sixth transistor.

9. The array structure of the resistive memory cell as claimed in claim 8 further comprises a third resistive memory cell having a seventh transistor, an eighth transistor, a ninth transistor and a third diode; wherein a first drain / source terminal of the seventh transistor is connected to the first bit line, a gate terminal of the seventh transistor is connected to the second word line, a first drain / source terminal of the eighth transistor is connected to the second drain / source terminal of the seventh transistor, a gate terminal of the eighth transistor is connected to the second source line, a first drain / source terminal of the ninth transistor is connected to the second drain / source terminal of the eighth transistor, a gate terminal of the ninth transistor is connected to the second word line, a second drain / source terminal of the ninth transistor is connected to the first bit line, a body terminal of the eighth transistor, the first drain / source terminal of the eighth transistor and the second drain / source terminal of the eighth transistor are connected to the first end of the third diode, a second end of the third diode is connected to the body terminal of the seventh transistor, and the second end of the third diode is connected to the body terminal of the ninth transistor.

10. The array structure of the resistive memory cell as described in claim 1, wherein the second-type merged region and the first-type well region form a first diode; the first doped region, the second-type merged region and the first gate structure form a first transistor; the second-type merged region and the second gate structure form a second transistor; the first drain / source terminal of the first transistor is connected to the first bit line, the gate terminal of the first transistor is connected to the first word line, the first drain / source terminal of the second transistor is connected to the second drain / source terminal of the first transistor, the gate terminal of the second transistor is connected to the first source line, the body terminal of the second transistor, the first drain / source terminal of the second transistor and the second drain / source terminal of the second transistor are connected to the first end of the first diode, and the second end of the first diode is connected to the body terminal of the first transistor.

11. The array structure of the resistive memory cell as described in claim 10 further includes a second resistive memory cell, comprising a third transistor, a fourth transistor and a second diode; wherein the first drain / source terminal of the third transistor is connected to the second bit line, the gate terminal of the third transistor is connected to the first word line, the first drain / source terminal of the fourth transistor is connected to the second drain / source terminal of the third transistor, the gate terminal of the fourth transistor is connected to the first source line, the body terminal of the fourth transistor, the first drain / source terminal of the fourth transistor and the second drain / source terminal of the fourth transistor are connected to the first end of the second diode, and the second end of the second diode is connected to the body terminal of the third transistor.

12. The array structure of the resistive memory cell as described in claim 11 further includes a third resistive memory cell, having a fifth transistor, a sixth transistor and a third diode; wherein the first drain / source terminal of the fifth transistor is connected to the first bit line, the gate terminal of the fifth transistor is connected to the second word line, the first drain / source terminal of the sixth transistor is connected to the second drain / source terminal of the fifth transistor, the gate terminal of the sixth transistor is connected to the second source line, the body terminal of the sixth transistor, the first drain / source terminal of the sixth transistor and the second drain / source terminal of the sixth transistor are connected to the first end of the third diode, and the second end of the third diode is connected to the body terminal of the fifth transistor.

13. A resistive memory cell array structure, the array structure having a first resistive memory cell, the first resistive memory cell include: A first type well region; A first doped region is formed below the surface of the first-type well region, and the first doped region is a second-type doped region; A second type merging region formed below the surface of the first type well region; A first gate structure is formed above the surface of the first-type well region between the first doped region and the second-type merged region, wherein the first gate structure includes a first insulating layer and a first conductive layer stacked, and the first conductive layer serves as a first word line; A second gate structure is formed above the second-type merging region, wherein the second gate structure includes a stacked second insulating layer and a second conductive layer, and the second conductive layer serves as a first source line; as well as A first metal layer connected to the first doped region, and the first metal layer serves as a first bit line; The second type merged region includes: a second doped region, a third doped region, a first extended lightly doped drain region, and a second extended lightly doped drain region, wherein the second doped region is formed below the surface of the first type well region and is located on a first side of the second gate structure, the third doped region is formed below the surface of the first type well region and is located on a second side of the second gate structure, the first extended lightly doped drain region is located below the second gate structure and in contact with the second doped region, and the second extended lightly doped drain region is located below the second gate structure and in contact with the third doped region; Wherein, the second doping region and the third doping region are the second type doping regions, and the first extended lightly doped drain region overlaps with the second extended lightly doped drain region; Wherein, during the forming action, the first source line receives a forming voltage, the first word line receives a start voltage, the first bit line receives a ground voltage, and the second insulating layer forms a conductive crack; Wherein, during the reset action, the first source line receives a reset voltage, the first word line receives the open voltage, and the first bit line receives a first voltage less than the reset voltage, so that the first resistive memory cell is in a reset state; In the setting operation, the first word line receives the start-up voltage, the first bit line receives the setting voltage, and the first source line receives a second voltage lower than the setting voltage, so that the first resistive memory unit becomes a setting state.

14. A resistive memory cell array structure, the array structure comprising a first resistive memory cell, the first resistive memory cell include: A first type well region; A first doped region is formed below the surface of the first-type well region, and the first doped region is a second-type doped region; A second type merging region formed below the surface of the first type well region; A first gate structure is formed above the surface of the first-type well region between the first doped region and the second-type merged region, wherein the first gate structure includes a first insulating layer and a first conductive layer stacked, and the first conductive layer serves as a first word line; A second gate structure is formed above the second-type merging region, wherein the second gate structure includes a stacked second insulating layer and a second conductive layer, and the second conductive layer serves as a first source line; A first metal layer connected to the first doped region, and the first metal layer serves as a first bit line; as well as An isolation structure formed in the first type well region; The second type merged region includes: a second type implantation region and a second doping region, which are formed below the surface of the first type well region, the second type implantation region overlaps with the second doping region, and the second type implantation region is located between the second doping region and the isolation structure; wherein the second gate structure is formed above the second type implant, and the second doped region is the second type doped region; Wherein, during the forming action, the first source line receives a forming voltage, the first word line receives a start voltage, the first bit line receives a ground voltage, and the second insulating layer forms a conductive crack; Wherein, during the reset action, the first source line receives a reset voltage, the first word line receives the open voltage, and the first bit line receives a first voltage less than the reset voltage, so that the first resistive memory cell is in a reset state; In the setting operation, the first word line receives the start-up voltage, the first bit line receives the setting voltage, and the first source line receives a second voltage lower than the setting voltage, so that the first resistive memory unit becomes a setting state.

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