OPC correction method

Abstract

The present invention discloses an OPC correction method, including: Step 1, providing a front-layer pattern, including first and second substrate patterns having a substrate height difference; Step 2, selecting the first and second substrate patterns in the front-layer pattern by a size selection method, and the reflection difference corresponding to the selected first and second substrate patterns will cause the photoresist size difference to be greater than or equal to a specified value; an auxiliary pattern is set on the selected first or second substrate pattern; Step 3, selecting a current-layer pattern in the original layout of the current layer that intersects the first or second substrate pattern corresponding to the auxiliary pattern; Step 4, performing edge segmentation on the selected current-layer pattern and performing local reverse size compensation to offset the photoresist size difference caused by the reflection difference; Step 5, performing OPC correction on the original layout of the current layer that has undergone local reverse size compensation. The present invention can improve the topography of the photoresist pattern on substrates with different heights and improve the uniformity of the line width or pitch of the current-layer pattern.

Description

Technical Field

[0001] The present invention relates to a semiconductor integrated circuit manufacturing method, and in particular to an optical proximity correction (OPC) method. Background Art

[0002] The light source generally passes through two interfaces when it passes through the mask to reach the photoresist, and reflection occurs at the interface. The existence of these reflected lights will affect the line width and morphology of the photoresist after exposure. When the graphic resolution reaches the sub-micron level, the negative impact of substrate reflection on line width and process window becomes increasingly obvious. With the development of semiconductor process technology, the line width of the ion implantation layer reaches below 200nm. In order to obtain a more accurate boundary of the ion implantation layer, an anti-reflection layer is introduced. The two beams of reflected light generated by the anti-reflection layer interfere with each other destructively, thereby maximally suppressing the negative effect of reflected light on line width and process window. Figure 1 The figure shows a schematic diagram of the destructive interference of substrate reflected light after the anti-reflection layer is introduced in the existing photolithography process; a bottom anti-reflection coating 102 (Bottom Anti-Reflection Coating, BARC) is formed on a semiconductor substrate 101, and a photoresist 103 is coated on the bottom anti-reflection layer 102. It can be seen that the reflected light 106 formed by the incident light 104 on the surface of the semiconductor substrate 101 will be eliminated by the interference of the reflected light 105 formed on the top surface of the bottom anti-reflection layer 102, thereby eliminating the adverse effect of the substrate reflected light 106 on the exposure.

[0003] However, due to the ups and downs of the gate and shallow trench isolation (STI) in the front substrate of the fin transistor (FinFET), the thickness of the flattened bottom anti-reflection layer varies at different positions on the substrate, resulting in significant differences in the width of the photoresist trench or line. Figure 2 , which is a schematic diagram of the structure after a bottom anti-reflection layer and a photoresist are formed when the substrate surface is uneven in the existing photolithography process; Figure 2 It is a cross-sectional view along the shallow trench isolation 201. The gate 202 will be formed to cover the top surface and side of the fin body, and will also extend to the top surface of the shallow trench isolation 201. It can be seen that the top surfaces of the shallow trench isolation 201 and the gate 202 are not flat, and both serve as substrate structures in the subsequent lithography process of the ion implantation layer. It can be seen that after the bottom anti-reflection layer 203 is formed and flattened, the thickness of the bottom anti-reflection layer 203 in the shallow trench isolation 201 and the gate 202 area is different; thus, when the photoresist 204 is coated and exposed, the bottom anti-reflection layer 203 in different areas has different ability to eliminate the reflected light of the bottom substrate, which will eventually make the exposure uneven, resulting in line width differences.

[0004] Currently, the improvement of the local line width uniformity of photoresist is mostly achieved by improving the control of the lithography equipment, improving the flatness of the front substrate and increasing the focus depth of the lithography process. These methods have high requirements on the equipment or process. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an OPC correction method, which can improve the photoresist pattern morphology of the current layer pattern across substrates of different heights, improve the uniformity of the line width or spacing of the current layer pattern, and increase the process window of the line width or spacing of the current layer pattern.

[0006] To solve the above technical problems, the OPC correction method provided by the present invention comprises the following steps:

[0007] Step 1: providing a front layer pattern, wherein the front layer pattern comprises a first substrate pattern and a second substrate pattern, and a substrate height difference exists between a top surface of the first substrate pattern and a top surface of the second substrate pattern.

[0008] The substrate height difference allows the bottom anti-reflection layer formed on the surface of the front layer pattern to have a thickness difference between the surfaces of the first substrate pattern and the second substrate pattern.

[0009] The difference in thickness of the bottom anti-reflection layer will cause the substrate residual reflection between the adjacent first substrate pattern and the second substrate pattern to have a reflection difference, and the reflection difference will cause the key size or spacing of the photoresist pattern corresponding to the current layer pattern on the adjacent first substrate pattern and the second substrate pattern to have a photoresist size difference.

[0010] The reflection difference is determined by the sizes of the first substrate pattern and the second substrate pattern.

[0011] Step 2: Select the first substrate pattern and the second substrate pattern from the front layer pattern by a size selection method, and the reflection difference corresponding to the selected first substrate pattern and the second substrate pattern will make the photoresist size difference greater than or equal to a specified value.

[0012] An auxiliary pattern is disposed on the selected first substrate pattern or the second substrate pattern.

[0013] Step three: providing a current layer original layout, and selecting a current layer graphic that will intersect with the first substrate graphic or the second substrate graphic corresponding to the auxiliary graphic from the current layer original layout.

[0014] Step 4: performing edge segmentation (Fragmentation) on the selected current layer pattern and performing local reverse size compensation, wherein the local reverse size compensation is used to offset the photoresist size difference caused by the reflection difference.

[0015] Step 5: Perform OPC correction on the original layout of the current layer after the local reverse size compensation.

[0016] A further improvement is that the first substrate pattern includes a gate.

[0017] A further improvement is that the gate covers the top surface and side surfaces of the fin.

[0018] A further improvement is that the second substrate pattern includes shallow trench isolation; the shallow trench isolation is located between the fins; and the top surface of the shallow trench isolation is lower than the top surface of the gate.

[0019] A further improvement is that, in the front layer pattern, the gates are arranged in parallel, the length direction of each gate is perpendicular to the length direction of the fin body; and the width of the gate is the gate channel length.

[0020] A further improvement is that, in step 2, the first substrate pattern or the second substrate pattern is selected in the following manner:

[0021] All of the gates are selected to have a width greater than the critical gate channel length.

[0022] A further improvement is that the auxiliary pattern is arranged on the selected gate.

[0023] A further improvement is that the critical gate channel length is obtained by software simulation, including:

[0024] Simulating the photoresist size difference generated by the gates with different widths;

[0025] The width of the gate corresponding to the specified value of the photoresist dimension difference is used as the critical gate channel length.

[0026] A further improvement is that when the photoresist size difference is smaller than a specified value, the influence of the photoresist size difference is ignored.

[0027] A further improvement is that the software simulation is implemented by S-litho software.

[0028] A further improvement is that the current layer is an ion implantation layer, the current layer pattern is an ion implantation layer pattern, and the ion implantation region is located in a spacing region of the ion implantation pattern.

[0029] A further improvement is that in step 4, the edge segmentation is to segment the edge of the intersection area of ​​the ion implantation layer pattern and the auxiliary pattern; and the local reverse size compensation is to move the segmented edge of the ion implantation layer pattern toward the inside of the ion implantation layer pattern by a compensation size.

[0030] A further improvement is that in step 2, the method for forming the auxiliary pattern includes:

[0031] The selected gate is used as a marking layer pattern, and the marking layer pattern is extended along the width direction of the gate to form the auxiliary pattern.

[0032] A further improvement is that the auxiliary pattern extends outside the length side of each gate to a size of 0 nm to 20 nm.

[0033] A further improvement is that the compensation size is adjusted according to the width of the gate and the process parameters of the bottom anti-reflection layer.

[0034] A further improvement is that the process parameters of the bottom anti-reflection layer include optical parameters, thickness and exposure energy.

[0035] A further improvement is that the optical parameters of the bottom anti-reflection layer include an extinction coefficient (k) and a refractive index (n).

[0036] A further improvement is that the OPC correction in step five includes sequentially performing rule-based OPC correction and model-based OPC correction.

[0037] The present invention pre-processes the current layer pattern in the current layer original layout according to the previous layer pattern before performing OPC correction on the current layer original layout. This pre-processing is based on the sizes of the first substrate pattern and the second substrate pattern with a substrate height difference in the previous layer pattern, and selects the first substrate pattern or the second substrate pattern that will eventually make the photoresist size difference greater than or equal to a specified value. This is mainly based on the fact that under the condition that the thickness difference of the bottom anti-reflection layer is determined by the known substrate height difference, the reflection difference of the substrate residual reflection between the adjacent first substrate pattern and the second substrate pattern is determined by the sizes of the first substrate pattern and the second substrate pattern, and the reflection difference will determine the current layer pattern on the adjacent first substrate pattern and the second substrate pattern. The difference in the critical size or spacing of the corresponding photoresist patterns is the photoresist size difference. Therefore, by selecting the sizes of the first substrate pattern and the second substrate pattern, the first substrate pattern or the second substrate pattern whose reflective photoresist size difference is greater than or equal to a specified value can be selected; then an auxiliary pattern is made for the selected first substrate pattern or the second substrate pattern, and based on the auxiliary pattern, the current layer pattern that intersects with the selected first substrate pattern or the second substrate pattern can be selected, and then the selected current layer pattern is edge segmented and locally reversed in size compensated, thereby improving the morphology of the photoresist pattern of the current layer pattern across substrates of different heights, improving the uniformity of the line width or spacing of the current layer pattern, and increasing the process window of the line width or spacing of the current layer pattern.

[0038] The invention is particularly suitable for improving the morphology of the photoresist pattern of the ion implantation layer pattern crossing the gate with height difference and the shallow trench isolation in the fin transistor and improving the line width uniformity and the process window.

[0039] Compared with the prior art in which improvement of the local line width uniformity of the photoresist is mostly achieved by improving the control of the lithography equipment, improving the flatness of the front substrate and increasing the focus depth of the lithography process, the present invention can improve the local line width uniformity of the ion implantation layer through OPC compensation, reduce the negative impact of the height difference of the front substrate on the photoresist ripple phenomenon, and reduce the requirements for equipment or process.

[0040] To solve this problem, an OPC compensation method for improving the local line width uniformity of the ion implantation layer is proposed to improve the local line width uniformity of the ion implantation layer and reduce the negative impact of the height difference of the front substrate on the photoresist ripple phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0042] Figure 1 It is a schematic diagram of introducing a bottom anti-reflection layer in the existing photolithography process to cause the reflected light from the substrate to form destructive interference;

[0043] Figure 2It is a schematic diagram of the structure after a bottom anti-reflection layer and a photoresist are formed when the substrate surface is uneven in the existing photolithography process;

[0044] Figure 3 It is a photoresist pattern formed by exposing a substrate with an uneven surface to a mask plate formed after the layout is corrected using an existing OPC correction method;

[0045] Figure 4 is a flow chart of an OPC correction method according to an embodiment of the present invention;

[0046] Figure 5 It is a schematic structural diagram of a bottom anti-reflection layer and a photoresist after forming the substrate surface when the substrate surface is uneven in the photolithography process corresponding to the OPC correction method of an embodiment of the present invention;

[0047] Figure 6 It is obtained by simulating with S-litho software in step 2 of the OPC correction method of the embodiment of the present invention. Figure 5 The corresponding photoresist morphology;

[0048] Figure 7 It is the layout pattern corresponding to step 2 to step 4 of the OPC correction method of the embodiment of the present invention;

[0049] Figure 8 The invention relates to a photoresist pattern formed by exposing a substrate with an uneven surface to a mask plate formed after the pattern is corrected using the OPC correction method of the embodiment of the invention. DETAILED DESCRIPTION

[0050] like Figure 4 FIG. 1 is a flow chart of an OPC correction method according to an embodiment of the present invention. The OPC correction method according to an embodiment of the present invention comprises the following steps:

[0051] Step 1: Provide a front layer pattern, wherein the front layer pattern includes a first substrate pattern and a second substrate pattern, and a substrate height difference exists between the top surface of the first substrate pattern and the top surface of the second substrate pattern. Step 1 corresponds to Figure 4 In step S101, i.e., the photolithography pattern, the front layer pattern is a layer of pattern in the photolithography pattern.

[0052] The substrate height difference allows the bottom anti-reflection layer 303 formed on the surface of the front layer pattern to have a thickness difference between the first substrate pattern and the second substrate pattern.

[0053] The thickness difference of the bottom anti-reflection layer 303 will cause the substrate residual reflection between the adjacent first substrate pattern and the second substrate pattern to have a reflection difference, and the reflection difference makes the key size or spacing of the photoresist 304 pattern corresponding to the current layer pattern 403 on the adjacent first substrate pattern and the second substrate pattern have a photoresist size difference.

[0054] The reflection difference is determined by the sizes of the first substrate pattern and the second substrate pattern.

[0055] In the embodiment of the present invention, Figure 5 As shown, the first substrate pattern includes a gate 302 .

[0056] The gate 302 covers the top surface and side surfaces of the fin.

[0057] The second substrate pattern includes a shallow trench isolation 303 ; the shallow trench isolation 303 is located between the fins; and a top surface of the shallow trench isolation 303 is lower than a top surface of the gate 302 .

[0058] In the front layer pattern, the gates 302 are arranged in parallel, and the length direction of each gate 302 is perpendicular to the length direction of the fin body; the width of the gate 302 is the gate channel length Lc. The gate 302 also extends to the surface of the shallow trench isolation 303, Figure 5 It is a cross-sectional structural diagram along the shallow trench isolation 303.

[0059] It can be seen that the top surfaces of the gate 302 and the shallow trench isolation 303 are not level. After the bottom anti-reflection layer 303 is formed, the top surface of the bottom anti-reflection layer 30 is flat but the thickness is uneven. This thickness difference will cause the top photoresist 304 to produce photoresist size differences after exposure.

[0060] In other embodiments, the first substrate pattern may also be a structure different from the gate 302 and the second substrate pattern may also be a structure different from the shallow trench isolation 303. It is only necessary to ensure that the first substrate pattern and the second substrate pattern have uneven surfaces and affect the exposure of the photoresist 304.

[0061] Step 2: Select the first substrate pattern and the second substrate pattern from the front layer pattern by a size selection method, and the reflection difference corresponding to the selected first substrate pattern and the second substrate pattern will make the photoresist size difference greater than or equal to a specified value.

[0062] An auxiliary pattern 402 is disposed on the selected first substrate pattern or the second substrate pattern.

[0063] Step 2 corresponds to Figure 4 Step S102 in the embodiment is to select gate electrodes that meet the size requirements to form auxiliary patterns.

[0064] In the embodiment of the present invention, the first substrate pattern or the second substrate pattern is selected in the following manner:

[0065] All of the gates 302 are selected to have a width greater than the critical gate channel length.

[0066] The critical gate channel length is obtained by software simulation, including:

[0067] Simulating the photoresist size difference generated by the gate 302 with different widths;

[0068] The width of the gate 302 corresponding to the specified value of the photoresist dimension difference is used as the critical gate channel length.

[0069] When the photoresist size difference is smaller than a specified value, the influence of the photoresist size difference is ignored.

[0070] Preferably, the software simulation is implemented by S-litho software. Figure 6 As shown, it is obtained by simulating with S-litho software in step 2 of the OPC correction method of the embodiment of the present invention. Figure 5 The corresponding photoresist morphology; Figure 6 In the figure, the shallow trench isolation is marked with a mark 301a, the gate is marked with a mark 302a, the bottom anti-reflection layer is marked with a mark 303a, and the photoresist is marked with a mark 304a. It can be seen that the thickness of the bottom anti-reflection layer 303a on the top of the gate 302a is relatively thin, so that the bottom anti-reflection layer 303a on the top of the gate 302a has a weaker ability to eliminate the substrate reflected light formed on the surface of the gate 302a, and the greater the width of the gate 302a, the greater the impact on the ability to eliminate the substrate reflected light; when the width of the gate 302a is less than the critical gate channel length, the effect on the pattern size of the photoresist 304a can be ignored; and when the width of the gate 302a is greater than or equal to the critical gate channel length, the line pattern size of the photoresist 304a will shrink. Figure 6 In FIG. 5 , it is shown that the lines of the photoresist 304a in the gate 302a region are all shrunk, and the spacing between the lines of the photoresist 304a is expanded. Figure 6 The critical gate channel length can be obtained in the corresponding simulation diagram.

[0071] like Figure 7 As shown, the auxiliary pattern 402 is disposed on the selected gate 302 .

[0072] In an embodiment of the present invention, the method for forming the auxiliary pattern 402 includes:

[0073] The selected gate electrode 302 is used as the marking layer pattern 401 , and the marking layer pattern 401 is extended along the width direction of the gate electrode 302 to form the auxiliary pattern 402 . Figure 7 In the embodiment, the width Lc1 of the gate 302 is selected to be greater than or equal to the critical gate channel length. In some embodiments, the auxiliary pattern 402 extends outside the length side of each gate 302 with a size of 0 nm to 20 nm.

[0074] Step three: provide a current layer original layout, and select a current layer graphic 403 in the current layer original layout that intersects with the first substrate graphic or the second substrate graphic corresponding to the auxiliary graphic 402.

[0075] Figure 7 The current layer graphic 403 that will intersect with the first substrate graphic or the second substrate graphic corresponding to the auxiliary graphic 402 is shown.

[0076] In the embodiment of the present invention, the current layer is an ion implantation layer, the current layer pattern 403 is an ion implantation layer pattern, and the ion implantation region is located in the spacing region of the ion implantation pattern, that is, the current layer pattern 403 is a spacing region.

[0077] Step 4: perform edge segmentation and local reverse size compensation on the selected current layer pattern 403, wherein the local reverse size compensation is used to offset the photoresist size difference caused by the reflection difference.

[0078] In the embodiment of the present invention, Figure 7 As shown, the edge segmentation is to segment the edge 404 of the intersection area of ​​the ion implantation layer pattern and the auxiliary pattern 402; the local reverse size compensation is to move the segmented edge 404 of the ion implantation layer pattern toward the inside of the ion implantation layer pattern by a compensation size d1, and the moved edge is shown by the dotted line corresponding to the mark 405.

[0079] In some embodiments, the compensation dimension d1 is adjusted according to the width of the gate 302 and the process parameters of the bottom anti-reflection layer 303 .

[0080] The process parameters of the bottom anti-reflection layer 303 include optical parameters, thickness, exposure energy, and the like.

[0081] The optical parameters of the bottom anti-reflection layer 303 include an extinction coefficient and a refractive index.

[0082] Steps 3 and 4 correspond to Figure 4Step S103 in the embodiment is to obtain an initial target pattern by means of segmented correction of the auxiliary pattern. The current layer pattern 403 of the current layer original layout after the local reverse size compensation is the initial target pattern.

[0083] Step 5: Perform OPC correction on the original layout of the current layer after the local reverse size compensation.

[0084] In the embodiment of the present invention, the OPC correction in step 5 includes:

[0085] Perform rule-based OPC corrections, i.e. Figure 4 In step S104, the final target graph is obtained based on the rule-based OPC.

[0086] and model-based OPC correction. Figure 4 Step S105 in which the mask pattern is obtained based on the OPC of the model

[0087] Finally, it is necessary to publish a photomask, i.e. a photoresist, and use the photoresist to perform exposure and analyze the results. Figure 4 In step S106, the analysis result is exposed.

[0088] In the embodiment of the present invention, before performing OPC correction on the original layout of the current layer, the current layer pattern 403 in the original layout of the current layer is preprocessed according to the previous layer pattern. This preprocessing is to select the first substrate pattern or the second substrate pattern that will make the photoresist size difference greater than or equal to the specified value according to the sizes of the first substrate pattern and the second substrate pattern with the substrate height difference in the previous layer pattern. This is mainly based on the fact that under the condition that the thickness difference of the bottom anti-reflection layer is determined by the known substrate height difference, the reflection difference of the substrate residual reflection between the adjacent first substrate pattern and the second substrate pattern is determined by the sizes of the first substrate pattern and the second substrate pattern, and the reflection difference will determine the photoresist 304 pattern corresponding to the current layer pattern 403 on the adjacent first substrate pattern and the second substrate pattern. The difference in the key size or spacing of the shape is the difference in the photoresist size, so the first substrate pattern or the second substrate pattern whose difference in the reflective photoresist size is greater than or equal to the specified value can be selected by selecting the size of the first substrate pattern and the second substrate pattern; then an auxiliary pattern 402 is made for the selected first substrate pattern or the second substrate pattern, and according to the auxiliary pattern 402, a current layer pattern 403 intersecting with the selected first substrate pattern or the second substrate pattern can be selected, and then the selected current layer pattern 403 is edge segmented and locally reversed in size compensated, thereby improving the morphology of the photoresist 304 pattern of the current layer pattern 403 across substrates of different heights, improving the uniformity of the line width or spacing of the current layer pattern 403, and increasing the process window of the line width or spacing of the current layer pattern 403.

[0089] The embodiment of the present invention is particularly suitable for improving the morphology of the photoresist 304 pattern of the ion implantation layer pattern crossing the gate 302 and the shallow trench isolation 303 with a height difference in the fin transistor and improving the line width uniformity and process window.

[0090] Compared with the prior art in which improvement of the local line width uniformity of the photoresist 304 is mostly achieved by improving the control of the lithography equipment, improving the flatness of the front substrate, and increasing the focus depth of the lithography process, the embodiment of the present invention can improve the local line width uniformity of the ion implantation layer through OPC compensation, reduce the negative impact of the height difference of the front substrate on the ripple phenomenon of the photoresist 304, and reduce the requirements for equipment or process.

[0091] To solve this problem, in order to improve the local line width uniformity of the ion implantation layer and reduce the negative impact of the height difference of the front substrate on the ripple phenomenon of the photoresist 304, an OPC compensation method for improving the local line width uniformity of the ion implantation layer is proposed.

[0092] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An OPC correction method, characterized in that, it includes the following steps: Step 1: Provide a front-layer pattern, the front-layer pattern includes a first substrate pattern and a second substrate pattern, and there is a substrate height difference between the top surface of the first substrate pattern and the top surface of the second substrate pattern; The substrate height difference causes the bottom anti-reflection layer formed on the surface of the front-layer pattern to have a thickness difference on the surfaces of the first substrate pattern and the second substrate pattern; The thickness difference of the bottom anti-reflection layer causes a reflection difference in the substrate residual reflection between the adjacent first substrate pattern and the second substrate pattern, and the reflection difference causes a photoresist size difference in the critical dimension or pitch of the photoresist pattern corresponding to the current-layer pattern on the adjacent first substrate pattern and the second substrate pattern; The reflection difference is determined by the sizes of the first substrate pattern and the second substrate pattern; The first substrate pattern includes a gate; the gate covers the top surface and the side surface of the fin body; The second substrate pattern includes a shallow trench isolation; the shallow trench isolation is located between the fin bodies; the top surface of the shallow trench isolation is lower than the top surface of the gate; In the front-layer pattern, the gates are arranged in parallel, and the length direction of each gate is perpendicular to the length direction of the fin body; the width of the gate is the gate channel length; Step 2: Select the first substrate pattern and the second substrate pattern in the front-layer pattern by a size selection method, and the selected reflection difference between the first substrate pattern and the second substrate pattern causes the photoresist size difference to be greater than or equal to a specified value; An auxiliary pattern is provided on the selected first substrate pattern or the second substrate pattern; In Step 2, the implementation method of selecting the first substrate pattern or the second substrate pattern is: Select all the gates with a width greater than the critical gate channel length; The critical gate channel length is obtained through software simulation, including: Simulating the photoresist size difference generated by the gates with different widths; Taking the width of the gate corresponding to the specified value of the photoresist size difference as the critical gate channel length; The auxiliary pattern is provided on the selected gate; the formation method of the auxiliary pattern includes: Taking the selected gate as a mark-layer pattern, and extending and expanding the mark-layer pattern along the width direction of the gate to form the auxiliary pattern; The size of the auxiliary pattern extending outside the length sides of each gate is 0 nm to 20 nm; Step 3: Provide the original layout of the current layer, and select the current-layer pattern that intersects with the first substrate pattern or the second substrate pattern corresponding to the auxiliary pattern in the original layout of the current layer; Step 4: Perform edge segmentation on the selected current-layer pattern and perform local reverse size compensation, and the local reverse size compensation is used to offset the photoresist size difference generated by the reflection difference; Step 5: Perform OPC correction on the original layout of the current layer that has undergone the local reverse size compensation.

2. The OPC correction method according to claim 1, characterized in that: When the difference in the photoresist size is less than the specified value, the influence caused by the difference in the photoresist size is ignored.

3. The OPC correction method according to claim 1, characterized in that: the software simulation is implemented by S-litho software.

4. The OPC correction method according to claim 1, characterized in that: the current layer is an ion implantation layer, the current layer pattern is an ion implantation layer pattern, and the ion implantation region is located in the spacer region of the ion implantation layer pattern.

5. The OPC correction method according to claim 4, characterized in that: in step four, the edge segmentation is to segment the edge of the intersection region of the ion implantation layer pattern and the auxiliary pattern; the local reverse size compensation is that the segmented edge of the ion implantation layer pattern moves inward to the ion implantation layer pattern by a compensation size.

6. The OPC correction method according to claim 5, characterized in that: the compensation size is adjusted according to the width of the gate and the process parameters of the bottom anti-reflection layer.

7. The OPC correction method according to claim 6, characterized in that: the process parameters of the bottom anti-reflection layer include optical parameters, thickness and exposure energy.

8. The OPC correction method according to claim 7, characterized in that: the optical parameters of the bottom anti-reflection layer include extinction coefficient and refractive index.

9. The OPC correction method according to claim 1, characterized in that: the OPC correction in step five includes performing rule-based OPC correction and model-based OPC correction in sequence.

Images