Access Processing Device and Method, Processing Equipment, Electronic Equipment, and Storage Medium

Abstract

An access processing device, an access processing method, a processing device, an electronic device, and a computer-readable storage medium. The access processing device includes a first interconnection module, a second interconnection module, and at least one address interleaving module coupled between the first interconnection module and the second interconnection module. The first interconnection module is configured to transmit an access transaction for a third device sent by a first device to the address interleaving module corresponding to the access transaction; each address interleaving module is configured to perform address interleaving processing on the access transaction received from the first interconnection module, and send the multiple sub-access transactions obtained by the processing to the second interconnection module; the second interconnection module is configured to separately send the multiple sub-access transactions to one or more of the multiple second devices corresponding to the multiple sub-access transactions to access the third device. The access processing device can make the number setting of the address interleaving modules more flexible and can improve the efficiency of processing the positioning problem.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an access processing device, an access processing method, a processing device, an electronic device, and a computer-readable storage medium. Background Art

[0002] An SOC (System on Chip) chip can implement functions such as signal acquisition, conversion, storage, processing, and I / O. With the continuous improvement of integrated circuit technology, the operating frequency and performance requirements of the chip are getting higher and higher, and more and more systems on chip integrate multiple memory controllers to enable the chip to have a larger memory bandwidth. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides an access processing device, which includes a first interconnection module, a second interconnection module, and at least one address interleaving module. The first interconnection module is configured to be coupled to at least one first device; the second interconnection module is configured to be coupled to a plurality of second devices, and the plurality of second devices are configured to control access to a third device; at least one address interleaving module is respectively coupled between the first interconnection module and the second interconnection module; the first interconnection module is configured to transmit an access transaction for the third device sent by the first device to the address interleaving module corresponding to the access transaction among the at least one address interleaving module; each address interleaving module is configured to perform address interleaving processing on the access transaction received from the first interconnection module, and send the obtained multiple sub-access transactions to the second interconnection module; the second interconnection module is configured to send the multiple sub-access transactions to one or more of the plurality of second devices corresponding to the multiple sub-access transactions respectively to access the third device.

[0004] For example, in the access processing device provided in an embodiment of the present disclosure, the first interconnection module includes a network on chip.

[0005] For example, in the access processing device provided in an embodiment of the present disclosure, the second interconnection module includes a network on chip, a crossbar switch matrix, or a ring bus.

[0006] For example, in the access processing device provided in an embodiment of the present disclosure, the number of the at least one address interleaving module is greater than or equal to the number of the plurality of second devices.

[0007] For example, in the access processing device provided in an embodiment of the present disclosure, the at least one address interleaving module includes a plurality of address interleaving modules, and the plurality of address interleaving modules are configured to respectively process access transactions for a plurality of different sub-address spaces of the third device.

[0008] For example, in the access processing device provided in an embodiment of the present disclosure, the plurality of address interleaving modules include a first address interleaving module and a second address interleaving module. The first address interleaving module is configured to process access transactions to a first sub-address space of the third device, and the second address interleaving module is configured to process access transactions to a second sub-address space of the third device. The capacity of the first sub-address space is the same as or different from the capacity of the second sub-address space.

[0009] For example, in the access processing device provided in an embodiment of the present disclosure, the plurality of address interleaving modules are configured to adjust the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules.

[0010] For example, in the access processing device provided in an embodiment of the present disclosure, the plurality of address interleaving modules are configured to adjust the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules according to their respective historical access frequencies.

[0011] For example, in the access processing device provided in an embodiment of the present disclosure, each of the at least one address interleaving module is configured to perform the address interleaving process according to its respective interleaving configuration rule; the at least one address interleaving module includes a first address interleaving module and a second address interleaving module, and the interleaving configuration rule of the first address interleaving module is the same as or different from the interleaving configuration rule of the second address interleaving module.

[0012] For example, in the access processing device provided in an embodiment of the present disclosure, the interleaving configuration rule includes an interleaving address range and / or an interleaving granularity. The interleaving address range is used to limit the address range of the access address space of each sub-access transaction processed by the at least one address interleaving module, and the interleaving granularity is used to limit the size of the access address space of each sub-access transaction processed by the at least one address interleaving module.

[0013] At least one embodiment of the present disclosure provides an access processing method, including: transmitting, by a first interconnect component, an access transaction sent by a first device to a third device to an address interleaving module corresponding to the access transaction in at least one address interleaving module; performing, by the at least one address interleaving module, an address interleaving process on the access transaction received from the first interconnect module, and sending the plurality of sub-access transactions obtained by the process to the second interconnect module; and respectively sending, by the second interconnect component, the plurality of sub-access transactions to one or more of the plurality of second devices corresponding to the plurality of sub-access transactions, so as to access the third device through the plurality of second devices, wherein the at least one address interleaving module is respectively coupled between the first interconnect module and the second interconnect module.

[0014] At least one embodiment of the present disclosure provides a processing device, including an access processing device provided by any embodiment of the present disclosure; and at least one first device, a plurality of second devices, and a third device.

[0015] For example, in the processing device provided by an embodiment of the present disclosure, the second device includes a storage controller, the third device is a storage device, and the plurality of second devices are configured to respectively control a part of the storage space of the storage device.

[0016] At least one embodiment of the present disclosure provides an electronic device, including a processor; a memory including one or more computer program modules; wherein, the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the access processing method provided by any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which can implement the access processing method provided by any embodiment of the present disclosure when executed by a computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0019] Figure 1 Shows a schematic diagram of a SOC chip;

[0020] Figure 2 Shows a schematic diagram of an access processing device provided by at least one embodiment of the present disclosure;

[0021] Figure 3 Shows a schematic diagram of address interleaving provided by at least one embodiment of the present disclosure;

[0022] Figure 4 Shows a flowchart of an access processing method provided by at least one embodiment of the present disclosure;

[0023] Figure 5 Shows a block diagram of a processing device provided by at least one embodiment of the present disclosure;

[0024] Figure 6 Shows a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0025] Figure 7 Shows a schematic block diagram of another electronic device provided by at least one embodiment of the present disclosure; and

[0026] Figure 8 The figure shows a schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an", or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "including" or "comprising" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to represent relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] Figure 1 The figure shows a schematic diagram of an SOC chip. As Figure 1 shown, the SOC chip may integrate or externally connect, for example, a DDR (Double Data Rate) memory 101, and for the DDR memory 101, a DDR controller 102 may be provided, and the DDR controller 102 is used to control access to the DDR memory 101. Figure 1 Each MC (Memory Controller) module shown, for example, may represent a DDR controller. Each MC module manages a partial storage space in the DDR memory 101. For example, the storage space of the DDR memory may be divided into multiple DDRs, and each MC module is used to manage one DDR. For example, each MC module is used to manage write operations and read operations for the corresponding DDR.

[0030] Each IP module 103 represents, for example, a device that can actively initiate operations outward. Each IP module 103 can, for example, issue access transactions to the DDR memory. The IP modules can be various functional modules, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a DPU (Data Processing Unit), a DMA (Direct Memory Access), etc. For example, it can be the processor itself or a processing core of a multi-core processor. The chip can also include an on-chip interconnect module 104. The on-chip interconnect module 104 is, for example, a Network on Chip (NOC) module. The NOC module can route the access transactions initiated by the IP modules to the corresponding MC modules for the DDR memory, and the MC modules can implement the access operations to the DDR memory. The access transactions can be writes or reads to the DDR memory.

[0031] Continuous access operations by the same MC module will cause delays. Therefore, in some examples, to increase the bandwidth, through the address interleaving module 105, the access operations originally sent to the same MC module can be distributed to multiple different MC modules, and the access operations originally processed sequentially by the same MC module are changed to be processed in parallel by multiple MC modules simultaneously to improve the performance of accessing the DDR memory. For example, an access operation to a DDR can be divided into multiple sub-access operations, and the destination addresses of the multiple sub-access operations can correspond to different DDRs. The multiple sub-access operations are sent to multiple MC modules respectively, and the multiple MC modules are used to process the multiple sub-access operations, thereby implementing the processing of the access operations, and thus the processing efficiency of the access transaction can be improved, which is equivalent to increasing the bandwidth for accessing the DDR.

[0032] Figure 1 The acc module in [description] represents the address interleaving module. Each IP module is connected to an acc module, and through this acc module, it is connected to the NOC module. Each IP module can first send its access transaction to the corresponding acc module. After the address interleaving processing of the access transaction by the acc module, multiple sub-access transactions are obtained, and then the acc module sends the multiple sub-access transactions to the corresponding multiple MC modules through the NOC module respectively. For example, each MC module processes one of the sub-access transactions, so that this access operation can be completed using multiple MC modules.

[0033] However, in the above solution, an address interleaving module needs to be added to the output of each IP module to implement the complex address interleaving function. For a large-scale SOC chip, the number of IP modules may reach dozens or hundreds. Then, dozens or hundreds of such address interleaving modules are required, which increases the chip area, power consumption, as well as the workload of design and chip verification. Moreover, after the operations sent by the IP module are address-interleaved by the address interleaving module, the addresses will become chaotic, making the addresses of the transactions (Transaction, a term belonging to the AMBA AXI bus, and an operation sent by the IP module can be called a Transaction) transmitted on the bus less intuitive. During the SOC test, problems need to be located frequently. Connecting the address interleaving module at the output of the IP module means that after the operations are output from the IP module, the subsequent operations become irregular, which increases the difficulty of locating problems during the test and debugging processes.

[0034] At least one embodiment of the present disclosure provides an access processing device, an access processing method, a processing device, an electronic device, and a computer-readable storage medium. The access processing device includes a first interconnection module, a second interconnection module, and at least one address interleaving module. The first interconnection module is configured to be coupled to at least one first device; the second interconnection module is configured to be coupled to a plurality of second devices, wherein the plurality of second devices are configured to control access to a third device; at least one address interleaving module is respectively coupled between the first interconnection module and the second interconnection module; the first interconnection module is configured to transmit an access transaction for the third device sent by the first device to the address interleaving module corresponding to the access transaction among at least one address interleaving module; each address interleaving module is configured to perform address interleaving processing on the access transaction received from the first interconnection module, and send the processed multiple sub-access transactions to the second interconnection module; the second interconnection module is configured to respectively send the multiple sub-access transactions to one or more of the plurality of second devices corresponding to the multiple sub-access transactions to access the third device.

[0035] According to the access processing device of the embodiments of the present disclosure, by arranging the address interleaving module (which can be abbreviated as the acc module) behind the first interconnection module (such as the NOC module) (between the first interconnection module and the second device), and using the first interconnection module to transmit the access transactions initiated by each first device (for example, a certain IP module) to the address interleaving module corresponding to the destination address of the access transaction for processing. Based on this method, it is not necessary to set an address interleaving module for each first device, but any number of address interleaving modules can be set, making the setting of the number of address interleaving modules more flexible. For example, for a large chip, the number of IP modules can reach seventy or eighty. By using the access processing device of the embodiments of the present disclosure, the number of address interleaving modules can be reduced to a single digit (the specific number can be determined according to the actual situation). Therefore, compared withFigure 1 For the situation shown, the purpose of reducing the number of address interleaving modules can be achieved, thereby reducing the chip area, power consumption, and the workload of design and chip verification. Moreover, in the embodiments of the present disclosure, the position of the address interleaving module is shifted backward compared with the prior art, and the operation addresses before the address interleaving module are intuitive, which increases the path from the IP module to the address interleaving module and greatly improves the efficiency of locating problems.

[0036] It should be noted that the "front" and "back" in the embodiments of the present disclosure are relative to the transmission line of the access transaction. The module that the access transaction reaches first is in front of the module that the access transaction reaches later. For example, if the first interconnection module receives the access transaction earlier than the address interleaving module, the first interconnection module is located before the address interleaving module.

[0037] In the present disclosure, the interconnection module adopts an on-chip interconnection method, which is different from, for example, Figure 1 the direct connection method shown. The on-chip interconnection method includes, for example, a network on chip (NOC) or die-to-die connection (D2D). The network on chip may include a switch network, a tree network, a ring network, a mesh network, or a torus network, or any combination thereof.

[0038] Figure 2 FIG. shows a schematic diagram of an access processing device provided by at least one embodiment of the present disclosure.

[0039] As Figure 2 shown, the access processing device includes a first interconnection module 201, a second interconnection module 202, and at least one address interleaving module 203. The first interconnection module 201 is configured to be coupled to at least one first device 204. The second interconnection module 202 is configured to be coupled to a plurality of second devices 205. The plurality of second devices 205 are configured to control access to a third device 206. The at least one address interleaving module 203 is respectively coupled between the first interconnection module 201 and the second interconnection module 202.

[0040] For example, the first interconnection module 201 is configured to transmit an access transaction for the third device 206 sent by the first device 204 to the address interleaving module corresponding to the access transaction in the at least one address interleaving module. Each address interleaving module 203 is configured to perform address interleaving processing on the access transaction received from the first interconnection module 201, and send the processed multiple sub-access transactions to the second interconnection module 202. The second interconnection module 202 is configured to respectively send the multiple sub-access transactions to one or more of the plurality of second devices 205 corresponding to the multiple sub-access transactions to access the third device 206.

[0041] For example, Figure 2 Each IP module shown may represent a first device 204. The number of the first devices 204 may be one or more, which may be specifically set according to actual requirements. The first device 204 may be, for example, a CPU, a GPU, a DPU, a DMA, etc., and may be, for example, a processor or a processing core of a multi-core processor. Each first device 204 may send out an access transaction (i.e., an access operation) to a third device 206. The third device 206 may be a memory, such as a DDR memory. In some of the following embodiments, the third device is taken as a DDR memory as an example for illustration, but the present disclosure is not limited thereto. The third device 206 may also be other types of memories, and the present disclosure does not limit the type of the DDR memory as an example, and may be, for example, a memory conforming to versions such as DDR, DDR2, DDR3, DDR4, or DDR5. For example, the access transaction sent by the first device 204 includes the destination address to be accessed and the type of operation to be performed. The access destination address may be a segment of the address space of the DDR memory, and the operation type may be, for example, a "read" operation or a "write" operation.

[0042] For example, Figure 2 Each MC module shown may represent a second device 205. The number of the second devices 205 may be two or more. Each second device may be used to manage a part of the storage space of the DDR memory. For example, different second devices manage different parts of the storage space of the DDR memory, which do not overlap with each other. For example, the DDR memory may include n + 1 (n is a positive integer) DDRs (DDR0 to DDRn). Correspondingly, the access processing device may be provided with n + 1 MC modules (MC0 to MC3). Each MC module is used to manage one DDR. The capacities of the storage spaces of the multiple DDRs may be the same or different, that is, the capacities of the storage spaces managed by each MC module may be the same or different. For example, the capacity of the DDR memory is 16GB. Taking four MC modules (MC0 to MC3) as an example, each MC module may, for example, manage 4GB on average, or one of them manages 1GB, and the remaining three MC modules each manage 5GB, and so on. Taking the four MC modules each managing 4GB as an example, the address range corresponding to the storage space of the DDR memory is, for example: 0x0_0000_0000 to 0x3_ffff_ffff. Then the address ranges corresponding to the four MC modules MC0 to MC3 may be respectively:

[0043] 0x0_0000_0000 to 0x0_ffff_ffff;

[0044] 0x1_0000_0000 to 0x1_ffff_ffff;

[0045] 0x2_0000_0000 to 0x2_ffff_ffff;

[0046] 0x3_0000_0000 to 0x3_ffff_ffff.

[0047] For example, the first interconnect module 201 may include a network-on-chip, i.e., Figure 2 the NOC module shown. The NOC module may include a plurality of connection ports, and the connection ports may be connected through a network topology to achieve the interconnection between the connection ports. A plurality of functional modules may be coupled to the plurality of connection ports of the NOC module, and thus the interconnection between the plurality of functional modules may be achieved. There may be an access relationship between the plurality of modules coupled to the first interconnect module 201. The functional module that initiates an access operation may be referred to as a master device, and the functional module that receives and processes the access operation may be referred to as a slave device.

[0048] For example, Figure 2 each acc module shown may represent an address interleaving module 203, and the number of address interleaving modules 203 may be one or more. For example, the above at least one address interleaving module may include a plurality of address interleaving modules, i.e., the number of address interleaving modules is two or more, and the plurality of address interleaving modules may be configured to respectively process access transactions for a plurality of different sub-address spaces of the third device. For example, when the number of address interleaving modules 203 is multiple, each address interleaving module 203 may correspond to a partial address space of the DDR memory. For example, the capacities of the address spaces corresponding to each address interleaving module 203 may be the same or different. The first interconnect module 201 is coupled to each address interleaving module 203 and to each first device 204. The first device 204 may initiate an access transaction, and the first interconnect module 201 may send the access transaction initiated by the first device 204 to the corresponding address interleaving module 203 to perform an address interleaving operation on the access transaction through the address interleaving module 203.

[0049] For example, the first interconnect module 201 may determine which address interleaving module 203 to send the access transaction to according to the destination address of the access transaction and the DDR address space corresponding to each address interleaving module 203. For example, in some examples, the number of address interleaving modules 203 may be the same as the number of DDRs, and each address interleaving module 203 may be respectively configured to process access transactions for the address space of one DDR. Taking four address interleaving modules (acc0 to acc3) as an example, the address interleaving modules acc0 to acc3 respectively correspond to the address spaces of DDR0 to DDR3, and the address ranges of the access transactions corresponding to the address interleaving modules acc0 to acc3 are respectively:

[0050] 0x0_0000_0000 to 0x0_ffff_ffff;

[0051] 0x1_0000_0000 to 0x1_ffff_ffff;

[0052] 0x2_0000_0000 to 0x2_ffff_ffff;

[0053] 0x3_0000_0000 to 0x3_ffff_ffff.

[0054] In this example, the four connection ports (Nodes) on the first interconnection module 201 that are respectively connected to the address interleaving modules acc0 to acc3 can be respectively configured with the above four address ranges. If the destination address of an access transaction initiated by an IP module is between 0x0_0000_0000 and 0x0_ffff_ffff, the first interconnection module 201 can send the access transaction to the address interleaving module acc0, and the address interleaving module acc0 performs address interleaving processing on the access transaction.

[0055] For example, in the above example, the number of address interleaving modules acc is the same as the number of DDRs (i.e., the number of the second device MC), both are four, but the present disclosure is not limited to this. In some embodiments, the number of address interleaving modules can also be different from the number of DDRs. For example, when the number of DDRs is four, the number of address interleaving modules can be two, and each address interleaving module corresponds to the address spaces of two DDRs. Or, the number of address interleaving modules can be one, and the one address interleaving module corresponds to all the address spaces of the DDR memory. Any access transaction initiated by an IP module for the DDR memory is sent to the one address interleaving module 203 via the first interconnection module.

[0056] For example, for the address interleaving processing performed by the address interleaving module, the high and low bits of the address can be exchanged and shifted according to certain rules to achieve the purpose of address interleaving. In the embodiments of the present disclosure, different interleaving methods can be implemented according to actual needs to achieve the optimal effect, so the interleaving method is not limited.

[0057] Figure 3 Shows a schematic diagram of address interleaving provided by at least one embodiment of the present disclosure.

[0058] Such as Figure 3As shown, a partial address space of each DDR can be mapped to other DDRs to achieve address swapping and shifting. For example, the address space of DDR0 can be divided into several address segments A, B, C, and D, and at least some of the address segments are mapped to other DDRs. For example, address segment A is mapped to address segment A' in DDR0 (address segment A' and address segment A can be the same or different), address segment B is mapped to address segment B' in DDR1, address segment C is mapped to address segment C' in DDR2, and address segment D is mapped to address segment D' in DDR3. The address range changes before and after the address segment mapping, but the capacity can remain the same. For example, the capacities of address segment D and address segment D' are the same (e.g., both are 1G).

[0059] For example, if the address interleaving module acc0 corresponds to the address space of DDR0, the access transactions for address segments A - D issued by the IP module will be sent to the address interleaving module acc0 via the first interconnection module 201, and the address interleaving module acc0 can perform address interleaving processing on the access transactions. The address interleaving module acc0 can, for example, split the access transaction into multiple sub - access transactions according to the destination address of the access transaction (i.e., address segments A - D) and the address mapping relationship configured in the address interleaving module acc0. For example, the access transaction is split into four sub - access transactions. Among them, the destination address of the first sub - access transaction becomes A', the destination address of the second sub - access transaction becomes B', the destination address of the third sub - access transaction becomes C', and the destination address of the fourth sub - access transaction becomes D'. The above - mentioned address mapping relationship is only an example for the purpose of explaining and illustrating the embodiments of the present disclosure, and the specific mapping method can be determined according to the actual situation.

[0060] For example, each address interleaving module 203 is also coupled to the second interconnection module 202, and the second interconnection module 202 is also coupled to each second device 205. The second interconnection module 202 can send each sub - access transaction processed by the address interleaving module 203 to the second device 205 corresponding to the destination address of the sub - access transaction. For example, continuing with the above example, the second interconnection module 202 can send the first sub - access transaction to MC0 to access address segment A' in DDR0 through MC0; send the second sub - access transaction to MC1 to access address segment B' in DDR1 through MC1; send the third sub - access transaction to MC2 to access address segment C' in DDR2 through MC2, and send the fourth sub - access transaction to MC3 to access address segment D' in DDR3 through MC3. Based on the above method, an access transaction originally sent to the same MC module is split into multiple sub - access transactions sent to multiple different MC modules respectively, and multiple MC modules are used to process the same access transaction, thereby improving the processing efficiency, which is equivalent to increasing the bandwidth for accessing the DDR.

[0061] For example, the second interconnection module is different from the first interconnection module, that is, the two are not the same interconnection module or do not belong to the same (larger) interconnection module. For example, the type of the second interconnection module is different from the type of the first interconnection module. In some examples, the second interconnection module may include a Network-on-Chip (NOC). Figure 2 The NOC bridge shown can be understood as a relatively small NOC network, which is a multi-input multi-output bus bridge. In other examples, the second interconnection module may include a CrossBar. Each input link and output link of the CrossBar has a cross point, where an input link and an output link are connected by a semiconductor switch, and the forwarding of the input to a specific output is completed by controlling the semiconductor switch. In other examples, the second interconnection module may include a Ring network. The nodes in the Ring network are connected end to end to form a ring. It is convenient for each module to interact with each other without a master control for transit. The functional module sends information onto the ring through a network interface, and the message is passed through each node on the ring one by one. After the message reaches the node connected to the destination functional module, it is sent off the ring and transferred to the network interface, and then passed to the destination functional module. Based on this method, by connecting IP modules through the first interconnection module NOC, complex interactions between many IP modules and other functional modules can be realized. Since the number of acc modules and MC modules is relatively small, another interconnection module different from the first interconnection module can be used to achieve simple interconnection, which can avoid occupying the resources of the first interconnection module and make the interaction between IP modules and other functional modules smoother.

[0062] According to the access processing device of the embodiments of the present disclosure, by arranging the address interleaving module behind the first interconnection module (between the first interconnection module and the second device), and using the first interconnection module to transmit the access transactions initiated by each first module to the address interleaving module corresponding to the destination address of the access transaction for processing. Based on this method, it is not necessary to set an address interleaving module for each first device, but any number of address interleaving modules can be set, making the setting of the number of address interleaving modules more flexible. For example, for a large chip, the number of first devices can reach dozens or hundreds. By using the access processing device of the embodiments of the present disclosure, the number of address interleaving modules can be reduced to a single digit (the specific number can be determined according to the actual situation). Therefore, compared with the prior art, the purpose of reducing the number of address interleaving modules can be achieved, and thus the area, power consumption, and the workload of design and chip verification of the chip can be reduced. Moreover, compared with the prior art, the embodiments of the present disclosure move the position of the address interleaving module backward, and the operation addresses before the address interleaving module are intuitive, shortening the path of address clutter and greatly improving the efficiency of problem positioning.

[0063] For example, the number of at least one address interleaving module is greater than or equal to the number of multiple second devices. Based on this approach, each DDR can correspond to at least one address interleaving module, which can ensure the processing efficiency while reducing the number of address interleaving modules, and prevent access transactions from being delayed due to too few address interleaving modules.

[0064] For example, for a large chip, the number of IP modules can reach seventy or eighty, and the number of MC modules can be multiple, for example, less than or equal to eight. If the number of acc modules is the same as the number of MC modules, the number of acc modules can also be controlled within single digits. Compared with the solution of setting one acc module for each IP module, the embodiments of the present disclosure can reduce the number of acc modules to 1 / 10 of the original, and can basically meet the processing requirements of access tasks. Within a certain number range, the processing efficiency of access transactions increases with the increase in the number of acc modules.

[0065] For example, as described above, multiple address interleaving modules can be configured to separately process access transactions to multiple different sub - address spaces of a third device. The multiple address interleaving modules include, for example, a first address interleaving module and a second address interleaving module. The first address interleaving module is configured to process access transactions to the first sub - address space of the third device, and the second address interleaving module is configured to process access transactions to the second sub - address space of the third device. In some examples, the capacity of the first sub - address space is the same as or different from the capacity of the second sub - address space. For example, the first sub - address space can be 2G, and the second sub - address space can be 4G.

[0066] For example, the first address interleaving module and the second address interleaving module can be any two address interleaving modules among the multiple address interleaving modules, that is, the capacities of the sub - address spaces corresponding to at least two address interleaving modules are different. For example, continuing with the above example, if the frequency of access to the address space 0x0_0000_0000~0x0_ffff_ffff is several times that of the other three address spaces, then four address interleaving modules acc0~acc3 can be configured to correspond to the following address spaces respectively:

[0067] 0x0_0000_0000~0x0_7fff_ffff;

[0068] 0x0_8000_0000~0x0_ffff_ffff;

[0069] 0x1_0000_0000~0x2_7fff_ffff;

[0070] 0x2_8000_0000~0x3_ffff_ffff.

[0071] In this way, the address interleaving module acc0 and the address interleaving module acc1 can jointly process access transactions for the address space from 0x0_0000_0000 to 0x0_ffff_ffff, balancing the loads of the respective address interleaving modules. Through such address allocation, the sizes of the address ranges managed by different address interleaving modules can be different, which can better balance the bandwidth of each address interleaving module and thus improve the overall bandwidth. The above address allocation method is only an example for facilitating the understanding of the solution of the embodiments of the present disclosure. The address space corresponding to each address interleaving module can be configured according to actual needs, and the present disclosure is not limited to the above example.

[0072] For example, multiple address interleaving modules are configured to be able to adjust the sizes of the sub-address spaces respectively corresponding to the multiple address interleaving modules. For example, within a period of time, the address interleaving module acc0 corresponds to all the address space of DDR0 (for example, a 4G space), that is, the address interleaving module acc0 is used to process access transactions for all the address space of DDR0; within another period of time, the address interleaving module acc0 can be adjusted to only correspond to a part of the address space of DDR0 (for example, a 2G space), that is, the address interleaving module acc0 is adjusted to process access transactions for a part of the address space of DDR0. In this example, the remaining part of the address space of DDR0 (for example, another 2G space) can be allocated to other address interleaving modules (such as acc1), as long as it is ensured that the multiple address interleaving modules can cover all the storage space of the DDR memory. By adjusting the sizes of the sub-address spaces corresponding to the respective address interleaving modules, the loads of the multiple address interleaving modules can be adjusted according to the actual operation situation, avoiding the situation where some address interleaving modules process too many access transactions while some other address interleaving modules are idle, and realizing load balancing among the multiple address interleaving modules.

[0073] For example, multiple address interleaving modules are configured to adjust the sizes of the sub-address spaces respectively corresponding to the multiple address interleaving modules according to their respective historical access frequencies. For example, within a period of time before the current time, if the access frequency of address interleaving module acc0 is higher than the first frequency threshold (or the number of access transactions sent to the address interleaving module acc0 exceeds the quantity threshold), a part of the address segments in the sub-address space currently corresponding to the address interleaving module acc0 can be divided and allocated to one or more of the remaining address interleaving modules. For example, a part of the address segments can be allocated to the address interleaving module with an access frequency lower than the second frequency threshold (the second frequency threshold is less than the first frequency threshold), so as to relieve the load of the address interleaving module acc0 with a higher access frequency and increase the load of the relatively idle address interleaving modules, thus achieving load balancing. Another example is that within a period of time before the current time, if the access frequency of address interleaving module acc0 is higher than that of the remaining address interleaving modules (such as acc1 to acc3) and the difference between the access frequency of address interleaving module acc0 and the access frequencies of the remaining address interleaving modules is greater than a certain threshold, a part of the address segments in the sub-address space currently corresponding to the address interleaving module acc0 can be divided and allocated to one or more of the remaining address interleaving modules to relieve the load of the address interleaving module acc0. Adjusting the sub-address spaces respectively corresponding to the multiple address interleaving modules according to the historical access frequencies can accurately balance the access frequencies of the respective address interleaving modules, and further balance the loads of the respective address interleaving modules, thereby improving the overall bandwidth.

[0074] For example, each address interleaving module is configured to perform address interleaving processing according to its respective interleaving configuration rules. For example, the interleaving configuration rules include an interleaving address range and / or an interleaving granularity. The interleaving address range is used to limit the address range of the access address space of each sub-access transaction processed by at least one address interleaving module, and the interleaving granularity is used to limit the size of the access address space of each sub-access transaction processed by at least one address interleaving module.

[0075] For example, refer to Figure 3, the interleaved address range may refer to the address mapping range of the address interleaving module, such that the destination address space of the sub-access transactions processed by the address interleaving module does not exceed this address range. For example, if the address interleaving module acc0 is configured to process access transactions regarding DDR0 and can map the address space of DDR0 to the address spaces of all four DDRs, then it can be understood that the address interleaving module acc0 can perform address interleaving operations within the range of all DDRs of the DDR memory, that is, the address interleaving module acc0 can distribute the received access transactions within the entire MC range. Another example, if the address interleaving module acc0 can only map the address space of DDR0 to itself (DDR0) and DDR1, then it can be understood that the address interleaving module acc0 can only perform address interleaving operations within the address range of DDR0 to DDR1, that is, the address interleaving module acc0 can only distribute the received access transactions within the range of MC0 to MC1.

[0076] For example, the interleaving granularity is used to limit the capacity of the destination address space of the sub-access transactions processed by the address interleaving module. The interleaving granularity can be, for example, 512B, 1KB, or 4KB, etc. For example, if the interleaving granularity of the address interleaving module acc0 is 4KB, Figure 3 the size of each of the shown address segments (A - B) can be 4KB, then the address space corresponding to each of the sub-access transactions processed by the address interleaving module acc0 is not greater than 4KB.

[0077] For example, in some embodiments, the multiple interleaving modules include a first address interleaving module and a second address interleaving module, and the interleaving configuration rules of the first address interleaving module are the same as or different from those of the second address interleaving module. The first address interleaving module and the second address interleaving module can be any two address interleaving modules among the multiple address interleaving modules, that is to say, the interleaving configuration rules of at least two address interleaving modules are different. For example, the address range of the first address interleaving module is the same as or different from that of the second address interleaving module, and / or the interleaving granularity of the first address interleaving module is the same as or different from that of the second address interleaving module. Based on this method, different address interleaving modules can be configured with different interleaving rules, and each address interleaving module can be flexibly configured to meet the actual requirements, such as meeting the requirements of different IP modules in the SOC, and also facilitating address management.

[0078] For example, the access processing device according to at least one embodiment of the present disclosure can be applied to the case of die - to - die (D2D) connection. For the die - to - die connection mode, a chip is divided into multiple smaller dies, and these dies are packaged in a multi - chip module. In the multi - chip module, multiple dies are interconnected through die - to - die connections. The access processing device according to at least one embodiment of the present disclosure can be applied to such a case involving operations between different chips. For example, it can be used in the case where an IP module in one chip accesses a DDR memory in another chip, or the case where the first interconnection module and the second interconnection module are located in different chips, and so on.

[0079] At least one embodiment of the present disclosure also provides an access processing method. Figure 4 The flowchart of an access processing method provided by at least one embodiment of the present disclosure is shown.

[0080] As Figure 4 shown, the access processing method may include steps S310 to S330.

[0081] Step S310: Transmit the access transaction for the third device sent by the first device to the address interleaving module corresponding to the access transaction in at least one address interleaving module through the first interconnection component.

[0082] Step S320: Perform address interleaving processing on the access transaction received from the first interconnection module by the at least one address interleaving module, and send the multiple sub - access transactions obtained by the processing to the second interconnection module.

[0083] Step S330: Send the multiple sub - access transactions to one or more of the multiple second devices corresponding to the multiple sub - access transactions respectively through the second interconnection component, so as to access the third device through the multiple second devices. The at least one address interleaving module is respectively coupled between the first interconnection module and the second interconnection module.

[0084] It should be noted that in the embodiments of the present disclosure, the access processing method corresponds to the information transmission and processing operations of each module in the foregoing access processing device. For the specific functions of the access processing method, reference can be made to the relevant descriptions of the access processing device, which will not be elaborated here. Figure 4 The steps of the access processing method shown are only exemplary, not restrictive. According to needs, the access processing method may further include other steps.

[0085] For example, the first interconnection module includes a network - on - chip; the second interconnection module includes a network - on - chip, a cross - bar switch matrix, or a ring bus.

[0086] For example, the number of the at least one address interleaving module is greater than or equal to the number of the multiple second devices.

[0087] For example, the at least one address interleaving module includes a plurality of address interleaving modules. Step S320 may further include: processing access transactions to a plurality of different sub-address spaces of the third device through the plurality of address interleaving modules respectively.

[0088] For example, the plurality of address interleaving modules includes a first address interleaving module and a second address interleaving module. Step S320 may further include: processing an access transaction to a first sub-address space of the third device through the first address interleaving module, and processing an access transaction to a second sub-address space of the third device through the second address interleaving module, where the capacity of the first sub-address space is the same as or different from the capacity of the second sub-address space.

[0089] For example, the access processing method further includes: adjusting the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules.

[0090] For example, adjusting the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules includes: adjusting the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules according to the respective historical access frequencies of the plurality of address interleaving modules.

[0091] For example, step S320 may further include: performing address interleaving processing through each address interleaving module according to its respective interleaving configuration rule. The at least one address interleaving module includes a first address interleaving module and a second address interleaving module, and the interleaving configuration rule of the first address interleaving module is the same as or different from the interleaving configuration rule of the second address interleaving module.

[0092] For example, the interleaving configuration rule includes an interleaving address range and / or an interleaving granularity. The interleaving address range is used to limit the address range of the access address space of each sub-access transaction processed by the at least one address interleaving module, and the interleaving granularity is used to limit the size of the access address space of each sub-access transaction processed by the at least one address interleaving module.

[0093] At least one embodiment of the present disclosure further provides a processing device. Figure 5 The block diagram of a processing device provided by at least one embodiment of the present disclosure is shown.

[0094] As Figure 5 shown, the processing device 400 includes an access processing device 410, and at least one first device 420, a plurality of second devices 430, and a third device 440.

[0095] For example, the access processing device 410 may be the access processing device described in any of the above embodiments. The access processing device 410 may include a first interconnection module, a second interconnection module, and at least one address interleaving module.

[0096] The functions of the first device, the second device, the third device, and the access processing device, as well as the connection relationships and data transmission relationships among them, can be referred to Figure 2 and the above descriptions of the corresponding content, which will not be elaborated here.

[0097] At least one embodiment of the present disclosure further provides an electronic device, which includes a processor and a memory. The memory includes one or more computer program modules. The one or more computer program modules are stored in the memory and configured to be executed by the processor. The one or more computer program modules include instructions for implementing the above-mentioned access processing method. This electronic device can make the setting of the number of address interleaving modules more flexible, can achieve the purpose of reducing the number of address interleaving modules, and can improve the efficiency of locating problems.

[0098] Figure 6 It is a schematic block diagram of an electronic device provided by some embodiments of the present disclosure. As Figure 6 shown, the electronic device 500 includes a processor 510 and a memory 520.

[0099] The memory 520 is used to store non-transitory computer-readable instructions (such as one or more computer program modules). The processor 510 is used to run the non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are run by the processor 510, one or more steps in the above-mentioned access processing method can be executed. The memory 520 and the processor 510 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0100] For example, the processor 510 can be a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be of the X86 or ARM architecture, etc. The processor 510 can be a general-purpose processor or a dedicated processor, and can control other components in the electronic device 500 to execute the desired functions.

[0101] For example, the memory 520 may include any combination of one or more computer program products, and the computer program products may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 510 may run one or more computer program modules to implement various functions of the electronic device 500. Various application programs, various data, and various data used and / or generated by the application programs may also be stored in the computer-readable storage medium.

[0102] It should be noted that in the embodiments of the present disclosure, the specific functions and technical effects of the electronic device 500 may refer to the descriptions of the access processing method and the access processing device in the foregoing text, and will not be elaborated herein.

[0103] Figure 7 FIG. is a schematic block diagram of another electronic device provided by some embodiments of the present disclosure. The electronic device 600 is, for example, suitable for implementing the access processing method provided by the embodiments of the present disclosure. For example, the electronic device 600 may be a terminal device, a server, a cloud device, etc. It should be noted that Figure 7 The illustrated electronic device 600 is only an example, and it will not impose any limitations on the functions and usage scopes of the embodiments of the present disclosure.

[0104] As Figure 7 shown, the electronic device 600 may include a processing device (such as a central processing unit, a graphics processing unit, etc.) 610, which may perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 620 or the program loaded from the storage device 680 into the random access memory (RAM) 630. In the RAM 630, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 610, the ROM 620, and the RAM 630 are connected to each other through a bus 640. The input / output (I / O) interface 650 is also connected to the bus 640.

[0105] Typically, the following devices can be connected to the I / O interface 650: input devices 660 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 670 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 680 including, for example, magnetic tapes, hard disks, etc.; and a communication device 690. The communication device 690 can allow the electronic device 600 to communicate with other electronic devices wirelessly or wireline to exchange data. Although Figure 7 the electronic device 600 with various devices is shown, it should be understood that it is not required to implement or have all the shown devices, and the electronic device 600 can alternatively implement or have more or fewer devices.

[0106] For example, according to an embodiment of the present disclosure, the above access processing method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program codes for executing the above access processing method. In such an embodiment, the computer program can be downloaded and installed from a network through the communication device 690, or installed from the storage device 680, or installed from the ROM 620. When the computer program is executed by the processing device 610, the functions defined in the access processing method provided by the embodiments of the present disclosure can be realized.

[0107] At least one embodiment of the present disclosure further provides a computer-readable storage medium for storing non-transitory computer-readable instructions, which can realize the above access processing method when executed by a computer. By using this computer-readable storage medium, the number setting of the address interleaving module can be made more flexible, the purpose of reducing the number of address interleaving modules can be achieved, and the efficiency of locating problems can be improved.

[0108] Figure 8 A schematic diagram of a storage medium provided for some embodiments of the present disclosure. As Figure 8 shown, the computer-readable storage medium 700 is used to store non-transitory computer-readable instructions 710. For example, when the non-transitory computer-readable instructions 710 are executed by a computer, one or more steps in the access processing method described above can be executed.

[0109] For example, the computer-readable storage medium 700 can be applied to the above electronic device 500. For example, the storage medium 700 can be Figure 6 the memory 520 in the electronic device 500 shown. For example, the relevant description of the storage medium 700 can refer to Figure 6 the corresponding description of the memory 520 in the electronic device 500 shown, which will not be elaborated here.

[0110] The following points need to be explained:

[0111] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0112] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0113] As mentioned above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. An access processing device, comprising: A first interconnection module configured to couple to at least one first device; A second interconnection module configured to couple to a plurality of second devices, wherein the plurality of second devices are configured to control access to a third device; and At least one address interleaving module respectively coupled between the first interconnection module and the second interconnection module; Wherein the first interconnection module is configured to transmit an access transaction for the third device sent by the first device to the address interleaving module corresponding to the access transaction in the at least one address interleaving module; Each of the at least one address interleaving module is configured to perform address interleaving processing on the access transaction received from the first interconnection module and send the obtained multiple sub-access transactions to the second interconnection module; The second interconnection module is configured to respectively send the multiple sub-access transactions to one or more of the plurality of second devices corresponding to the multiple sub-access transactions to access the third device; Wherein the second interconnection module is configured to connect one of the address interleaving modules to any one of the second devices.

2. The access processing device according to claim 1, wherein, The first interconnection module includes a network-on-chip.

3. The access processing apparatus according to claim 1, wherein The second interconnection module includes a network-on-chip, a crossbar switch matrix, or a ring bus.

4. The access processing device according to claim 1, wherein, The number of the at least one address interleaving module is greater than or equal to the number of the plurality of second devices.

5. The access processing device according to claim 1, wherein, The at least one address interleaving module includes a plurality of address interleaving modules, The plurality of address interleaving modules are configured to respectively process access transactions for multiple different sub-address spaces of the third device.

6. The access processing device according to claim 5, wherein, The plurality of address interleaving modules include a first address interleaving module and a second address interleaving module, The first address interleaving module is configured to process access transactions for a first sub-address space of the third device, and the second address interleaving module is configured to process access transactions for a second sub-address space of the third device, The capacity of the first sub-address space is the same as or different from the capacity of the second sub-address space.

7. The access processing device according to claim 5, wherein, The plurality of address interleaving modules are configured to adjust the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules.

8. The access processing apparatus according to claim 7, wherein, The plurality of address interleaving modules are configured to adjust the sizes of the sub-address spaces respectively corresponding to the plurality of address interleaving modules according to their respective historical access frequencies.

9. The access processing device according to claim 1, wherein Each of the at least one address interleaving module is configured to perform the address interleaving processing according to its respective interleaving configuration rule; The at least one address interleaving module includes a first address interleaving module and a second address interleaving module, and the interleaving configuration rule of the first address interleaving module is the same as or different from the interleaving configuration rule of the second address interleaving module.

10. The access processing device according to claim 9, wherein, The interleaving configuration rule includes an interleaving address range and / or an interleaving granularity, Wherein the interleaving address range is used to limit the address range of the access address space of each of the sub-access transactions processed by the at least one address interleaving module, The interleaving granularity is used to limit the size of the access address space of each of the sub-access transactions processed by the at least one address interleaving module.

11. An access processing method, comprising: Transfer the access transaction for the third device sent by the first device to the address interleaving module corresponding to the access transaction in at least one address interleaving module through the first interconnection module; Perform address interleaving processing on the access transaction received from the first interconnection module by the at least one address interleaving module, and send the multiple sub-access transactions obtained by the processing to the second interconnection module; Send the multiple sub-access transactions to one or more of the multiple second devices corresponding to the multiple sub-access transactions respectively through the second interconnection module, so as to access the third device through the multiple second devices, wherein the at least one address interleaving module is respectively coupled between the first interconnection module and the second interconnection module; Wherein, the second interconnection module is configured to connect one of the address interleaving modules to any one of the second devices.

12. A processing device, comprising: The access processing device according to any one of claims 1-10; And At least one first device, multiple second devices and a third device.

13. The processing device according to claim 12, wherein, The second device includes a storage controller, and the third device is a storage device, wherein the multiple second devices are configured to respectively control a part of the storage space of the storage device.

14. An electronic device, comprising: A processor; A memory, including one or more computer program modules; Wherein, the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing the access processing method according to claim 11.

15. A computer-readable storage medium for storing non-temporary computer-readable instructions, which can implement the access processing method according to claim 11 when the non-temporary computer-readable instructions are executed by a computer.

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