ReRAM-based key-value database in-house computing system

Abstract

The present invention provides a ReRAM-based key-value database in-house computing framework, comprising: a memory component, a ReRAM component and a disk component; the memory component is at least configured to: accommodate random key-value pairs into sequential batch write operations; the ReRAM component comprises a storage module and a computing module; the storage module comprises at least: the highest level, the second highest level and the WAL file of the LSM-tree; the computing module is at least configured to: use a merge accelerator engine to process the highest level and the second highest level merge tasks; the disk component is at least configured to: perform low-level merge operations; for write requests, the key-value pairs are first recorded in the WAL file and stored in the memory table according to their key ranges, and for read requests, the ReRAM component is accessed when reading the highest level and the second highest level; the present invention effectively improves the write throughput of the key-value database with minimal data movement consumption and an efficient parallel computing method, and greatly alleviates the problems of write blocking and write pause.

Description

Technical Field

[0001] The present invention relates to the technical field of key-value databases. Based on a storage-computing integrated structure using a novel storage medium ReRAM, an in-store computing system for a key-value database based on ReRAM is proposed for accelerating the throughput of the key-value database. The system effectively improves the write throughput of the key-value database with minimal data movement consumption and an efficient parallel computing method, and greatly alleviates the problems of write blocking and write pause. Background Art

[0002] The statements in this section merely provide background art related to the present invention and do not necessarily constitute prior art.

[0003] Key-value storage systems based on LSM-tree, such as LevelDB and RocksDB, have been widely deployed in data-intensive applications. LSM-tree uses a memory buffer to convert random writes into sequential writes and flushes batches of data to disk in a hierarchical structure. Once the space of a certain layer is used up, a compaction process is triggered to merge all overlapping key-value items into their adjacent lower layers. However, as the amount of data increases, the merging process involves greater high I / O pressure and high computing pressure, which ultimately leads to frequent write pauses and severe throughput degradation.

[0004] The key-value storage system based on LSM-tree is mainly divided into two components, including the memory part and the disk part. The memory component is used to accommodate random key-value pairs into sequential batch write operations. The memory component maintains a memtable and an immutable memtable to store key-value pairs in the order of key size.

[0005] For the disk part, SSTable is the basic disk storage unit of the LSM-tree-based key-value storage system, which is converted from immemtable. SSTable maintains key-value pairs in multiple data blocks. When packing key-value pairs into data blocks, the same prefix of different keys (called shared prefix) is only saved once in the first key-value pair containing the shared prefix, which is called prefix compression. In addition, when compressing data blocks into SSTable, a snappy algorithm is used to iteratively compress those repeated bit fields. The principles of these two compression algorithms are similar, and both compress repeated parts through comparison operations. SSTable is logically organized into multiple levels, and the size of two adjacent levels increases by a multiple of a fixed number, generally 10. Except for the highest level (L0), the key-value pairs in a level are sorted in the order of the keys, that is, the key ranges of SSTables in the same level do not overlap. The disk also maintains log files for crash recovery, called WAL files. Each key-value pair is first written to the WAL file before being inserted into the memtable to ensure crash consistency.

[0006] The LSM-tree based key-value storage system includes two main processes, namely refresh and merge. All key-value pair write operations are first performed in memtable. If the memtable is filled up, it is converted to immemtable and can no longer be updated. Then, the immemtable is attached to L0 as a new SSTable, so the key value ranges of different SSTables in L0 may overlap.

[0007] For the merge operation, if the size of a level exceeds a preset threshold, a merge process is triggered to compress all overlapping SSTables to their adjacent lower levels. The merge process consists of three stages (i.e., decoding, merging, and encoding). Specifically, if the Nth level (L N ) reaches its capacity, the merge thread will first merge the N+1th layer (L N+1 ) and L N All SSTable files that overlap the key range of the selected file are extracted into memory and the SSTable is decoded into key-value pairs. Finally, the key-value pairs are sorted and encoded into SSTable format.

[0008] There are many works to alleviate the overhead of the merge process in key-value databases to address the write blocking and write pause problems in key-value databases. First, in order to reduce the I / O caused by the merge process, some works propose to optimize the system data structure by exploring data access patterns, such as key-value separation and hot / cold data separation. Other works turn to implementing key-value storage on top of emerging non-volatile memories (NVMs) with high capacity and low latency (such as PCM or 3D-xpoint). The main idea is to store the top layer of the LSM-tree in the NVM to reduce access latency. However, in these designs, the merge process as a computationally intensive operation has not been fully optimized, resulting in high computational pressure on the entire system and limited performance improvement. On the other hand, in order to alleviate the computational pressure caused by the merge, some works propose to offload the merge task to the FPGA and implement a multi-stage merge pipeline. However, this approach still involves a lot of data movement between disk and memory and between memory and processing units. Summary of the invention

[0009] In order to address the shortcomings of the prior art, the present invention is based on a storage and computing integrated structure using a new storage medium ReRAM, and proposes a ReRAM-based key-value database in-store computing system design for the background of accelerating the throughput of the key-value database. With minimal data movement consumption and efficient parallel computing methods, the write throughput of the key-value database is effectively improved, and the problems of write blocking and write pause are greatly alleviated.

[0010] In order to achieve the above object, the present invention adopts the following technical solution:

[0011] A ReRAM-based key-value database in-house computing system, comprising: a memory component, a ReRAM component, and a disk component;

[0012] The memory component is configured to at least: accommodate random key-value pairs into sequential batch write operations;

[0013] ReRAM components, including storage modules and computing modules;

[0014] The storage module includes at least: the top layer of the LSM-tree, the second top layer, and the WAL file;

[0015] The computing module is configured at least to: use a merge accelerator engine to process the highest layer and the second highest layer merge task;

[0016] The disk component is configured, at a minimum, to: perform a low-level merge operation;

[0017] For write requests, key-value pairs are first recorded into the WAL file and stored in the memory table according to their key range. For read requests, the ReRAM component is accessed when reading the highest and second highest layers.

[0018] As an optional further limitation, a merge accelerator engine includes: a memory array, a merge engine, and a data buffer module;

[0019] The memory array is configured to store the top level and the second-highest level of the LSM-tree and WAL files.

[0020] The merging engine includes: a decoding module, a merging module and an encoding module, which correspond to the three stages of the merging operation respectively;

[0021] The data buffer module is configured to: buffer the intermediate results of the merging engine.

[0022] As an optional further qualification, the decoding module is configured to extract key-value pairs from the SSTable in two stages:

[0023] Unpack the data block from the SSTable, including: finding repeated bit fields and restoring those fields in the data block;

[0024] Decode the key-value pairs from the data block, including: finding the shared prefix of each key-value pair to expand the original key-value pair.

[0025] As an optional further limitation, the decoding module is further configured to: set the remaining bits to zero through an AND operation, then shift the non-repeated bit field to the left and add it to the repeated bit field to obtain a complete data block.

[0026] As an optional further limitation, the decoding module is further configured to: obtain the first few bits of the first key containing the shared prefix through an RSF operation, then shift the shared prefix to the left, add the unshared part, and generate a complete key-value pair.

[0027] As an optional further limitation, the merge module is configured to sort the key-value pairs in ascending order and verify their validity, including the following process:

[0028] Convert the sort operation into multiple MIN operations, perform the nearest distance search configuration and search for the data with the closest distance to zero to complete the MIN operation, the MIN process requires the column driver to drive the bit line of the crossbar array and map the input query to the required bit line voltage level, modify the bit line drive voltage to give the bit binary weight;

[0029] Detect the charging and discharging behavior of the word line and find the binary value closest to zero. When the minimum value is found, mark the row of data as invalid and continue to repeatedly find the minimum value in the remaining data;

[0030] Validation is used to check if the entry is marked as DELETE, which is done through an XOR operation.

[0031] As an optional further limitation, the encoding module is configured to: encode the ordered key-value pairs belonging to an SSTable into its defined persistent format, including two encoding operations: determining the compressed part and recording the length of the compressed part.

[0032] As an optional further qualification, in Re-LSM the key range is divided into multiple sub-ranges and a memory table is maintained for each sub-range, replacing the immutable memory table with an index table to record the WAL file offset of each key-value pair in the memory table.

[0033] As an optional further qualification, when refreshing data to the top level, the SSTables in the top level are also divided into several sub-ranges. The SSTables in each sub-range may overlap, but the SSTables in different sub-ranges do not overlap.

[0034] When a merge of the top-level and second-level layers occurs, only the SSTables in one sub-range are recovered, and the merge processes in different sub-ranges are distributed to different ReRAM components and executed in parallel.

[0035] As an optional further qualification, an index table is maintained to record the key-value pairs in the memory buffer and their positions in the WAL. When a flush occurs, only the index table is flushed to the ReRAM component to convert the WAL file into the top-level SSTable.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] 1. The present invention utilizes the characteristics of ReRAM and proposes a PIM computing architecture for the merging process in the key-value database, which reduces the data movement overhead between the CPU and the memory and greatly reduces the computing delay of the merging process.

[0038] 2. The present invention decomposes the merging process into several independent multiplication, addition, comparison and shift operations, and designs a corresponding ReRAM circuit for acceleration for each operation.

[0039] 3. The present invention utilizes the multi-unit structure of ReRAM and designs a parallel computing model for merging operations between different layers, which greatly improves the parallelism of the merging operation and improves the overall performance of key-value database writing.

[0040] 4. The present invention divides the key range into different sub-ranges, thereby realizing fine-grained merge operations, further reducing I / O blocking, and improving the overall throughput of the system.

[0041] 5. The present invention directly converts the WAL file into the top-level SSTable file, further reducing I / O blocking and reducing computing pressure.

[0042] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0044] Figure 1 This is an overall design diagram of the key-value database in-house computing system provided by an embodiment of the present invention.

[0045] Figure 2 The overall architecture design diagram of the ReRAM bank provided in an embodiment of the present invention.

[0046] Figure 3 This is an example diagram of a fine-grained merging operation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0048] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0049] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0050] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0051] Example:

[0052] like Figure 1 , Figure 2 and Figure 3As shown, Embodiment 1 of the present invention provides a ReRAM-based key-value database in-house computing system Re-LSM, which offloads certain computing and memory-intensive tasks in the high layers of the LSM-tree to the ReRAM, thereby reducing the huge computing and I / O overhead; when the high layers of the LSM-tree (i.e., L0, L1) are merged, it may saturate all system computing and memory resources, and eventually stagnate the entire system process. In addition, the memory refresh operation of dumping the memory buffer to the disk also involves a large I / O operation. Therefore, this embodiment adopts a layered DRAM-NVM-DISK hybrid storage architecture, and DRAM is used as a storage buffer to convert random writes into sequential writes. ReRAM is divided into a storage part and a computing part: the storage part is used to store certain components of the LSM-tree (e.g., L0, L1, and WAL); the computing part is used to perform in-place merge operations for these components. The disk part is used to store data at a lower level. In addition, in order to further reduce the I / O overhead, this embodiment proposes a WAL-to-SSTable conversion method to reduce I / O refreshes. Inside ReRAM, the three processes of merging are analyzed and converted into basic logical operations, which are then mapped to the crossbar array of ReRAM. Finally, the keys are divided into different fine-grained sub-ranges so that the merge operation can be performed in parallel on each sub-range.

[0053] Specifically, it includes the following:

[0054] The computing system in the key-value database mainly consists of three parts: memory part, ReRAM part and disk part.

[0055] Similar to the original LSM-tree design, the memory component is used to buffer random key-value pair writes into continuous batches. To support fine-grained parallel merges, the key range is divided into multiple sub-ranges in Re-LSM, and a memtable is maintained for each sub-range. In addition, to reduce the I / O overhead of the refresh operation, the immemtable is replaced with an index table to record the WAL file offset of each key-value pair in the memtable.

[0056] The ReRAM component is divided into a storage part and a computing part. For the storage part, some parts of the LSM-tree (i.e., L0, L1, and WAL) are offloaded to the ReRAM; for the computing part, a merge accelerator engine is designed to handle the L0-L1 merge task.

[0057] The disk component is the same as the original LSM-tree design, except that it serves to store the low level of the LSM-tree and still performs low level merge operations in the original method.

[0058] For write requests, the key-value pairs are first recorded in the WAL and stored in the memtable according to their key range; the read request path is the same as the original LSM-tree design, except that ReRAM is accessed when reading L0 and L1.

[0059] The PIM-based merge accelerator consists of three components: memory array, merge engine, and data buffer. The memory array stores L0, L1, and WAL files of the LSM-tree, which is the same as the traditional memory sub-array. The merge engine is divided into three modules: decoding module, merge module, and encoding module, corresponding to the three stages of the merge operation. The engine includes many ReRAM cross switches driven by row decoders and performs different operations through several modified peripheral circuits. The data buffer is used to buffer the intermediate results of the merge engine.

[0060] The decoding module is used to extract key-value pairs from SSTable, which is divided into two stages: decompressing data blocks from SSTable (based on the snappy algorithm) and decoding key-value pairs from data blocks (based on prefix compression).

[0061] The decompression process is to find repeated bit fields and recover those fields in the data block, and the decoding process is to find the shared prefix of each key-value pair to expand the original key-value pair. To extract the repeated bit fields in the data block, the remaining bits are set to zero through the AND operation, and then the non-repeating bit fields are shifted to the left and added to the repeated bit fields to get a complete data block. This process can be done by combining the left shift (LSF) and SUM basic operations.

[0062] In order to expand the shared prefix of the key-value pair, the first few bits of the first key containing the shared prefix are obtained through the right shift (RSF) operation, and then the shared prefix is ​​shifted to the left and the unshared part is added to generate a complete key-value pair; this process can be completed through the basic operations of LSF and SUM; the above process is mapped to the crossbar array of ReRAM.

[0063] For AND operation, by modifying the sensor amplifier (i.e., SA), the cell can output logic '1' when both batteries are in a low resistance state ('1'), and output logic '0' otherwise; the principle of RSF operation design is to convert it into a matrix-vector multiplication operation (i.e., input 1011 multiplied by the matrix stored in the ReRAM cell); LSF operation can be converted into a matrix-vector multiplication operation like RSF operation.

[0064] The merge module is used to sort the key-value pairs in increasing order and verify their validity. In Re-LSM, for the sorting part, it can be converted into multiple "MIN" operations; perform the nearest distance search configuration and search for the data closest to zero to complete the MIN operation. The MIN process requires the column driver to drive the bit line of the cross switch and map the input query to the required bit line voltage level; modify the bit line drive voltage to give the bit binary weight.

[0065] The CAM SA is responsible for detecting the charging and discharging behavior of the word line and finding the binary value closest to zero; when the minimum value is found, the row of data is marked as invalid and the search for the minimum value in the remaining data is repeated; by doing so, validity verification is used to check whether the entry is marked as "DELETE", which can be done through an XOR operation.

[0066] The encoding module is used to encode the ordered key-value pairs belonging to an SSTable into its defined persistent format, including two encoding operations. The encoding steps of the two encoding methods are similar:

[0067] (1) Determine the compressed portion (i.e., the repeated bit fields in the data block and the shared prefix of each key-value pair);

[0068] (2) Record the length of the compressed part. This process can be performed as a simple bit comparison and addition operation, which can be completed by XOR and SUM.

[0069] In the original LSM-tree design, since the key ranges of SSTables in L0 may overlap, when merging in L0, a large number of SSTables in L0 and L1 may be involved. This process involves a large amount of data and computing resources, and may even bring the entire system to a standstill.

[0070] In Re-LSM, the key range is divided into several sub-ranges, and a memtable is maintained for each sub-range. When data is refreshed to L0, the SSTables in L0 are also divided into several sub-ranges; the SSTables in each sub-range may overlap, but the SSTables in different sub-ranges do not overlap; when the L0-L1 merge occurs, fine-grained merges can be performed, and only the SSTables in one sub-range are recycled to reduce I / O and computing overhead, and the merge process in different sub-ranges can also be distributed to different ReRAM processing units for parallel execution.

[0071] In a key-value storage system based on LSM-tree, the key-value pairs will first be written to the WAL file and then inserted into the memory buffer. Therefore, before the memory buffer is flushed to disk, the key-value pairs are actually persisted in the form of WAL. In Re-LSM, in order to further reduce the I / O overhead of the refresh operation, it is recommended to maintain an index table to record the key-value pairs in the memory buffer and their positions in the WAL. When a refresh occurs, only the index table is flushed to the ReRAM component to convert the WAL file to the SSTable of L0.

[0072] The following further describes in detail the ReRAM-based parallel computing acceleration strategy and the specific calculation process of the decoding operation proposed by the present invention in combination with the algorithm pseudo code.

[0073] S1: Parallel execution of merge operations strategy

[0074] The parallelization strategy based on ReRAM computing units proposed in the present invention effectively improves the speed of data merging, improves the overall write throughput of the key-value storage system, greatly reduces the write blocking and write pause problems that occur in the process, and ensures the efficient operation of the key-value storage system.

[0075]

[0076] S2: Decoding Algorithm Strategy

[0077] The two decoding algorithms based on ReRAM proposed in the present invention reduce the time complexity of decoding operation and improve the decoding speed. The prefix decoding algorithm strategy is as follows:

[0078]

[0079]

[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A ReRAM-based key-value database in-house computing system, characterized in that: include: Memory components, ReRAM components, and disk components; The memory component is configured to at least: accommodate random key-value pairs into sequential batch write operations; ReRAM components, including storage modules and computing modules; The storage module includes at least: the top layer of the LSM-tree, the second top layer, and the WAL file; The computing module is configured at least to: use a merge accelerator engine to process the highest layer and the second highest layer merge task; The disk component is configured, at a minimum, to: perform a low-level merge operation; For write requests, the key-value pairs are first recorded in the WAL file and stored in the memory table according to their key range. For read requests, the ReRAM component is accessed when reading the highest and second highest layers; The merge module is configured to sort the key-value pairs in ascending order and verify their validity, including the following processes: Convert the sort operation into multiple MIN operations, perform the nearest distance search configuration and search for the data with the closest distance to zero to complete the MIN operation, the MIN process requires the column driver to drive the bit line of the crossbar array and map the input query to the required bit line voltage level, modify the bit line drive voltage to give the bit binary weight; Detect the charging and discharging behavior of the word line and find the binary value closest to zero. When the minimum value is found, mark the row of data as invalid and continue to repeatedly find the minimum value in the remaining data; Validation is used to check whether the entry is marked as DELETE, which is done through an XOR operation; As an optional further limitation, the encoding module is configured to: encode the ordered key-value pairs belonging to an SSTable into its defined persistent format, including two encoding operations: determining the compressed part and recording the length of the compressed part.

2. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: The decoding module is configured to extract key-value pairs from SSTable in two stages: Unpack the data block from the SSTable, including: finding repeated bit fields and restoring those fields in the data block; Decode the key-value pairs from the data block, including: finding the shared prefix of each key-value pair to expand the original key-value pair.

3. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: The decoding module is further configured to: set the remaining bits to zero through an AND operation, then shift the non-repeated bit field to the left, and add it to the repeated bit field to obtain a complete data block.

4. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: The decoding module is further configured to: obtain the first few bits of the first key containing the shared prefix through the RSF operation, then shift the shared prefix to the left, add the unshared part, and generate a complete key-value pair.

5. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: The encoding module is configured to encode the ordered key-value pairs belonging to an SSTable into its defined persistent format, including two encoding operations: determining the compressed part and recording the length of the compressed part.

6. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: In Re-LSM, the key range is divided into multiple sub-ranges, and a memory table is maintained for each sub-range. The immutable memory table is replaced with an index table to record the WAL file offset of each key-value pair in the memory table.

7. The ReRAM-based key-value database in-house computing system according to claim 6, characterized in that: When refreshing data to the top layer, the SSTables in the top layer are also divided into several sub-ranges. The SSTables in each sub-range may overlap, but the SSTables in different sub-ranges do not overlap. When a merge of the top-level and second-level layers occurs, only the SSTables in one sub-range are recovered, and the merge processes in different sub-ranges are distributed to different ReRAM components and executed in parallel.

8. The ReRAM-based key-value database in-house computing system according to claim 1, wherein: An index table is maintained to record the key-value pairs in the memory buffer and their positions in the WAL. When a flush occurs, only the index table is flushed to the ReRAM component to convert the WAL file into the top-level SSTable.

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