Control method applied to goa driving layer, goa driving device and display panel

Abstract

The application relates to a control method applied to a GOA driving layer, a GOA driving device and a display panel. The control method comprises the following steps: in a frame time, when a Normal GOA circuit in a tail stage normal area of the GOA driving layer is polled and driven, a control signal is input into a corresponding stage Dummy GOA circuit in a tail stage invalid area; wherein, in the frame time, the control signal comprises a first pulse and a second pulse; the first pulse is a starting signal of the frame time, and is used for opening a pull-up control module of the Normal GOA circuit; and the second pulse is used for closing a pull-down module of the Dummy GOA circuit. The Dummy GOA circuit is pulled down in the same frame time, the mode that the Dummy GOA circuit is pulled down in the next frame time in the prior art is changed, the Q point voltage of the Dummy GOA circuit is pulled down in advance, the compressive stress of a thin film transistor connected with the Q point is reduced, the IV characteristic is prevented from easily drifting, and the abnormal lighting of a light emitting device is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a control method applied to a GOA driving layer, a GOA driving device and a display panel. BACKGROUND

[0002] With the continuous development of display technology, in order to reduce the frame size of the display panel and reduce the cost, the GOA (Gate On Array) driving structure is widely used in the field of display panel. The GOA driving structure design has developed to many classic structures such as 20T1C type. Generally, the GOA driving structure using level transmission pull-down contains tail stage Dummy GOA (invalid GOA) circuit, and the pull-down of the pull-down module of the tail stage Dummy GOA circuit is opened by the STV (Start Voltage) signal of the next frame, but there is no level transmission of the next frame STV signal for the tail stage Dummy GOA circuit. Therefore, in the actual product, this design will cause the Q point of the tail stage Dummy GOA circuit to be at a high potential for a long time, so that the TFT (Thin Film Transistor) connected with the Q point is stressed for a longer time, the IV (current voltage) characteristic is easy to drift, resulting in that the pull-down effect of the tail stage Dummy GOA circuit on the front stage GOA circuit is poor, causing abnormal lighting. SUMMARY

[0003] Therefore, it is necessary to provide a control method applied to a GOA driving layer, a GOA driving device and a display panel for solving the problem of IV characteristic drift caused by the TFT being stressed for a longer time.

[0004] In order to achieve the above-mentioned purpose, in a first aspect, the embodiments of the present application provide a control method applied to a GOA driving layer, comprising the following steps:

[0005] In a frame time, when polling the Normal GOA circuit in the tail stage normal area of the GOA driving layer to drive, inputting a control signal to the Dummy GOA circuit of the corresponding stage in the tail stage invalid area;

[0006] Wherein, in a frame time, the control signal contains a first pulse and a second pulse; the first pulse is a start signal of a frame time, used to open the pull-up control module of the Normal GOA circuit; the second pulse is used to close the pull-down module of the Dummy GOA circuit.

[0007] In one of the embodiments, the tail stage invalid area includes M stage Dummy GOA circuits; the GOA driving layer includes X clock signal lines;

[0008] When X is less than M, and M is an integer multiple of X, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of Dummy GOA circuit.

[0009] In one of the embodiments, the tail stage of the invalid area includes M stages of Dummy GOA circuit; the GOA driving layer includes X clock signal lines;

[0010] When X is less than M, and M is not an integer multiple of X, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of Dummy GOA circuit.

[0011] Or

[0012] The rising edge of the second pulse is located at or after the falling edge of the last pulse of the second type of clock signal; the second type of clock signal is the clock signal transmitted by the clock signal line not connected to the Dummy GOA circuit.

[0013] In one of the embodiments, the tail stage of the invalid area includes M stages of Dummy GOA circuit; the GOA driving layer includes X clock signal lines;

[0014] When X is equal to M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of Dummy GOA circuit.

[0015] In one of the embodiments, the tail stage of the invalid area includes M stages of Dummy GOA circuit; the GOA driving layer includes X clock signal lines;

[0016] When X is greater than M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of Dummy GOA circuit.

[0017] Or

[0018] The rising edge of the second pulse is located at or after the falling edge of the last pulse of the second type of clock signal; the second type of clock signal is the clock signal transmitted by the clock signal line not connected to the Dummy GOA circuit.

[0019] In one of the embodiments, the pulse width of the second pulse is equal to the pulse width of the clock signal of the GOA driving layer.

[0020] In a second aspect, the embodiments of the present application provide a GOA driving device, comprising a signal inputter and a GOA driving layer;

[0021] The GOA driving layer comprises N-stage Normal GOA circuits and M-stage Dummy GOA circuits;

[0022] The stages of the Normal GOA circuits and the stages of the Dummy GOA circuits are sequentially connected; the M-stage Normal GOA circuit at the tail of the circuit formed by sequentially connecting the stages of the Normal GOA circuits is a tail-stage normal area; and the circuit formed by sequentially connecting the stages of the Dummy GOA circuits is a tail-stage invalid area.

[0023] The signal inputter is connected to the pull-down modules of the stages of the Dummy GOA circuits respectively.

[0024] The signal inputter is configured to perform the control method applied to the GOA driving layer.

[0025] In one of the embodiments, the Dummy GOA circuit comprises a pull-up control module, a pull-up module, an inverter, a pull-down maintaining module, a pull-down module and a reset module.

[0026] The first end of the pull-up control module is connected to the first end of the pull-up module, the first end of the pull-down module and the first end of the pull-down maintaining module respectively, the second end is connected to the first end of the inverter, and the third end is connected to the V SSQ signal through the reset module.

[0027] The second end of the pull-up module is connected to the second end of the pull-down maintaining module, and the third end is connected to the second end of the pull-down module; the second end of the inverter is connected to the third end of the pull-down maintaining module, and the third end is connected to the V SSQ signal.

[0028] The fourth end of the pull-down maintaining module is connected to the V SSQ signal, and the fifth end is connected to the V SSG signal; the third end of the pull-down module is connected to the V SSQ signal, and the fourth end is connected to the V SSG signal.

[0029] In one of the embodiments, the inverter comprises a first inverter and a second inverter; and the pull-down maintaining module comprises a first pull-down maintaining module and a second pull-down maintaining module.

[0030] The first end of the first pull-down maintaining module and the first end of the second pull-down maintaining module are connected to the first end of the pull-up control module respectively; the second end of the first pull-down maintaining module and the second end of the second pull-down maintaining module are connected to the second end of the pull-up module respectively; the third end of the first pull-down maintaining module is connected to the second end of the first inverter; the third end of the second pull-down maintaining module is connected to the second end of the second inverter; the fourth end of the first pull-down maintaining module and the fourth end of the second pull-down maintaining module are connected to the V SSQ signal respectively; the fifth end of the first pull-down maintaining module and the fifth end of the second pull-down maintaining module are connected to the V SSG signal respectively.

[0031] The first end of the first inverter and the first end of the second inverter are connected to the second end of the pull-up control module respectively; the third end of the first inverter and the third end of the second inverter are connected to the V SSQ signal respectively.

[0032] In a third aspect, the embodiments of the present application provide a display panel, comprising a display layer, a controller and the GOA driving device described above.

[0033] The controller is connected to the GOA driving device; and the GOA driving device is connected to the display layer.

[0034] One of the above technical solutions has the following advantages and beneficial effects:

[0035] In the process of displaying each frame of picture of the display layer, line-by-line scanning is needed. In a frame of picture time length, when the line-by-line scanning reaches the last few lines, i.e. polling to the Normal GOA circuit driving in the tail stage normal area of the GOA driving layer, a control signal is input to the Dummy GOA circuit of the corresponding stage in the tail stage invalid area. The control signal contains a first pulse and a second pulse, wherein the first pulse is a start signal of the frame of picture time length, used to open the pull-up control module of the Normal GOA circuit, and the second pulse is used to close the pull-down module of the Dummy GOA circuit. The Dummy GOA circuit is pulled down in the same frame of picture time length, which changes the mode that the Dummy GOA circuit is pulled down in the next frame of picture time length in the traditional technology, thereby the Q point voltage of the Dummy GOA circuit is pulled down in advance, the compressive stress of the thin film transistor connected to the Q point is reduced, the IV characteristic is inhibited from drifting easily, and the abnormal lighting of the light emitting device is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is an equivalent circuit diagram of the Dummy GOA circuit in the traditional technology.

[0037] Figure 2 It is Figure 1a working timing diagram of the Dummy GOA circuit.

[0038] Figure 3 a flow chart of the control method applied to the GOA driving layer provided by the embodiment of the present application.

[0039] Figure 4 a waveform diagram of the control signal provided by the embodiment of the present application.

[0040] Figure 5 a schematic diagram of the Dummy GOA circuit provided by the embodiment of the present application. DETAILED DESCRIPTION

[0041] For the purpose of facilitating the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element and integrated as a whole, or a middle element can exist at the same time. The terms "mount", "one end", "the other end" and the like used herein are only for the purpose of illustration.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0044] In the conventional technology, for example, a product with a resolution of 2160*3180 and 12 CK signals, 6-stage Dummy GOA (equivalent circuit diagram as shown in Figure 1 FIG. 1) circuit. As shown in Figure 1 FIG. 2, the pull-down of T31 / T41 of the Dummy GOA circuit (2161-2166 stages) is opened by the STV signal of the next frame. The working timing is as shown in Figure 2As shown, CK1-CK12 are clock signals, STV is the start signal of each frame, and the Reset signal is consistent with the STV signal waveform. In this product, the Q point of the Dummy GOA circuit is at a high potential for a long time, causing the TFTs (Thin Film Transistors) connected to the Q point, such as T21 / 22 and T52 / 54, to be under stress for a longer time, and the IV characteristics are prone to drift, which can cause the ST(n) output of the Dummy GOA circuit to weaken. In this product, the ST(n) of rows 2161-2166 is the pull-down signal of rows 2155-2160, so the pull-down of T31 / T41 in the (2155-2160 stage) Normal GOA circuit is affected, causing abnormal lighting.

[0045] To solve the above problems, as shown in Figure 3 A control method applied to a GOA driving layer is provided, comprising the following steps:

[0046] Step 31, during the polling of the Normal GOA circuit in the tail stage normal area of the GOA driving layer, a control signal is input to the Dummy GOA circuit in the corresponding stage of the tail stage invalid area within a frame duration.

[0047] A frame duration refers to the playing duration of a single image in an image animation. When displaying an image, the GOA driving layer will scan from the first row to the last row within a frame duration, for example, a display product with a resolution of 2048*1024 contains 1024 stages of GOA circuits, and within a frame duration, the first stage GOA circuit to the 1024th stage GOA circuit will drive the scanning lines of the corresponding rows.

[0048] The Normal GOA circuit refers to the GOA circuit connected to the scanning line, which can drive the scanning line. The Dummy GOA circuit refers to the invalid GOA circuit connected to the tail of the Normal GOA circuit. The tail stage normal area refers to the last few stages of Normal GOA circuits, and the number of Normal GOA circuits contained in the tail stage normal area is equal to the number of Dummy GOA circuits contained in the tail stage invalid area. All stages of Dummy GOA circuits are contained in the tail stage invalid area. Similarly, taking a display product with a resolution of 2048*1024 as an example, for example, the display product includes 4 stages of Dummy GOA circuits, which are connected in turn after the 1024th stage Normal GOA circuit, and the tail stage normal area includes the 4th stage (1021-1024th stage) Normal GOA circuit.

[0049] Polling to the Normal GOA circuit in the tail-level normal region of the GOA driver layer can be understood as the GOA circuit driving the scan line step by step, waiting for the Normal GOA circuit in the tail-level normal region. Similarly, taking the above-mentioned display product with a resolution of 2048*1024 as an example, polling to the Normal GOA circuit in the tail-level normal region of the GOA driver layer means that it is the turn of the first-level Normal GOA circuit in levels 1021-1024 to start working and driving the scan line.

[0050] The pull-down of the nth-level Normal GOA circuit within the normal region of the tail stage is controlled by the ST(n) signal output from the corresponding level Dummy GOA circuit within the invalid region of the tail stage. Similarly, taking the above-mentioned display product with a resolution of 2048*1024 as an example, the pull-down of the 1022nd-level Normal GOA circuit is controlled by the ST(1026) signal output from the 2nd-level Dummy GOA circuit.

[0051] The control signal is used to control the pull-down of the Dummy GOA circuit, specifically, such as... Figure 4 As shown, within one frame's duration, the control signal includes a first pulse and a second pulse. The first pulse is the start signal for one frame's duration and is used to activate the pull-up control module of the Normal GOA circuit. The second pulse is used to deactivate the pull-down module of the Dummy GOA circuit, thereby enabling the pull-down of the current-stage Dummy GOA circuit within the same frame's duration, pulling down the voltage value at point Q.

[0052] Here are some ways to set the second pulse:

[0053] In the first example, the tail-level invalid region includes M stages of dummy GOA circuitry; the GOA driver layer includes X clock signal lines. The number of stages M of the dummy GOA circuitry depends on the actual type of the GOA driver layer, and similarly, the number of clock signal lines X depends on the actual type of the GOA driver layer.

[0054] When X is less than M, and M is an integer multiple of X, the rising edge of the second pulse occurs at or after the falling edge of the last pulse of the first type of clock signal. It should be noted that the first type of clock signal is the clock signal transmitted via the clock signal line connected to the last stage of the Dummy GOA circuit. For example, when M is 6, X is 1, 2, or 3.

[0055] The rising edge of the second pulse is located at the falling edge of the last pulse of the first clock signal, which means that the rising edge of the second pulse is superimposed on the falling edge of the last pulse of the first clock signal on the time axis. The rising edge of the second pulse is located after the falling edge of the last pulse of the first clock signal, which means that the rising of the second pulse is later than the falling edge of the last pulse of the first clock signal on the time axis.

[0056] Taking a product with 3 clock signals, 6-stage Dummy GOA circuit and resolution of 2160*3180 as an example, there are 722 pulses on each clock signal, and the 772th pulse is the last pulse.

[0057] In the second example, the tail stage invalid area includes M-stage Dummy GOA circuit; the GOA driving layer includes X clock signal lines;

[0058] When X is less than M and M is not an integer multiple of X, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first clock signal. The first clock signal is the clock signal transmitted by the clock signal line connected to the last stage Dummy GOA circuit. For example, M is 6 and X is 4 or 5.

[0059] Alternatively, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the second clock signal. It should be noted that the second clock signal is the clock signal transmitted by the clock signal line not connected to the Dummy GOA circuit.

[0060] Taking a product with 4 clock signals, 6-stage Dummy GOA circuit and resolution of 2160*3180 as an example, there are 542 pulses on each clock signal, and the 542th pulse is the last pulse. The first clock signal is the clock signal transmitted by the 2nd clock signal line. The second clock signal is the clock signal transmitted by the 3rd and 4th clock signal lines.

[0061] In the third example, the tail stage invalid area includes M-stage Dummy GOA circuit; the GOA driving layer includes X clock signal lines;

[0062] When X is equal to M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first clock signal. The first clock signal is the clock signal transmitted by the clock signal line connected to the last stage Dummy GOA circuit. For example, M is 6 and X is.

[0063] Taking a product with 6 clock signals, 6-stage Dummy GOA circuit and resolution of 2160*3180 as an example, there are 361 pulses on each clock signal, and the 361th pulse is the last pulse.

[0064] In a fourth example, the tail-stage invalid area includes M-stage Dummy GOA circuits; the GOA driving layer includes X clock signal lines;

[0065] When X is greater than M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is a clock signal transmitted by a clock signal line connected to the last-stage Dummy GOA circuit. For example, M is 6 and X is 12.

[0066] Alternatively, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the second type of clock signal; the second type of clock signal is a clock signal transmitted by a clock signal line not connected to the Dummy GOA circuit.

[0067] Taking a product with a resolution of 2160*3180 and 12 clock signals and 6-stage Dummy GOA circuits as an example, there are 181 pulses on each clock signal, and the 181st pulse is the last pulse. The first type of clock signal is a clock signal transmitted by the 6th clock signal line (as shown in FIG. 6A). The second type of clock signal is a clock signal transmitted by the 7th to 12th clock signal lines. Figure 4

[0068] In one example, the pulse width of the second pulse is equal to the pulse width of the clock signal of the GOA driving layer.

[0069] During the display of each frame of the display layer, line-by-line scanning is required. During the time length of a frame, when the last few lines are scanned, i.e., polling to the Normal GOA circuit driving in the tail-stage normal area of the GOA driving layer, a control signal is input to the Dummy GOA circuit of the corresponding stage in the tail-stage invalid area. The control signal includes a first pulse and a second pulse, wherein the first pulse is a start signal of the time length of a frame, used to open the pull-up control module of the Normal GOA circuit, and the second pulse is used to close the pull-down module of the Dummy GOA circuit. The Dummy GOA circuit is pulled down in the same time length of a frame, which changes the mode of the prior art that the Dummy GOA circuit is pulled down in the next time length of a frame, thereby pulling down the Q point voltage of the Dummy GOA circuit in advance, reducing the compressive stress of the thin-film transistor connected to the Q point, suppressing the easy drift of the IV characteristic, and avoiding the abnormal lighting of the light-emitting device.

[0070] Based on the control method applied to the GOA driving layer of the present application, a GOA driving device is provided, which includes a signal inputter and a GOA driving layer.

[0071] ​The GOA driving layer includes N-level Normal GOA circuits and M-level Dummy GOA circuits.

[0072] The Normal GOA circuits and the Dummy GOA circuits are sequentially connected in stages; the Normal GOA circuits sequentially connected in stages form a tail-end M-level Normal GOA circuit at the tail end of the line; and the Dummy GOA circuits sequentially connected in stages form a tail-end invalid area. Taking N as 2160 and M as 6 as an example, the Normal GOA circuits are sequentially connected in stages from the first level to the 2160th level, and the Dummy GOA circuits from the first level to the sixth level are sequentially connected after the 2160th Normal GOA circuit.

[0073] The signal inputter is connected to the pull-down module of each level of the Dummy GOA circuit. The signal inputter is used to implement the control method applied to the GOA driving layer.

[0074] It should be noted that the control method applied to the GOA driving layer in this embodiment is the same as that in the foregoing embodiments, and will not be described again here.

[0075] In one example, as shown in FIG. 5, Figure 5 The Dummy GOA circuit includes a pull-up control module 510, a pull-up module 520, an inverter 530, a pull-down maintenance module 540, a pull-down module 550, and a reset module 560. It should be noted that the pull-up control module 510 is used to pre-charge the Q point of the Dummy GOA circuit, and the pull-up module 520 is used to output a high potential. The pull-down module 550 is used to pull down the Q point and the output of the Dummy GOA circuit. The pull-down maintenance module 540 is used to maintain the low voltage of the Q point of the Dummy GOA circuit. The inverter 530 is used to invert the phase of the input signal by 180 degrees.

[0076] The connection relationship is: the first end of the pull-up control module 510 is respectively connected to the first end of the pull-up module 520, the first end of the pull-down module 550, and the first end of the pull-down maintenance module 540, the second end is connected to the first end of the inverter 530, and the third end is connected to the V SSQ signal through the reset module 560.

[0077] The second end of the pull-up module 520 is connected to the second end of the pull-down maintenance module 540, and the third end is connected to the second end of the pull-down module 550; the second end of the inverter 530 is connected to the third end of the pull-down maintenance module 540, and the third end is connected to the V SSQ signal;

[0078] The fourth end of the pull-down maintenance module 540 is connected to the VSSQ signal, the fourth end is connected to V SSG signal; the third end of the pull-down module 550 is connected to V SSQ signal, the fourth end is connected to V SSG signal.

[0079] In one example, the inverter includes a first inverter and a second inverter; the pull-down maintenance module includes a first pull-down maintenance module and a second pull-down maintenance module. The first inverter and the first pull-down maintenance module are combined, and the second inverter and the second pull-down maintenance module are combined to work in traffic, prevent the connection point of the first inverter and the first pull-down maintenance module, and the connection point of the second inverter and the second pull-down maintenance module from being seriously forward shifted by PBTS and Vth for a long time, and G(N) cannot be pulled low.

[0080] The connection relationship is: the first end of the first pull-down maintenance module and the first end of the second pull-down maintenance module are respectively connected to the first end of the pull-up control module; the second end of the first pull-down maintenance module and the second end of the second pull-down maintenance module are respectively connected to the second end of the pull-up module; the third end of the first pull-down maintenance module is connected to the second end of the first inverter; the third end of the second pull-down maintenance module is connected to the second end of the second inverter; the fourth end of the first pull-down maintenance module and the fourth end of the second pull-down maintenance module are respectively connected to V SSQ signal; the fifth end of the first pull-down maintenance module and the fifth end of the second pull-down maintenance module are respectively connected to V SSG signal.

[0081] The first end of the first inverter and the first end of the second inverter are respectively connected to the second end of the pull-up control module; the third end of the first inverter and the third end of the second inverter are respectively connected to V SSQ signal.

[0082] The GOA driving device of the present application can realize the same frame closing of the pull-down module of the Dummy GOA circuit, pull down the potential of the Q point of the Dummy GOA circuit as soon as possible, and avoid the long-term pressure on the TFT connected to the Q point, resulting in IV characteristic drift.

[0083] The above-mentioned GOA driving device should be put into a display panel, and a display panel is provided, which includes a display layer, a controller and the above-mentioned GOA driving device; wherein the controller is connected to the GOA driving device; and the GOA driving device is connected to the display layer.

[0084] The display panel of the present application can be closed in the same frame due to the pull-down module of the Dummy GOA circuit, so that the performance of the display panel is good and abnormal lighting will not occur.

[0085] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, it is to be understood that the application embraces all such possible combinations.

[0086] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A control method applied to the GOA driving layer, characterized in that, Includes the following steps: Within the duration of one frame, when polling to the Normal GOA circuit in the tail level normal region of the GOA driving layer, a control signal is input to the Dummy GOA circuit in the corresponding level in the tail level invalid region. Within one frame's duration, the control signal includes a first pulse and a second pulse; the first pulse is the start signal for one frame's duration and is used to turn on the pull-up control module of the Normal GOA circuit; the second pulse is used to turn off the pull-down module of the Dummy GOA circuit. The number of Normal GOA circuits contained in the normal region of the tail stage is equal to and greater than 1 the number of Dummy GOA circuits contained in the invalid region of the tail stage; the invalid region of the tail stage contains Dummy GOA circuits from all stages.

2. The control method applied to the GOA driving layer according to claim 1, characterized in that, The tail-stage invalid region includes the M-stage Dummy GOA circuit; the GOA driving layer includes X clock signal lines; When X is less than M, and M is an integer multiple of X, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of the Dummy GOA circuit.

3. The control method applied to the GOA driving layer according to claim 1, characterized in that, The tail-stage invalid region includes the M-stage Dummy GOA circuit; the GOA driving layer includes X clock signal lines; When X is less than M, and M is not an integer multiple of X, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of the Dummy GOA circuit. or The rising edge of the second pulse is located at or after the falling edge of the last pulse of the second type of clock signal; the second type of clock signal is the clock signal transmitted by the clock signal line that is not connected to the Dummy GOA circuit.

4. The control method applied to the GOA driving layer according to claim 1, characterized in that, The tail-level invalid region includes the M-level Dummy GOA circuit; The GOA driver layer includes X clock signal lines; When X equals M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of the Dummy GOA circuit.

5. The control method applied to the GOA driving layer according to claim 1, characterized in that, The tail-level invalid region includes the M-level Dummy GOA circuit; The GOA driver layer includes X clock signal lines; When X is greater than M, the rising edge of the second pulse is located at or after the falling edge of the last pulse of the first type of clock signal; the first type of clock signal is the clock signal transmitted by the clock signal line connected to the last stage of the Dummy GOA circuit. or The rising edge of the second pulse is located at or after the falling edge of the last pulse of the second type of clock signal; the second type of clock signal is the clock signal transmitted by the clock signal line that is not connected to the Dummy GOA circuit.

6. The control method applied to the GOA driving layer according to any one of claims 1 to 5, characterized in that, The pulse width of the second pulse is equal to the pulse width of the clock signal of the GOA driving layer.

7. A GOA driving device, characterized in that, This includes signal input devices and the GOA driver layer; The GOA driving layer includes an N-level Normal GOA circuit and an M-level Dummy GOA circuit. The Normal GOA circuits and Dummy GOA circuits at each level are connected sequentially; the M-level Normal GOA circuit at the end of the line formed by the sequential connection of the Normal GOA circuits at each level is the tail-level normal region; the line formed by the sequential connection of the Dummy GOA circuits at each level is the tail-level invalid region. The signal input devices are respectively connected to the pull-down modules of each stage of the Dummy GOA circuit; The signal input device is used to execute the control method applied to the GOA driving layer as described in any one of claims 1 to 6.

8. The GOA driving device according to claim 7, characterized in that, The Dummy GOA circuit includes a pull-up control module, a pull-up module, an inverter, a pull-down sustain module, a pull-down module, and a reset module; The first terminal of the pull-up control module is connected to the first terminal of the pull-up module, the first terminal of the pull-down module, and the first terminal of the pull-down sustaining module, respectively. The second terminal is connected to the first terminal of the inverter. The third terminal is connected to V through the reset module. SSQ Signal; The second terminal of the pull-up module is connected to the second terminal of the pull-down sustaining module, and the third terminal is connected to the second terminal of the pull-down module; the second terminal of the inverter is connected to the third terminal of the pull-down sustaining module, and the third terminal is connected to the V... SSQ Signal; The fourth terminal of the pull-down sustaining module is connected to the V SSQ Signal, the fifth terminal is connected to V SSG Signal; the third terminal of the pull-down module is connected to the V SSQ The signal, the fourth terminal is connected to the V SSG Signal.

9. The GOA driving device according to claim 8, characterized in that, The inverter includes a first inverter and a second inverter; the pull-down sustaining module includes a first pull-down sustaining module and a second pull-down sustaining module; The first terminal of the first pull-down sustaining module and the first terminal of the second pull-down sustaining module are respectively connected to the first terminal of the pull-up control module; the second terminal of the first pull-down sustaining module and the second terminal of the second pull-down sustaining module are respectively connected to the second terminal of the pull-up module; the third terminal of the first pull-down sustaining module is connected to the second terminal of the first inverter; the third terminal of the second pull-down sustaining module is connected to the second terminal of the second inverter; the fourth terminal of the first pull-down sustaining module and the fourth terminal of the second pull-down sustaining module are respectively connected to the V SSQ Signal; The fifth terminal of the first pull-down sustaining module and the fifth terminal of the second pull-down sustaining module are respectively connected to the V SSG Signal; The first terminals of the first inverter and the second inverter are respectively connected to the second terminals of the pull-up control module; the third terminals of the first inverter and the second inverter are respectively connected to the V... SSQ Signal.

10. A display panel, characterized in that, Includes a display layer, a controller, and the GOA driving device as described in any one of claims 7-9; The controller is connected to the GOA driving device; the GOA driving device is connected to the display layer.

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