A method of manufacturing a semiconductor device

Abstract

This invention discloses a method for manufacturing a semiconductor device. The method includes: Step S1: providing a semiconductor substrate, forming a polishing barrier layer on the surface of the semiconductor substrate, forming trenches in the semiconductor substrate, and filling the trenches with first filling layers of different thicknesses to obtain first trenches and second trenches with different aspect ratios; Step S2: performing a deposition process to form an isolation material layer, the isolation material layer covering the surface of the semiconductor substrate and filling the remaining depth of the second trenches; Step S3: performing a first chemical mechanical polishing process to remove the isolation material layer from the surface of the semiconductor substrate. According to this invention, for the step difference formed after filling trenches with different aspect ratios, the distribution of polishing slurry on the polishing pad can be adjusted by adjusting the landing position of the polishing slurry supplied to the polishing pad, thereby achieving high gloss and high uniformity film quality, while significantly reducing the polishing process cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device. Background Technology

[0002] As integrated circuit device dimensions shrink, advanced processes (below 0.13µm) typically employ trench isolation (STI) technology to improve device density and isolation performance. To achieve ideal isolation, the aspect ratio (AR) of the trench isolation structure increases with each technology node. However, after HDP-CVD filling, the difference in silicon oxide thickness between the trench isolation region and the non-trench isolation region (active or active region) gradually increases, and the difference in silicon oxide thickness between the trench and the active region in the die density / ISO region is further amplified. Furthermore, in the design of deep trench structure devices with different aspect ratios, including trench gate structures and trench isolation structures, multiple materials with different aspect ratios are often used for filling. The greater the difference in aspect ratio, the greater the step difference formed after silicon oxide filling, and the larger the surface depression after filling. Additionally, due to limitations in the filling process itself, differences in film thickness often exist between the center and edge regions of the wafer surface during filling. This poses a significant challenge to the control of chemical mechanical planarization (CMP) uniformity within the wafer chip and the overall film thickness uniformity on the wafer surface.

[0003] Typical methods for improving uniformity in CMP processes often focus on individual hardware, consumables, and process parameters. Improving the polishing process by targeting a single specific factor involves hardware improvements such as zoned pressure control of the polishing head, refining the head structure, or optimizing the retainer ring to mitigate stress abrupt changes at wafer edges during polishing. Additives can be added to the polishing slurry to improve edge morphology, depending on the placement of the polishing point. Alternatively, a protective layer (nitride or photoresist) can be formed on the oxide surface of the trenches to reduce step differences. While these hardware, consumable, and single-factor optimization techniques each have their own characteristics, they all introduce new conditions and factors into the CMP process system, resulting in high implementation costs and long verification cycles. Furthermore, these methods for improving the planarization of trench isolation structures rely heavily on advanced hardware and consumables, which can improve uniformity to some extent. However, for more advanced technology nodes and devices with special structures, a single improvement cannot completely solve the polishing uniformity problem. If the residual film thickness morphology cannot be well controlled in the early stages of the STI CMP polishing process, the difference in the morphology of the previous film thickness steps will be further amplified, resulting in over-polishing of trench silicon oxide and discoloration at the center / edge of the wafer surface, which leads to a decrease in device electrical performance and a reduction in yield.

[0004] To address the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, characterized by comprising:

[0007] Step S1: Provide a semiconductor substrate, form a polishing barrier layer on the surface of the semiconductor substrate, form a trench in the semiconductor substrate, the trench includes a first trench located in a first region and a second trench located in a second region, fill the first trench and the second trench with a first filling layer, wherein the top of the first filling layer in the first trench is flush with the surface of the semiconductor substrate, and the top of the first filling layer in the second trench is lower than the surface of the semiconductor substrate;

[0008] Step S2: Perform a deposition process to form an isolation material layer that covers the surface of the semiconductor substrate and fills the remaining depth of the second trench;

[0009] Step S3: Perform a first chemical mechanical polishing process to remove the isolation material layer on the surface of the semiconductor substrate, wherein the first chemical mechanical polishing process includes:

[0010] Perform a first chemical mechanical polishing step to remove a portion of the insulating material layer from the surface of the semiconductor substrate;

[0011] A second chemical mechanical polishing step is performed to remove the remaining insulating material layer above the surface of the polishing barrier layer, wherein the polishing slurry is supplied to the polishing pad at different locations in the first and second chemical mechanical polishing steps.

[0012] For example, in the first chemical mechanical polishing step, the distance between the landing point and the center of the polishing pad is a first distance, and in the second polishing step, the distance between the landing point and the center of the polishing pad is a second distance, wherein...

[0013] The first distance is less than the second distance.

[0014] For example, in step S2, the isolation material layer in the second region has a recess, and in step S3, after the isolation material layer on the surface of the semiconductor substrate is partially removed in the first chemical mechanical polishing step, the height of the isolation material layer above the polishing barrier layer is 1.2-1.5 times the height of the bottom of the recess from the surface of the semiconductor substrate.

[0015] For example, in the first chemical mechanical polishing process, deionized water is supplied to the landing point.

[0016] For example, in the first chemical mechanical polishing step and the second chemical mechanical polishing step, the relative positions of the polishing slurry supply pipe for supplying the polishing slurry and the deionized water supply pipe for supplying the deionized water are different.

[0017] For example, in the first chemical mechanical polishing step, the polishing slurry supply pipe is located vertically above the deionized water supply pipe.

[0018] For example, in the first chemical mechanical polishing step, the polishing slurry supply pipe and the deionized water supply pipe are arranged in parallel in the horizontal direction.

[0019] For example, in the second chemical mechanical polishing step, the endpoint position of the second chemical mechanical polishing step is set by a method of motor torque endpoint detection, wherein the endpoint position is set after the second chemical mechanical polishing step has polished to the interface between the isolation material layer and the polishing barrier layer, so that the second chemical mechanical polishing step is slightly over-polished.

[0020] For example, after step S2, the method further includes:

[0021] Step S4: Remove a portion of the isolation material layer in the second trench, wherein the top of the remaining isolation material layer in the second trench is below the surface of the semiconductor substrate;

[0022] Step S5: Perform a deposition process to form a second fill layer, which covers the surface of the semiconductor substrate and fills the remaining second trench;

[0023] Step S6: Perform a second chemical mechanical polishing process to planarize the second filler layer.

[0024] For example, prior to step S6, an abrasive protective layer is formed on the surface of the second filler layer.

[0025] For example, in step S6, the second chemical mechanical polishing process includes:

[0026] Perform a third chemical mechanical polishing step to remove the polishing protective layer and partially remove the second filler layer to remove the depressions on the second filler layer;

[0027] Perform a fourth chemical mechanical polishing step to remove the remaining second filler layer.

[0028] For example, the grinding rate of the third chemimechanical grinding step is greater than the rate of the fourth chemimechanical grinding step.

[0029] For example, the second filling layer includes a gate material layer, and prior to step S5, a gate oxide layer is formed on the surface of the semiconductor substrate and on the sidewalls of the unfilled portion of the second trench.

[0030] According to the semiconductor device manufacturing method of the present invention, for the step difference formed after filling trenches with different aspect ratios, a two-step chemical mechanical polishing process is adopted to control the removal thickness of the filling layer. By adjusting the landing position of the polishing slurry supplied to the polishing pad, the distribution of the polishing slurry on the polishing pad is adjusted, thereby improving the uniformity of the chemical mechanical polishing process, achieving high gloss and high quality film quality, and significantly reducing the polishing process cost. Attached Figure Description

[0031] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0032] In the attached image:

[0033] Figures 1A-1I This is a schematic diagram of the structure of a semiconductor device formed in a manufacturing method of a semiconductor device according to an embodiment of the present invention;

[0034] Figure 2 This is a schematic diagram showing the relative positions of various components in a chemical mechanical polishing apparatus in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0035] Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0037] To fully understand the present invention, a detailed description will be provided below to illustrate the method for manufacturing the semiconductor device of the present invention. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of semiconductors. Preferred embodiments of the present invention are described in detail below; however, in addition to these detailed descriptions, the present invention may have other embodiments.

[0038] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0039] Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the invention is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art. In the drawings, for clarity, the thickness of layers and regions is exaggerated, and the same reference numerals are used to denote the same elements, and therefore their description will be omitted.

[0040] To address the problems in the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0041] Step S1: Provide a semiconductor substrate, form a polishing barrier layer on the surface of the semiconductor substrate, form a trench in the semiconductor substrate, the trench includes a first trench located in a first region and a second trench located in a second region, fill the first trench and the second trench with a first filling layer, wherein the top of the first filling layer in the first trench is flush with the surface of the semiconductor substrate, and the top of the first filling layer in the second trench is lower than the surface of the semiconductor substrate;

[0042] Step S2: Perform a deposition process to form an isolation material layer that covers the surface of the semiconductor substrate and fills the remaining depth of the second trench;

[0043] Step S3: Perform a first chemical mechanical polishing process to remove the isolation material layer on the surface of the semiconductor substrate, wherein the first chemical mechanical polishing process includes:

[0044] Perform a first chemical mechanical polishing step to remove a portion of the insulating material layer from the surface of the semiconductor substrate;

[0045] A second chemical mechanical polishing step is performed to remove the remaining insulating material layer above the surface of the polishing barrier layer, wherein the polishing slurry is supplied to the polishing pad at different locations in the first and second chemical mechanical polishing steps.

[0046] See below. Figures 1A-1I , Figure 2 and Figure 3 An exemplary description of a chemical mechanical polishing method according to the present invention is provided. Figures 1A-1I This is a schematic diagram of the structure of a semiconductor device formed in a manufacturing method of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a schematic diagram showing the relative positions of various components in a chemical mechanical polishing apparatus in a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0047] First, see Figure 1A A semiconductor substrate 100 is provided, an abrasion barrier layer is formed on the semiconductor substrate 100, and trenches are formed in the semiconductor substrate 100, the trenches including a first trench 1001 located in a first region A and a second trench 1002 located in a second region B.

[0048] The semiconductor substrate 100 may specifically be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc.

[0049] In this embodiment, the semiconductor substrate 100 is a silicon wafer.

[0050] For example, after the step of forming a trench on the semiconductor substrate 100, the method includes: forming a hard mask layer on the semiconductor substrate 100, the hard mask layer having a thermal oxide layer and a silicon nitride layer; forming a patterned photoresist layer on the hard mask layer; etching the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer, the patterned hard mask layer exposing the region where the trench is to be formed; and etching the semiconductor substrate using the patterned hard mask layer as a mask to form the trench.

[0051] In one embodiment of the present invention, as shown in FIG1, the hard mask layer includes a thermally oxidized silicon layer 101 and a silicon nitride layer 102, wherein the silicon nitride layer can serve as a polishing barrier layer for subsequent chemical mechanical polishing processes, which will be further described in subsequent steps.

[0052] It should be understood that in this embodiment, the hard mask layer including the thermally oxidized silicon layer 101 and the silicon nitride layer 102 is merely exemplary, and the use of the silicon nitride layer 102 as a polishing barrier layer is merely exemplary. Those skilled in the art should understand that any film structure that can be used to form trenches by etching a semiconductor substrate can be used as a hard mask layer. At the same time, any material that is different from the material of the first filling layer and can be used as a polishing barrier layer of the first filling layer is applicable to this invention.

[0053] Continue reading Figure 1B A first filling layer is filled in the first trench 1001 and the second trench 1002. In one example of the present invention, the first trench 1001 and the second trench 1002 are used to form a trench-type gate structure with different depths. The first filling layer filling the first trench 1001 and the second trench 1002 includes a silicon oxide layer 103 and a polysilicon layer 104. In the first trench 1001, the first filling layer completely fills the first trench 1001, such that the top of the first filling layer in the first trench 1001 is flush with the surface of the semiconductor substrate. In the second trench 1002, the first filling layer partially fills the second trench 1002, such that the top of the first filling layer in the second trench 1002 is lower than the surface of the semiconductor substrate 100.

[0054] For example, the step of filling the first trench 1001 and the second trench 1002 with a first filling layer (including a silicon oxide layer 103 and a polysilicon layer 104) includes:

[0055] A thermal oxidation process or a chemical vapor deposition process is performed to form a silicon oxide layer 103 at the bottom and sidewalls of the first trench 1001 and the second trench 1002; a deposition process is performed to form a polycrystalline silicon layer 104, which covers the surface of the semiconductor substrate 100 and fills the first trench 1001 and the second trench 1002; a chemical mechanical polishing process is performed to planarize the polycrystalline silicon layer 104 and stop it on the silicon nitride layer 102; an etching process is performed to remove the polycrystalline silicon in the trenches. The silicon layer 104 is flush with the surface of the semiconductor substrate; a photolithography process is performed to form a patterned photoresist layer, which covers the first region A and exposes the second trench 1002 in the second region B; an etching process is performed to partially remove the polysilicon layer 104 in the second trench 1002; then, an etching process is performed to partially remove the silicon oxide layer 103 on the sidewall of the second trench 1002, so that the top of the silicon oxide layer 103 in the second trench 1002 is lower than the polysilicon layer 104, forming a... Figure 1B The device structure shown.

[0056] Accordingly, trenches with different aspect ratios are formed, wherein the first trench 1001 in the first region A is completely filled, while the second trench 1002 in the second region B is partially filled. When the remaining second trench 1002 is filled, since the first trench 1001 in the first region A is already filled, the material layer filling the remaining second trench 1002 forms a step difference between the first region A and the second region B on the semiconductor substrate surface. This step difference affects the uniformity of the subsequent chemical mechanical polishing.

[0057] It should be understood that in this embodiment, the use of silicon oxide layer 103 and polysilicon layer 104 in the trench as filling layers is merely exemplary. Those skilled in the art should understand that filling the trench with any material to form trenches with different aspect ratios is applicable to this invention.

[0058] Next, continue to refer to Figure 1C A deposition process is performed to form an isolation material layer 105, which covers the surface of the semiconductor substrate 100 and fills the remaining depth of the second trench 1002.

[0059] Since the first trench 1001 in the first region A is completely filled by the silicon oxide layer 103 and the polysilicon layer 104, while the remaining portion of the second trench 1002 in the second region B is unfilled, when the isolation material layer 105 covers the surface of the semiconductor substrate 100, a step height difference is formed between the first region A and the second region B. Simultaneously, a depression is formed in the second trench 1002 in the second region B, such as... Figure 1CAs indicated by the middle arrow D, the step height difference between the first region A and the second region B, and the depression in the second groove 1002 of the second region B, lead to problems of film uniformity and localized dishing due to over-grinding during subsequent chemical mechanical polishing.

[0060] For example, the insulating material layer 105 is a silicon dioxide layer.

[0061] For example, methods for forming the insulating material layer 105 include chemical vapor deposition, physical vapor deposition, etc.

[0062] Next, a first chemical mechanical polishing process is performed to remove the insulating material layer on the surface of the semiconductor substrate shown.

[0063] In this invention, a two-step chemical mechanical polishing process is adopted. In each step of the chemical mechanical polishing process, the positions of the polishing slurry supply pipe and the deionized water supply pipe are different, so as to obtain a flattening effect with good uniformity and no depression problem.

[0064] Specifically, firstly, such as Figure 1D As shown, a first chemical mechanical polishing step is performed to partially remove the isolation material layer 105 on the surface of the semiconductor substrate 100.

[0065] In this step, by partially removing the isolation material layer 105 on the surface of the semiconductor substrate 100, the isolation material layer 105 on both the first region A and the second region B is partially removed, leaving the remaining portion of the isolation material layer 105 on the polishing barrier layer (silicon nitride layer 103).

[0066] In one example according to the invention, after the first chemical mechanical polishing step, the thickness H2 of the remaining insulating material layer 105 on the polishing barrier layer is 1.2-1.5 times the height from the lowest point of the depression D of the second region B to the surface H1 of the insulating material layer during the deposition of the insulating material layer 105.

[0067] Meanwhile, since the pattern density at the center of the wafer is often greater than that at the edge, the thickness of the isolation material layer 105 on the wafer surface near the center is often greater than that near the edge. Therefore, in the first chemical mechanical polishing step, the position of the polishing slurry supply device supplying polishing slurry to the polishing pad is adjusted so that the landing point of the polishing slurry supplied by the polishing slurry supply device to the polishing pad is close to the center of the polishing pad.

[0068] like Figure 2The diagram illustrates the positional relationship of various components on a chemical mechanical polishing platform during a first chemical mechanical polishing step according to an embodiment of the present invention. The chemical mechanical polishing platform includes a polishing slurry supply device 201, a deionized water supply device 202, and a polishing pad 203. The polishing slurry supply device 201 and the deionized water supply device 202 supply polishing slurry and deionized water, respectively, to a landing point E. The distance between landing point E and the center point A of the polishing pad 203 is adjustable.

[0069] In one embodiment of the present invention, in the first chemical mechanical polishing step, the distance between the landing point E of the polishing slurry supplied by the polishing slurry supply device and the center A of the polishing pad is 9.5-10 cm. By adjusting the distance between the landing point E of the polishing slurry supply device and the center A of the polishing pad, the distribution area of ​​the polishing slurry on the polishing pad can be adjusted, thereby adjusting the polishing rate of different areas on the wafer surface during the wafer polishing process, and thus adjusting the uniformity of wafer polishing.

[0070] In this step, the position of the polishing slurry supply device supplying polishing slurry to the polishing pad is adjusted so that the landing point of the polishing slurry supplied by the polishing slurry supply device to the polishing pad is close to the center of the polishing pad. This helps the polishing slurry to be distributed closer to the center area of ​​the wafer, increases the polishing rate in the center area of ​​the wafer, and helps to reduce the step height difference of the isolation material layer between the center area and the edge area, thereby achieving the overall flatness repair of the isolation material layer on the wafer surface (i.e., reducing the range of variation in the film thickness of the isolation material layer).

[0071] Meanwhile, in one example according to the present invention, in the first chemimechanical grinding process, deionized water is also supplied to the landing point.

[0072] In an embodiment of the present invention, the concentration of the polishing slurry can be adjusted by adjusting the amount of polishing slurry provided by the polishing slurry supply device and the amount of deionized water provided by the deionized water supply device, thereby adjusting the polishing rate of the wafer in the chemical mechanical polishing process. By reducing the difference in polishing rate between different film layers, the uniformity of the entire chemical mechanical polishing process can be adjusted.

[0073] Furthermore, in one example according to the present invention, in the first chemical mechanical polishing process, the relative positions of the polishing slurry supply pipe for supplying the polishing slurry and the deionized water supply pipe for supplying the deionized water are different in the first chemical mechanical polishing step and the second chemical mechanical polishing step.

[0074] By setting different relative positions for the grinding slurry supply pipe and the deionized water supply pipe, the mixing effect of the grinding slurry and deionized water varies. Specifically, when the grinding slurry supply pipe is positioned vertically above the deionized water supply pipe, the uniformity of the grinding slurry at the landing point E is better than when it is positioned vertically below it, resulting in better mask uniformity in the chemical mechanical polishing (CMP) step. Furthermore, compared to a horizontal arrangement of the grinding slurry supply pipe and the deionized water supply pipe, a vertically positioned grinding slurry supply pipe results in a more concentrated grinding slurry distribution, leading to a higher grinding rate. Therefore, in embodiments of the present invention, the relative positions of the grinding slurry supply pipe and the deionized water supply pipe are further adjusted to regulate the grinding slurry distribution, thereby adjusting the grinding rate and ultimately the grinding uniformity.

[0075] In one embodiment of the present invention, in the first chemical mechanical polishing step, the polishing slurry supply device is first turned on, while the deionized water supply device is not turned on, so that the distance between the polishing slurry supply device supplying polishing slurry to the landing point E on the surface of the polishing pad and the center A of the polishing pad is 9.5-10 cm; after the first polishing time period, the deionized water supply device is turned on to continue polishing. At this time, the polishing slurry supply device is set directly above the deionized water supply device, so that the polishing slurry is diluted when supplied to the landing point E, and at the same time has a high polishing rate; when the preset polishing endpoint is reached (the thickness H2 of the remaining isolation material layer 105 on the polishing barrier layer is 1.2-1.5 times the height from the lowest point of the depression D of the second region B when the isolation material layer 105 is deposited to the surface H1 of the isolation material layer), the polishing slurry supply device is turned off, while the deionized water supply device remains on, so that the distance between the landing point E of the deionized water supply device supplying deionized water on the polishing pad and the center A of the polishing pad is 8-11 cm.

[0076] Next, as Figure 1E As shown, a second chemical mechanical polishing step is performed to remove the isolation material layer 105 above the polishing barrier layer (silicon nitride layer 102).

[0077] In this step, the difference in polishing rate between the wafer center and edge regions is adjusted by changing the landing point of the polishing slurry and deionized water mixture supplied by the polishing slurry supply device and the deionized water attack device on the polishing pad, which differs from the landing point in the first chemical mechanical polishing step. In this step, uniformity of the isolation material layer distribution on the wafer surface is achieved through a small loss of the polishing barrier layer (silicon nitride layer 102).

[0078] For example, in the first chemical mechanical polishing step, the polishing slurry supply pipe supplies the polishing slurry to the polishing pad at a first distance from the center of the polishing pad, and in the second polishing step, the polishing slurry supply pipe supplies the polishing slurry to the polishing pad at a second distance from the center of the polishing pad, wherein the first distance is less than the second distance.

[0079] According to the present invention, on the surface of a semiconductor wafer after trench filling, due to the device structure design, there is a difference in the step height distribution of the filling material layer at the center and the edge. Due to the characteristics of the polishing pad itself (hardness and elasticity) and the difference in the film layer distribution on the wafer surface, there is a difference in the contact area during the polishing process between the wafer and the polishing pad. This results in different contact pressure distributions in the areas on the wafer surface with different film layer step heights, which in turn affects the distribution of fluid pressure of the polishing slurry at the interface between the wafer and the polishing pad during the polishing process, as well as the von Mises stress profile distribution at the center and edge of the wafer, leading to a difference in the polishing rate between the center and edge regions of the wafer. In the technical solution of the present invention, by controlling the landing point of the polishing slurry supplied to the polishing pad surface by the polishing slurry supply device during the polishing process, the distribution of the polishing slurry on the polishing pad surface can be improved, thereby changing the distribution of the polishing rate in the center and edge regions of the wafer during the polishing process.

[0080] After the first chemical mechanical polishing (CMP) step, the removal of part of the isolation material layer above the polishing barrier layer, coupled with adjustments to the placement of the polishing slurry on the polishing pad during the first CMP step, restores the flatness of the isolation material layer on the wafer surface (i.e., reduces the thickness variation range of the isolation material layer above the polishing barrier layer), significantly reducing the step height difference between the wafer center and edge regions. In this step, increasing the distance between the polishing slurry supply point to the polishing pad and the center of the polishing pad facilitates the distribution of the polishing slurry closer to the wafer edge region. By appropriately reducing the polishing barrier layer, flattening of the wafer center and edge regions is achieved, resolving the problems of residual material in the wafer edge region, die region damage, and excessive trench depressions caused by over-polishing. According to the method of the present invention, by changing the distance between the polishing slurry supply point to the polishing pad and the center of the polishing pad, the polishing rate of the wafer center and edge regions can be adjusted, significantly reducing polishing time and saving costs.

[0081] In one embodiment of the present invention, in the second chemical mechanical polishing step, the polishing slurry supply device and the deionized water supply device, which are positioned vertically, are first simultaneously turned on. The polishing slurry supply device is located directly above the deionized water supply device, so that the distance E between the polishing slurry supply device and the deionized water supply point on the polishing pad surface and the center A of the polishing pad is 11-11.5 cm. Polishing is carried out at a high polishing rate for a first time period. Afterward, the deionized water supply device is turned off, and polishing continues. The process continues until the target torque is reached (using motor torque endpoint detection). When the grinding endpoint (the interface between the grinding barrier layer and the isolation material layer) is reached, the deionized water supply device, which is parallel to the grinding slurry supply device and is located on the same horizontal plane as the grinding slurry supply device, is turned on. The distance between the landing point E of the grinding slurry and deionized water supplied by the grinding slurry supply device and the center A of the grinding pad is 11-11.5 cm. The grinding continues for a second time period, and over-grinding is performed at a lower grinding rate. During the over-grinding process, the isolation material layer on the wafer cladding is planarized by losing the grinding barrier layer (silicon nitride layer 103). The optimal smooth and undamaged surface is achieved with low silicon nitride loss. Finally, the grinding slurry supply device is turned off, and the distance between the landing point E of the deionized water supplied by the deionized water supply device and the center A of the grinding pad is 10-11.5 cm.

[0082] The above is an exemplary description of a semiconductor device manufacturing process according to the present invention. According to the present invention, during the filling of trenches with different aspect ratios, a two-step chemical mechanical polishing (CMP) process is used to achieve planarization to address the step height difference between the central and edge regions of the wafer caused by filling trenches with different aspect ratios. In the two-step CMP process, the distance E from the center A of the polishing pad to the landing point E of the polishing slurry supply device and the deionized water supply device is changed, thereby altering the distribution of the polishing slurry on the wafer surface and consequently changing the polishing rate of the film material in different regions of the wafer surface, thus improving the overall uniformity after the CMP process. Simultaneously with changing the landing point, the relative positions of the polishing slurry supply device and the deionized water supply device are also adjusted. By adjusting the relative positions during the mixing process of the polishing slurry and deionized water, the uniformity and distribution of the mixed polishing slurry are adjusted, thereby adjusting the polishing rate of the film material in different regions of the wafer surface, thus improving the overall uniformity after the CMP process. Compared to technical solutions that optimize from the perspectives of hardware, consumables, and single factors by changing the structure of the grinding head and the grinding fluid, the technical solution of this invention significantly reduces grinding time and saves costs.

[0083] See below for further details. Figure 1F-Figure 1IAnother embodiment of the present invention will now be described.

[0084] In step S3, after the second chemical mechanical polishing step is completed, the process further includes: performing an etching process to remove the remaining polishing barrier layer (silicon nitride layer 102), thermal oxide layer 101, and isolation material layer 105 on the surface of the semiconductor substrate, so that the top of the isolation material layer 105 in the second trench 1002 is flush with the surface of the semiconductor substrate 100.

[0085] In one embodiment of the present invention, after step S3 is executed, the following is also performed:

[0086] Step S4: Remove a portion of the isolation material layer in the second trench, wherein the top of the remaining isolation material layer in the second trench is below the surface of the semiconductor substrate;

[0087] Step S5: Perform a deposition process to form a second fill layer, which covers the surface of the semiconductor substrate and fills the remaining second trench;

[0088] Step S6: Perform a second chemical mechanical polishing process to remove the second filler layer on the surface of the semiconductor substrate.

[0089] See Figure 1F First, an etching process is performed to remove part of the isolation material layer 105 in the second trench 1002;

[0090] The method for removing a portion of the isolation material layer 105 in the second trench 1002 includes: performing a photolithography process to form a patterned photoresist layer, the patterned photoresist layer exposing the area of ​​the second trench from which the portion of the isolation material layer is to be removed; and performing an etching process using the patterned photoresist layer as a mask to remove the portion of the isolation material layer in the second trench.

[0091] Next, a deposition process is performed to form a second fill layer that covers the surface of the semiconductor substrate and fills the remaining second trench;

[0092] In one embodiment of the invention, isolation is formed in a portion of the trench via an isolation material layer 105 to ultimately form a trench-type gate structure. For example... Figure 1F As shown, by removing part of the isolation material layer 105 in the second trench 1002, the remaining part of the isolation material layer 1002 separates the upper and lower gate material layers 105, ultimately forming a gate structure that can be connected to different voltages.

[0093] In the process of forming trench gate structures with different aspect ratios, the second filling layer includes a gate oxide layer and a gate material layer.

[0094] like Figure 1F As shown, firstly, a gate oxide layer 106 is formed on the surface of the semiconductor substrate 100 and on the sidewalls of the trenches not filled by the isolation material layer 105.

[0095] Methods for forming gate oxide layers include thermal oxidation, chemical vapor deposition, or physical vapor deposition.

[0096] Next, as Figure 1G As shown, a gate material layer 107 is deposited on a semiconductor substrate 100, and the gate material layer 107 constitutes a second fill layer.

[0097] For example, the gate material layer 107 is a doped polysilicon layer.

[0098] Because the second trench 1002 in the second region B has been partially filled by the first filling layer (including the gate oxide layer 106 and the gate material layer 107) and the isolation material layer 105, the depth ratio of the remaining unfilled part of the second trench 1002 is greatly reduced. As a result, during the filling of the second filling layer (gate material layer 107), the step height difference between the first region A and the second region B is greatly reduced. However, there are still depressions in the second filling layer (gate material layer 107) on the surface of the second trench 1002.

[0099] In one example of the invention, such as Figure 1H As shown, before performing a second chemical mechanical polishing process on the second fill layer, a polishing protection layer 108 is also formed on the surface of the second fill layer (gate material layer 107).

[0100] A polishing protective layer 108 is formed on the surface of the second filler layer (gate material layer 107). Because there are depressions on the surface of the second filler layer (gate material layer 107), the polishing protective layer is deposited more extensively at the depression locations. Figure 1H As shown. In the second chemical mechanical polishing process, the polishing protection layer 108 above the second filler layer (gate material layer 107) is first removed. During the removal of the polishing protection layer 108, the polishing protection layer 108 located on the flat surface of the second filler layer (gate material layer 107) is removed first. During the further removal of the gate material layer 107, the chemical mechanical polishing rate of the recessed area is slowed down because the recessed area still has the polishing protection layer 108. By balancing the chemical mechanical polishing rates of the recessed area and the non-recessed area, the removal rate of the second filler layer (gate material layer 107) on the entire wafer surface can be adjusted, and the planarization of the second filler layer (gate material layer 107) can be finally achieved.

[0101] For example, in step S6, the second chemical mechanical polishing process includes:

[0102] Perform a third chemical mechanical polishing step to remove the polishing protective layer and partially remove the second filler layer to remove the depressions on the second filler layer;

[0103] A fourth chemical mechanical polishing step is performed to remove the remaining second filler layer at the first height.

[0104] According to one embodiment of the present invention, in the third chemical mechanical polishing step, appropriate polishing parameters (high polishing rate: Large areas of the gate material layer 107 are removed, and the polishing stage is controlled by motor torque endpoint detection (motor torque EPD). Polishing continues until the lowest point of the recess in the gate material layer 107 is reached, and an over-polishing stage is further set to ultimately remove the remaining gate material layer on the semiconductor substrate surface.

[0105] like Figure 1I As shown, after the third chemical mechanical grinding step, a low grinding rate is used. When the residual gate material layer 107 is removed and the grinding reaches the interface between the gate material layer 107 and the gate oxide layer 106, the termination point is obtained by the motor torque EPD curve. Then, the grinding stage time is set to obtain a lower dishing morphology.

[0106] Thus far, the technical solution of the present invention has been exemplarily described. In one embodiment of the present invention, after completing the aforementioned structure, the step of forming an electrical connection structure on the surface of the semiconductor substrate to connect the gate structure is further described, and will not be repeated here. According to the semiconductor device manufacturing method of the present invention, for the step difference formed after filling trenches with different aspect ratios, the distribution of the polishing slurry on the polishing pad is adjusted by adjusting the landing position of the polishing slurry on the polishing pad during the chemical mechanical polishing process, thereby improving the uniformity of the chemical mechanical polishing process, achieving high gloss and high quality film layer quality, and significantly reducing the polishing process cost.

[0107] See Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Figure 2 As shown, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes:

[0108] Step S1: Provide a semiconductor substrate, form a polishing barrier layer on the surface of the semiconductor substrate, form a trench in the semiconductor substrate, the trench includes a first trench located in a first region and a second trench located in a second region, fill the first trench and the second trench with a first filling layer, wherein the top of the first filling layer in the first trench is flush with the surface of the semiconductor substrate, and the top of the first filling layer in the second trench is lower than the surface of the semiconductor substrate;

[0109] Step S2: Perform a deposition process to form an isolation material layer that covers the surface of the semiconductor substrate and fills the remaining depth of the second trench;

[0110] Step S3: Perform a first chemical mechanical polishing process to remove the isolation material layer on the surface of the semiconductor substrate, wherein the first chemical mechanical polishing process includes:

[0111] Perform a first chemical mechanical polishing step to remove a portion of the insulating material layer from the surface of the semiconductor substrate;

[0112] A second chemical mechanical polishing step is performed to remove the remaining insulating material layer above the surface of the polishing barrier layer, wherein the polishing slurry is supplied to the polishing pad at different locations in the first and second chemical mechanical polishing steps.

[0113] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: Step S1: Provide a semiconductor substrate, form a polishing barrier layer on the surface of the semiconductor substrate, form a trench in the semiconductor substrate, the trench includes a first trench located in a first region and a second trench located in a second region, fill the first trench and the second trench with a first filling layer, wherein the top of the first filling layer in the first trench is flush with the surface of the semiconductor substrate, and the top of the first filling layer in the second trench is lower than the surface of the semiconductor substrate; Step S2: Perform a deposition process to form an isolation material layer that covers the surface of the semiconductor substrate and fills the remaining depth of the second trench; Step S3: Perform a first chemical mechanical polishing process to remove the isolation material layer on the surface of the semiconductor substrate, wherein the first chemical mechanical polishing process includes: Perform a first chemical mechanical polishing step to remove a portion of the insulating material layer from the surface of the semiconductor substrate; A second chemical mechanical polishing step is performed to remove the remaining insulating material layer above the surface of the polishing barrier layer. In the first and second chemical mechanical polishing steps, the landing point of the polishing liquid supplied to the polishing pad is different. In the first chemical mechanical polishing step, the distance between the landing point and the center of the polishing pad is a first distance, and in the second chemical mechanical polishing step, the distance between the landing point and the center of the polishing pad is a second distance. The first distance is less than the second distance. In step S2, the isolation material layer in the second region has a recess. In step S3, after the first chemical mechanical polishing step removes part of the isolation material layer on the surface of the semiconductor substrate, the height of the isolation material layer above the polishing barrier layer is 1.2-1.5 times the height of the bottom of the recess from the surface of the semiconductor substrate.

2. The method according to claim 1, characterized in that, In the first chemical mechanical grinding process, deionized water is supplied to the landing point.

3. The method according to claim 2, characterized in that, In the first chemical mechanical polishing step and the second chemical mechanical polishing step, the relative positions of the polishing slurry supply pipe for supplying the polishing slurry and the deionized water supply pipe for supplying the deionized water are different.

4. The method according to claim 3, characterized in that, In the first chemical mechanical polishing step, the polishing slurry supply pipe is located vertically above the deionized water supply pipe.

5. The method according to claim 3, characterized in that, In the first chemical mechanical polishing step, the polishing fluid supply pipe and the deionized water supply pipe are arranged in parallel in the horizontal direction.

6. The method according to claim 1, characterized in that, In the second chemical mechanical polishing step, the endpoint position of the second chemical mechanical polishing step is set by a method of motor torque endpoint detection, wherein the endpoint position is set after the second chemical mechanical polishing step has polished to the interface between the isolation material layer and the polishing barrier layer, so that the second chemical mechanical polishing step is slightly over-polished.

7. The method according to claim 1, characterized in that, Following step S2, the method further includes: Step S4: Remove a portion of the isolation material layer in the second trench, wherein the top of the remaining isolation material layer in the second trench is below the surface of the semiconductor substrate; Step S5: Perform a deposition process to form a second fill layer, which covers the surface of the semiconductor substrate and fills the remaining second trench; Step S6: Perform a second chemical mechanical polishing process to planarize the second filler layer.

8. The method according to claim 7, characterized in that, Prior to step S6, an abrasive protective layer is formed on the surface of the second filler layer.

9. The method according to claim 8, characterized in that, In step S6, the second chemical mechanical polishing process includes: Perform a third chemical mechanical polishing step to remove the polishing protective layer and partially remove the second filler layer to remove the depressions on the second filler layer; Perform a fourth chemical mechanical polishing step to remove the remaining second filler layer.

10. The method according to claim 9, characterized in that, The grinding rate of the third chemimechanical grinding step is greater than the rate of the fourth chemimechanical grinding step.

11. The method according to claim 7, characterized in that, The second filling layer includes a gate material layer, and prior to step S5, a gate oxide layer is formed on the surface of the semiconductor substrate and on the sidewalls of the unfilled portion of the second trench.

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