Semiconductor structure and method of forming the same

Abstract

Embodiments of the present application provide a semiconductor structure and a forming method thereof. An initial substrate is provided, and a surface of the initial substrate includes adjacent well regions and drift regions. A fin region is formed by the well regions and a portion of the drift regions facing the well regions. A platform region is formed by a portion of the drift regions away from the well regions. A portion of the initial substrate is removed in the fin region to form a substrate, a fin, and a platform adjacent to the fin. The initial substrate with a remaining thickness is the substrate. The initial substrate protruding from the substrate in the fin region is the fin. The initial substrate protruding from the substrate in the platform region is the platform. A gate structure is formed across the fin, and the gate structure covers a portion of the drift regions and a portion of the well regions. A source is formed in the well region, and a drain is formed in the drift region. Embodiments of the present application can improve the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Semiconductor devices are electronic devices whose conductivity lies between that of a good conductor and an insulator. They utilize the unique electrical properties of semiconductor materials to perform specific functions, such as generating, controlling, receiving, converting, and amplifying signals, and performing energy conversion. Commonly used semiconductor devices include field-effect transistors (FETs), bipolar transistors (BPTZs), and diodes. Among these, laterally diffused metal-oxide-semiconductor (LDMOS) is particularly widely used in power integrated circuits due to its greater compatibility with complementary metal-oxide-semiconductor (CMOS) logic processes.

[0003] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of transistors is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes the subthreshold leakage phenomenon, also known as the short-channel effect (SCE), more likely to occur.

[0004] Therefore, in order to better adapt to the reduction of feature size, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as LDMOS fin field-effect transistors. In this device structure, the gate structure can control the ultra-thin body (fin) from at least both sides. Compared with planar LDMOS, the gate structure has stronger control over the channel and can effectively suppress short-channel effects; and compared with other devices, it has better compatibility with existing integrated circuit manufacturing.

[0005] However, the electrical performance of semiconductor devices produced by existing technologies still needs to be improved. Summary of the Invention

[0006] The problem addressed by this invention is how to provide a semiconductor structure and a method for forming the same, in order to improve the electrical performance of the device.

[0007] To address the above problems, the present invention provides a method for forming a semiconductor structure, comprising:

[0008] An initial substrate is provided, the surface of which includes adjacent well regions and drift regions, wherein the well regions and a portion of the drift regions facing the well regions are defined as fin regions, and a portion of the drift regions facing away from the well regions is defined as plateau regions.

[0009] A portion of the thickness of an initial substrate is removed from a portion of the fin region to form a substrate, a fin, and a platform adjacent to the fin. The remaining thickness of the initial substrate is used as the substrate, the initial substrate protruding from the substrate in the fin region is used as the fin, and the initial substrate protruding from the substrate in the platform region is used as the platform.

[0010] A gate structure is formed across the fin, the gate structure covering a portion of the drift region and a portion of the well region;

[0011] A source electrode is formed in the well region, and a drain electrode is formed in the drift region.

[0012] Accordingly, the present invention also provides a semiconductor structure, comprising:

[0013] The substrate has a surface comprising adjacent well regions and drift regions, wherein the well regions and a portion of the drift regions facing the well regions constitute fin regions, and a portion of the drift regions facing away from the well regions constitutes plateau regions.

[0014] A fin protruding from the substrate in the fin region, and a platform protruding from the substrate in the platform region, wherein the fin and the platform are adjacent to each other;

[0015] A gate structure spanning the fin, the gate structure covering a portion of the drift region and a portion of the well region;

[0016] The source electrode is located within the well region, and the drain electrode is located within the drift region.

[0017] Compared with the prior art, in the embodiments of the present invention, when forming the fin, a platform adjacent to the fin is also formed, and a drift region including at least the platform is formed. This allows the voltage to be divided based on the platform of the drift region when the drain is connected to high voltage in the embodiments of the present invention, thereby avoiding device breakdown and improving device performance. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a method for forming a semiconductor structure.

[0019] Figures 2 to 18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure provided by the present invention;

[0020] Figure 19This is a schematic diagram of the semiconductor structure provided by the present invention. Detailed Implementation

[0021] The devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0022] refer to Figure 1 The diagram illustrates a semiconductor structure for forming an LDMOS device, including a source 180, a drain 190, and a gate 170. The gate spans a portion of a well region 10A and a drift region 10B. The source 180 is formed in the well region 10A, and the drain 190 is formed in the drift region 10B. The drain 190 and the source 180 are simultaneously formed on a fin 130. The voltage applied to the drain should not be too high, otherwise it may cause device breakdown and affect the device's performance.

[0023] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: providing an initial substrate, the surface of which includes adjacent well regions and drift regions, wherein the well regions and a portion of the drift regions facing the well regions are defined as fin regions, and a portion of the drift regions facing away from the well regions are defined as plateau regions; removing a portion of the thickness of the initial substrate within the fin regions to form a substrate, fins, and a plateau adjacent to the fins, wherein the remaining thickness of the initial substrate is defined as the substrate, the portion of the initial substrate protruding from the substrate within the fin regions is defined as the fins, and the portion of the initial substrate protruding from the substrate within the plateau regions is defined as the plateau; forming a gate structure spanning the fins, the gate structure covering a portion of the drift regions and a portion of the well regions; forming a source electrode within the well regions and a drain electrode within the drift regions.

[0024] As can be seen, in the embodiments of the present invention, when forming the fin, a platform adjacent to the fin is also formed, and a drift region including at least the platform is formed. This enables voltage division based on the platform of the drift region when the drain is connected to high voltage in the embodiments of the present invention, thereby avoiding device breakdown and improving device performance.

[0025] It should be further explained that the reference Figure 1 In the structure described above, when the drain voltage is applied, the electric field at the tip of the fin with the drift region 10B is very high, which easily causes the HCI (Hot Carrier Injection) effect, thus affecting the device performance. However, in the semiconductor structure provided by the embodiments of the present invention, the drift region formed within the platform does not have the tip of the fin, thus it is less prone to the HCI effect, further improving the device performance.

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] refer to Figures 2-18 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method provided by the present invention.

[0028] refer to Figures 2-3 ,in, Figure 3 for Figure 2 A cross-sectional view obtained along the AA' direction. Specifically, an initial substrate 200 is provided, the surface of which includes adjacent well regions 20A and drift regions 20B, wherein the portion of the well region 20A and the portion of the drift region 20B facing the well region is designated as fin region I, and the portion of the drift region 20B facing away from the well region 20A is designated as plateau region II.

[0029] The initial substrate is used to provide a process basis for the subsequent formation of the substrate, fins, and platforms adjacent to the fins. The initial substrate is also used to provide a process basis for the subsequent formation of semiconductor structures.

[0030] In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. The initial substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the initial substrate may be suitable for process requirements or easy to integrate.

[0031] The initial substrate surface includes adjacent well regions 20A and drift regions 20B. Optionally, the well regions 20A and drift regions 20B are connected. The well region 20A can be used as the well region of an LDMOS device, and the drift region 20B can be used as the drift region of an LDMOS device. In subsequent processes, corresponding device structures are formed on the well regions 20A and drift regions 20B, thereby forming the corresponding LDMOS device.

[0032] The well region 20A and drift region 20B are doped with dopants of different conductivity types. For example, when N-type ions are doped in the well region, P-type ions are doped in the drift region; when P-type ions are doped in the well region, N-type ions are doped in the drift region. The different conductivity types of dopants can be related to the conductivity type of the final device to be formed, which will not be elaborated here.

[0033] The well region 20A and drift region 20B can be formed by epitaxial processes. For example, during epitaxial growth, corresponding ions are doped to form a layer structure of the corresponding conductivity type; or, the well region 20A and drift region 20B can be formed by ion implantation of corresponding ions in the corresponding regions of the initial substrate. Wherein, when the doping ion is an N-type ion, the N-type ion can be a P ion, an As ion, or an Sb ion; when the doping ion is a P-type ion, the P-type ion can be a B ion, a Ga ion, or an In ion.

[0034] Fin region I is the region used to form the fin in subsequent processes, and platform region II is the region used to form the platform in subsequent processes. It should be noted that, since the gate structure is formed on the fin in subsequent processes, and the gate structure covers part of the well region 20A and part of the drift region 20B, fin region I also includes a portion of the drift region 20B facing the well region 20A. Correspondingly, platform region II is defined as the remaining region of the drift region 20B, that is, the portion of the drift region 20B facing away from the well region 20A.

[0035] Optionally, the initial substrate may further include a planarization layer 210, a hard mask material layer 220, and a hard mask cap layer 221.

[0036] The initial substrate may further include a planarization layer 210, which is used to alleviate surface unevenness of the initial substrate and provide a corresponding process foundation for subsequent processes. The hard mask material layer 220 is used to form a patterned hard mask layer after patterning, which serves as a mask for forming fins in subsequent steps. The hard mask cap layer 221 is used to accurately transfer the pattern to the hard mask layer. The planarization layer 210, hard mask material layer 220, and hard mask cap layer 221 can be made of one or more of silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, silicon carbonitride oxynitride, silicon oxynitride, boron nitride, and boron carbonitride, and adjacent layers can be made of different materials. In this embodiment, the planarization layer 210 can be made of silicon oxide, the hard mask material layer 220 can be made of silicon nitride, and the hard mask cap layer 221 can be made of silicon oxide.

[0037] It should be noted that the thermal expansion coefficients of the hard mask material layer and the fin material differ significantly. If the hard mask material layer is formed directly on the initial substrate, it is prone to cracking or even falling off, thus failing to function as a mask layer. Therefore, a planarization layer is formed between the hard mask material layer and the initial substrate. This planarization layer not only alleviates the problem of unevenness on the surface of the initial substrate but also acts as a buffer for the hard mask material layer.

[0038] refer to Figures 4-7 , Figure 7 for Figure 6 A structural diagram along the BB' direction. Specifically, a portion of the thickness of the initial substrate is removed from a certain area within the fin region to form a substrate 201, a fin 202, and a platform adjacent to the fin. The remaining thickness of the initial substrate serves as the substrate, the initial substrate protruding from the substrate within the fin region serves as the fin, and the initial substrate protruding from the substrate within the platform region serves as the platform.

[0039] The fins are used to subsequently provide the channels for fin field-effect transistors. In this embodiment, the fins and the substrate are obtained by etching the same semiconductor material layer. The fins and the substrate are made of the same material; in this embodiment, the material of the fins is silicon.

[0040] The platform provides a process foundation for subsequent processes. In this embodiment, the initial substrate protruding from the substrate within the platform region is used as the platform. In this embodiment, the platform, the fins, and the substrate are obtained by etching the same semiconductor material layer. The platform, fins, and substrate are made of the same material; in this embodiment, the platform is made of silicon.

[0041] Specifically, the step of removing a portion of the initial substrate thickness within the fin region may include:

[0042] refer to Figure 4 A patterned first mask layer 230 is formed on the initial substrate, the first mask layer 230 exposing a portion of the initial substrate of the fin region and the platform region.

[0043] Optionally, the first mask layer is used to expose a portion of the initial substrate of the fin region and platform region after patterning. The first mask layer 230 can be formed using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) techniques, thereby meeting the requirements for accuracy and stability of pattern transfer at a smaller critical size.

[0044] In this embodiment, the material of the first mask layer can be silicon nitride. Silicon nitride has high hardness and density, which is beneficial for improving the masking effect of the first mask layer in subsequent patterning. Furthermore, silicon nitride is a commonly used dielectric material in semiconductor processes and has high process compatibility. In other embodiments, the material of the first mask layer can also be amorphous carbon. In other embodiments, the material of the first mask layer can also be one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN, and SiON.

[0045] In this embodiment of the invention, in order to ensure the uniformity of the fin size, multiple pseudo-fins parallel to the fin are formed at the same time as the fin. Correspondingly, the first mask layer is used to form both the fin and the pseudo-fin (not shown in the figure).

[0046] refer to Figure 5 A patterned second mask layer 240 is formed on the first mask layer, the second mask layer covering the first mask layer of the platform region II and exposing the first mask layer of the fin region I;

[0047] Optionally, the second mask layer is used to cover the first mask layer of the platform area, thereby exposing the first mask layer of the fin area so that subsequent processes can perform corresponding treatments on the fin area.

[0048] In this embodiment, the second mask layer is a photolithography mask layer. The material of the corresponding photolithography mask layer can be photoresist, which can be formed by spin coating and curing processes. The exposure and development can be achieved using appropriate process parameters. The photoresist can be positive or negative; this invention does not impose a specific limitation.

[0049] refer to Figures 6-7 , Figure 7 for Figure 6 A cross-sectional view along the BB' direction shows that, using the first mask layer and the second mask layer 240 as masks, a portion of the initial substrate thickness is etched away to form a substrate 201 and a fin 202 protruding from the substrate in the fin region.

[0050] Accordingly, in the step of etching away part of the initial substrate thickness, the initial substrate is patterned using the first mask layer and the second mask layer as masks, so that the initial substrate with the remaining thickness is used as the substrate, the initial substrate protruding from the substrate in the fin region is used as the fin, and the initial substrate protruding from the substrate in the platform region is used as the platform.

[0051] Specifically, during the etching process, the hard mask cap layer 221 can be etched first using the first mask layer and the second mask layer 240 as masks to transfer the fin pattern onto the hard mask cap layer 221. Then, using the hard mask cap layer 221 as a mask, the hard mask material layer 220 is etched to form a patterned hard mask layer 222. Further, using the hard mask layer 222 as a mask, the planarization layer 210 and the initial substrate are etched to form the fin 202. It should be noted that in this embodiment, since the hard mask layer 222 and the first mask layer 230 are made of the same material, while patterning the hard mask material layer 220, the first mask layer 230 exposed in the fin region is removed or partially removed. The figure illustrates this by example of removing the first mask layer 230 exposed in the fin region.

[0052] In this embodiment, when etching the initial substrate, the initial substrate can be etched by wet etching, dry etching, or a combination of wet etching and dry etching, thereby forming the corresponding structure.

[0053] Optionally, the initial substrate can be etched by wet etching. Accordingly, the etching solution for wet etching can be an acid mixture, such as hydrochloric acid, phosphoric acid, nitric acid, etc., mixed in a certain proportion.

[0054] It should be noted that, based on the embodiments of the present invention, the first mask layer is also used to form a pseudo fin. Accordingly, in the etching process of this step, while forming the fin, a pseudo fin parallel to the fin is also formed.

[0055] refer to Figures 8-10 This is a schematic diagram of the structure after etching away a portion of the initial substrate thickness in the step of removing a portion of the initial substrate thickness in the fin region.

[0056] In this embodiment of the invention, after etching away a portion of the initial substrate thickness, it is necessary to further remove the remaining first and second mask layers. In particular, the first and second mask layers are still retained in the platform region. Specifically, the steps for removing the first and second mask layers may include:

[0057] First, remove the second mask layer;

[0058] In this embodiment of the invention, the second mask layer is a photoresist layer, and correspondingly, the second mask layer can be removed by a stripping process.

[0059] The second mask layer covers the first mask layer of the platform area, and removing the second mask layer exposes the first mask layer of the platform area.

[0060] refer to Figure 8 A sacrificial layer 250 is formed on the side of the substrate having the fin, and the sacrificial layer 250 covers the substrate 201, the fin 202 and the first mask layer.

[0061] The sacrificial layer 250 is used to fill the spaces between the fins 202 to protect the fins 202 and prevent them from being etched or tilted or deformed by stress during subsequent processes.

[0062] To reduce the impact of the sacrificial layer on subsequent processes, in this embodiment, the sacrificial layer 250 is made of a material that is easy to remove.

[0063] Specifically, the material of the sacrificial layer 250 can be a spin-on carbon (SOC) layer or an organic dielectric layer (ODL). In this embodiment, the material of the sacrificial layer is a spin-on carbon layer.

[0064] Spin-coated carbon layers are readily available materials, which helps reduce the process cost of forming the sacrificial layer. Moreover, spin-coated carbon layers are easy to remove, which helps reduce the difficulty of subsequent sacrificial layer removal operations, simplifies the process flow, improves process manufacturing efficiency, and also helps reduce the impact of the sacrificial layer on subsequent process steps and semiconductor structure.

[0065] In this embodiment, the step of forming the sacrificial layer 250 may include: spin-coating the spin-coated carbon layer on the side of the substrate having the fin, the spin-coated carbon layer covering the substrate, the fin and the first mask layer; and curing the spin-coated carbon layer.

[0066] It should be noted that, in the step of forming the sacrificial layer, the thickness of the sacrificial layer on the substrate should not be too small or too large. If the thickness of the sacrificial layer is too small, it is difficult for the sacrificial material layer to fill the gap between adjacent fins, which will adversely affect subsequent processes such as removing the first mask layer and forming the isolation layer. Moreover, if the thickness of the sacrificial material layer is too small, it may not completely cover the fins and the substrate, reducing the coverage between the fins and the substrate. If the thickness of the sacrificial layer is too large, it will increase the difficulty of subsequent removal of the sacrificial layer. Therefore, in this embodiment, the thickness of the sacrificial layer is greater than the height of the fin but less than twice the height of the fin.

[0067] Next, a portion of the sacrificial layer is removed until part of the first mask layer is exposed.

[0068] The process of removing the sacrificial layer can employ a dry etching process with anisotropic properties to achieve precise control over the etching thickness. In this embodiment of the invention, the dry etching process is a plasma etching process, wherein the etching gas is one or more of H2, CO2, CH4, and O2.

[0069] In other alternative implementations, wet etching can also be used, as well as a process that combines wet and dry etching; no restrictions are imposed here.

[0070] Next, the first mask layer is etched away.

[0071] Since the first mask layer has been exposed by the sacrificial layer, the first mask layer can be removed by dry etching, wet etching, or a combination of dry and wet etching processes.

[0072] Since the sacrificial layer has been filled between the fins, the embodiments of the present invention will not damage the fins during the etching process of removing the first mask layer.

[0073] refer to Figure 9 After etching away the first mask layer, the sacrificial layer is removed.

[0074] Accordingly, the process for removing the sacrificial layer can refer to the aforementioned steps. Optionally, the sacrificial layer can be removed using dry etching, wet etching, or a combination of dry and wet etching.

[0075] In this embodiment, reference Figure 10 The fin region may include an isolation region 20C, which is located on the side of the fin region opposite to the platform region II. The isolation region 20C is used to form an isolation structure, thereby achieving isolation between devices on the substrate.

[0076] refer to Figure 11 Remove the fins within the isolation zone 20C to form an isolation trench N.

[0077] The isolation trench N is used to provide process space for the subsequent formation of the isolation structure.

[0078] Specifically, at least a portion of the fin height within the isolation zone can be removed using dry etching, wet etching, or a combination of both.

[0079] In embodiments of the present invention, when a pseudo-fin is also formed, the pseudo-fin can be removed simultaneously during the step of removing at least a portion of the height of the fin within the isolation zone, thereby simplifying the process and reducing process costs.

[0080] It should be noted that in the steps of forming the isolation trench N and removing the false fin, the hard mask cap layer and hard mask layer on the fin can be used to achieve the corresponding patterning process, thereby exposing the area of ​​the fin that needs to be removed. It should also be noted that after forming the isolation trench N and removing the false fin, the remaining hard mask cap layer and hard mask layer are removed, and the remaining planarization layer (such as...) is further removed. Figure 11 (As shown).

[0081] Next, refer to Figures 12-14 , Figure 13 for Figure 12 Structural diagram along the CC' direction, Figure 14 for Figure 12 A structural diagram along the DD' direction. Specifically, an isolation material layer covering the substrate is formed within the fin region, wherein the isolation material layer within the isolation region 20C serves as the isolation structure 260, and the isolation material layer between the fins serves as the isolation layer 261.

[0082] The isolation layer 261 is used to isolate the substrate between at least adjacent fins, and the isolation structure 260 is used to isolate adjacent device structures.

[0083] In this embodiment, the insulating material layer is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps reduce the difficulty and cost of forming the insulating material layer. Furthermore, silicon oxide has a low dielectric constant, which also helps improve the insulating effect of the insulating layer. In other embodiments, the insulating layer can also be made of other insulating materials such as silicon nitride and silicon oxynitride.

[0084] In this embodiment, a flowable chemical vapor deposition (FCVD) process is used to form the isolation material layer. The FCVD process has excellent filling capabilities and is suitable for filling openings with high aspect ratios, which helps reduce the probability of voids and other defects forming within the isolation material layer, thereby improving the quality of the isolation material layer.

[0085] Next, refer to Figures 15-16 , Figure 16 for Figure 15 A structural diagram along the EE' direction forms a gate structure spanning the fin.

[0086] The gate structure 270 includes a gate dielectric layer 271, a gate 272, and a sidewall 273. Specifically, the steps for forming the gate structure may include:

[0087] A conformal cover is formed over an initial substrate having a gate dielectric material layer on one side of the fin; a gate 272 is formed on the gate dielectric material layer that spans the fin, the gate covering part of the sidewall and part of the top of the fin; sidewalls 273 are formed on both sides of the gate; using the gate and sidewalls as a mask, the exposed gate dielectric material layer is removed, and the remaining gate dielectric material layer is used as the gate dielectric layer 271.

[0088] To ensure the uniformity of gate size, embodiments of the present invention further form dummy gates simultaneously with the gate, and remove the dummy gates after forming the dummy gate structure. Specifically, the step of forming a gate spanning the fin on the gate dielectric layer may include: forming a gate material layer covering the side of the substrate having the fin; patterning the gate material layer to form a gate and a plurality of dummy gates parallel to the gate; and removing the dummy gates and the sidewalls on both sides of the dummy gate after forming sidewalls on both sides of the gate.

[0089] It should be noted that the gate dielectric material layer is used to subsequently form the gate dielectric layer. The material of the gate dielectric layer is a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0090] Optionally, the gate serves as an electrode for electrical connection with an external circuit. In this embodiment, the gate material can be a magnesium-tungsten alloy; in other embodiments, the gate structure material can also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0091] Optionally, the gate material layer is used to subsequently form the gate. Therefore, the selection of the gate material can be found in the previous section on the selection of the gate material layer, and will not be repeated here.

[0092] During the formation of the gate, some dummy gates are also formed. These dummy gates are used to improve the size consistency and morphological uniformity of the gate. They are removed in subsequent steps. Both the dummy gates and the gate are obtained by imaged gate material layers, and the dummy gates and the gate are made of the same material.

[0093] The sidewall is used to support the gate, and the sidewall has a stable support. The sidewall is used to protect the gate from tilting or bending, so that the formed gate structure is not prone to tilting or bending.

[0094] In this embodiment, the sidewall is made of silicon nitride. In other embodiments, the sidewall may also be made of silicon oxynitride.

[0095] The dummy gate is formed simultaneously with the gate. In this embodiment of the invention, after sidewalls are formed on both sides of the gate, the dummy gate in the gate needs to be removed.

[0096] In this embodiment, a gate dielectric material layer is first formed, then a gate is formed on the fin, and sidewalls are formed on both sides of the gate. Then, the exposed part of the gate dielectric material layer is removed, and the remaining gate dielectric material layer is used as the gate dielectric layer.

[0097] refer to Figure 17 After forming a gate structure spanning the fin, a barrier layer 280 is formed on the side of the gate structure facing the platform, and the barrier layer 280 covers at least a portion of the drift region.

[0098] The barrier layer can be a metallized barrier layer, which is used to prevent doped ions in the drift region from diffusing outward.

[0099] It is understandable that when the drift area is a fin, a barrier layer needs to be formed in the groove between the fins. Correspondingly, the formation process of the barrier layer is not easy to control, and the morphology of the formed barrier layer is not good. However, in this embodiment, since most of the drift area is a platform, the process of forming the barrier layer in this embodiment is simpler, and the morphology of the formed barrier layer is good.

[0100] Optionally, in this embodiment, the material of the barrier layer may include amorphous silicon. In other embodiments, the material of the barrier layer may also include silicon nitride or silicon titanate.

[0101] refer to Figure 18 A source electrode 290 is formed in the well region, and a drain electrode 291 is formed in the drift region.

[0102] It can be explained in detail that when the semiconductor device is an LDMOS transistor, the LDMOS transistor is a high-voltage device. The parasitic transistor formed by the drain, substrate and source of the LDMOS transistor can discharge electrostatic current. When the drain of the embodiment of the present invention is connected to high voltage, voltage division can be performed based on the aforementioned platform to avoid device breakdown.

[0103] As can be seen, in the embodiments of the present invention, when forming the fin, a platform adjacent to the fin is also formed, and a drift region including at least the platform is formed. This enables voltage division based on the platform of the drift region when the drain is connected to high voltage in the embodiments of the present invention, thereby avoiding device breakdown and improving device performance.

[0104] Accordingly, embodiments of the present invention also propose a semiconductor structure, referring to... Figure 19 The diagram shows a cross-sectional view of the semiconductor structure in this embodiment.

[0105] The semiconductor structure includes: a substrate, the surface of which includes adjacent well regions 30A and drift regions 30B, the well regions 30A and the portion of the drift regions 30B facing the well regions 30A are fin regions, and the portion of the drift regions 30B facing away from the well regions is a plateau region;

[0106] A fin protruding from the substrate in the fin region, and a platform protruding from the substrate in the platform region, wherein the fin and the platform are adjacent to each other;

[0107] A gate structure 370 spans the fin, the gate structure 370 covering a portion of the drift region 30B and a portion of the well region 30A;

[0108] The source 390 is located in the well region 30A, and the drain 391 is located in the drift region 30B.

[0109] In this embodiment, the substrate material is silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium phosphate, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. The initial substrate material may be a material suitable for process requirements or easy to integrate.

[0110] Optionally, the initial substrate may further include a planarization layer, a hard mask material layer, and a hard mask cap layer. The planarization layer alleviates surface unevenness of the initial substrate and provides a corresponding process basis for subsequent processes. The hard mask material layer is used to form a patterned hard mask layer after patterning, which serves as a mask for forming fins in subsequent steps. The hard mask cap layer is used to accurately transfer the pattern to the hard mask layer.

[0111] Furthermore, the fins are used to subsequently provide the channels for fin field-effect transistors. The fins and the substrate are obtained by etching the same semiconductor material layer. The fins and the substrate are made of the same material; in this embodiment, the material of the fins is silicon.

[0112] The platform is used to provide the basis for subsequent processes. In this embodiment of the invention, the initial substrate protruding from the substrate within the platform region is used as the platform. The platform, the fins, and the substrate are obtained by etching the same semiconductor material layer. The platform, the fins, and the substrate are made of the same material; in this embodiment, the platform is made of silicon.

[0113] Optionally, the fin region includes a device region and an isolation region. The device region is adjacent to the platform region, and the isolation region is located on the side of the device region away from the platform region. An isolation groove with its bottom lower than the top of the fin is provided in the isolation region. An isolation structure 360 ​​is provided in the isolation groove. An isolation layer (not shown in the figure) is provided in the device region, exposing a portion of the height of the fin.

[0114] The gate structure is adjacent to the platform, or the distance between the gate structure and the platform is less than or equal to 10-200 nm. The gate structure includes a gate dielectric layer, a gate, and sidewalls. The sidewalls are located on both sides of the gate, and the gate dielectric layer is located between the fin and the gate. The gate dielectric layer is made of a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO2. In other embodiments, the gate dielectric layer material may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0115] Furthermore, the gate serves as an electrode for electrical connection with an external circuit. In this embodiment, the gate material can be a magnesium-tungsten alloy; in other embodiments, the gate structure material can also be Al, Cu, Ag, Au, Pt, Ni, or Ti, etc.

[0116] The sidewall is used to support the gate, and the sidewall has a stable support. The sidewall is used to protect the gate from tilting or bending, so that the formed gate structure is not prone to tilting or bending.

[0117] In this embodiment, the sidewall is made of silicon nitride. In other embodiments, the sidewall may also be made of silicon oxynitride.

[0118] In this embodiment, a barrier layer 380 is located on the side of the gate structure facing the platform, and the barrier layer 380 covers at least a portion of the drift region.

[0119] The barrier layer can be a metallized barrier layer, which is used to prevent doped ions in the drift region from diffusing outward.

[0120] Optionally, in this embodiment, the material of the barrier layer may include amorphous silicon. In other embodiments, the material of the barrier layer may also include silicon nitride or silicon titanate.

[0121] As can be seen, in this embodiment of the invention, a platform adjacent to the fin is also provided on one side of the fin, and a drift region including at least the platform is formed. This allows the voltage to be divided based on the platform of the drift region when the drain is connected to high voltage in this embodiment of the invention, thereby avoiding device breakdown and improving device performance.

[0122] The semiconductor structure can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments; they will not be repeated here.

[0123] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial substrate is provided, the surface of which includes adjacent well regions and drift regions, wherein the well regions and a portion of the drift regions facing the well regions are defined as fin regions, and a portion of the drift regions facing away from the well regions is defined as plateau regions. A portion of the thickness of an initial substrate is removed from a region within the fin area to form a substrate, a fin, and a platform adjacent to the fin. The remaining thickness of the initial substrate serves as the substrate, the initial substrate protruding from the substrate within the fin area serves as the fin, and the initial substrate protruding from the substrate within the platform area serves as the platform. The platform, the fin, and the substrate are obtained by etching the same semiconductor material layer. The platform is used for voltage division. A gate structure is formed across the fin, the gate structure covering a portion of the drift region and a portion of the well region; the gate structure is adjacent to the platform, or the distance between the gate structure and the platform is less than or equal to 10nm~200nm; A barrier layer is formed on the side of the gate structure facing the platform, and the barrier layer covers at least a portion of the drift region; the barrier layer is a metallized barrier layer, and the barrier layer is used to prevent doped ions in the drift region from diffusing outward; A source electrode is formed in the well region, and a drain electrode is formed in the drift region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The initial substrate in which a portion of the thickness is removed from a portion of the fin region includes: A patterned first mask layer is formed on the initial substrate, the first mask layer exposing a portion of the initial substrate of the fin region and the platform region; A patterned second mask layer is formed on the first mask layer, the second mask layer covering the first mask layer of the platform region and exposing the first mask layer of the fin region; Using the first mask layer and the second mask layer as masks, an initial substrate with a portion of its thickness is etched away to form a substrate and a fin protruding from the substrate within the fin region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of removing a portion of the initial substrate thickness within the fin region, after etching away the portion of the initial substrate thickness, the method further includes: Remove the second mask layer; A sacrificial layer is formed on the side of the substrate having the fin, the sacrificial layer covering the substrate, the fin and the first mask layer; Remove a portion of the sacrificial layer until part of the first mask layer is exposed; The first mask layer is removed by etching. After etching away the first mask layer, the sacrificial layer is removed.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The sacrificial layer is a spin-coated carbon layer or an organic dielectric layer.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The fin region includes an isolation region located on the side of the fin region opposite to the platform region. After removing a portion of the initial substrate thickness within the fin region and before forming a gate structure spanning the fin, the fin region further includes: Remove the fins within the isolation zone to form an isolation trench; An isolation material layer covering the substrate is formed within the fin region, wherein the isolation material layer within the isolation region serves as an isolation structure, and the isolation material layer between the fins serves as an isolation layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that: In the step of forming the fin, a plurality of pseudo-fins parallel to the fin are also formed; In the step of removing at least a portion of the height of the fins within the isolation zone, the pseudo-fins are also removed.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure includes a gate dielectric layer, a gate, and sidewalls, and the formation of the gate structure across the fin includes: A gate dielectric material layer is formed to conformally cover the initial substrate having one side of the fin. A gate is formed across the fin on the gate dielectric material layer, the gate covering part of the sidewall and part of the top of the fin; Sidewalls are formed on both sides of the gate; Using the gate and sidewalls as a mask, the exposed gate dielectric material layer is removed, and the remaining gate dielectric material layer is used as the gate dielectric layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming a gate across the fin on the gate dielectric layer includes: A gate material layer is formed covering the side of the substrate having the fin; The gate material layer is patterned to form a gate and a plurality of dummy gates parallel to the gate; After forming sidewalls on both sides of the gate, the dummy gate and the sidewalls on both sides of the dummy gate are removed.

9. A semiconductor structure, characterized in that, include: The substrate has a surface comprising adjacent well regions and drift regions, wherein the well regions and a portion of the drift regions facing the well regions constitute fin regions, and a portion of the drift regions facing away from the well regions constitutes plateau regions. A fin protrudes from the substrate in the fin region, and a platform protrudes from the substrate in the platform region; the fin and the platform are adjacent to each other; the platform, the fin, and the substrate are obtained by etching the same semiconductor material layer; the platform is used for voltage division. A gate structure spanning the fin, the gate structure covering a portion of the drift region and a portion of the well region; the gate structure is adjacent to the platform, or the distance between the gate structure and the platform is less than or equal to 10~200nm; The source electrode is located within the well region, and the drain electrode is located within the drift region; It also includes a barrier layer located on the side of the gate structure facing the platform, and the barrier layer covers at least a portion of the drift region.

10. The semiconductor structure as described in claim 9, characterized in that, Also includes: The fin region includes a device region and an isolation region. The device region is adjacent to the platform region. The isolation region is located on the side of the device region away from the platform region. An isolation groove with its bottom lower than the top of the fin is provided in the isolation region. An isolation structure is provided in the isolation groove. An isolation layer with a portion of the height of the fin is provided in the device region.

11. The semiconductor structure as described in claim 9, characterized in that, Also includes: The gate structure includes a gate dielectric layer, a gate, and sidewalls, with the sidewalls located on both sides of the gate and the gate dielectric layer located between the fin and the gate.

Images