A method for fabricating a vertical Schottky diode with ultra-small size

Abstract

A method for fabricating a vertical Schottky diode with ultra-small size, comprising: mechanically peeling off an organic adhesive layer including a bottom electrode from a sacrificial substrate and inverting it to form the bottom electrode; transferring a thin two-dimensional semiconductor material with no dangling bonds and atomically flat onto the bottom electrode; mechanically peeling off an organic adhesive layer including a top electrode from the sacrificial substrate and transferring and laminating it onto the thin two-dimensional semiconductor material with no dangling bonds and atomically flat, releasing the organic flexible adhesive layer and the top electrode, wherein the work functions of the top electrode and the bottom electrode are different, and an ohmic contact and a Schottky contact are respectively formed with the thin two-dimensional semiconductor material. The present invention miniaturizes the size limit of the vertical Schottky diode device to the atomic thickness, providing an important way for realizing integrated devices and circuits with large current density, low power consumption and high-frequency switching speed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor nanotechnology, and more particularly to the field of device size reduction methods. Background Art

[0002] Schottky diodes are fundamental components of modern electronics and optoelectronics. Schottky diodes have majority carrier transport and excellent rectifying properties, and have been widely used in logic circuits, high-frequency switching devices, and optical detection and light-emitting devices. Structurally, traditional Schottky diodes have a vertical three-layer sandwich structure. Two electrodes contact on both sides of the semiconductor, where one electrode forms an ohmic contact and the other electrode forms a Schottky barrier contact with the semiconductor. In this structure, the diode length (L) can be defined by the thickness of the semiconductor layer. From a performance perspective, reducing the length of the Schottky diode helps to improve its speed and power consumption by reducing redundant series resistance, shortening the carrier transport distance, and increasing the drive current density. At the same time, reducing the diode length can also increase the device integration density in the vertical direction, which is important for future three-dimensional (3D) integrated devices and circuits.

[0003] For this reason, a great deal of effort has been expended by numerous scholars to reduce the semiconductor thickness by scaling down the length of Schottky diodes. Early attempts involved using thin epitaxial layers (such as Si or III-V compounds) as the intermediate semiconductor placed on highly doped semiconductors (acting as metal electrodes) to reduce the diode length. However, reducing the thickness of the epitaxial layer requires strict control of the growth conditions, which often introduces defects, strain, and surface roughness, leading to a decline in the performance of the epitaxial layer and even failure. To overcome the above problems, two-dimensional (2D) materials have been used as the semiconductors for constructing ultra-thin Schottky diodes. Due to the atomic-thin bulk thickness and the surface without dangling bonds, the length of 2D Schottky diodes can ideally be reduced to the atomic level thickness. However, due to the fine two-dimensional lattice, the 2D diode length depends not only on its thickness but is more restricted by the non-ideal metal-2D interface, where the interface basically determines the performance of the entire device. For example, traditional bottom metals typically exhibit isolated islands or percolation networks during the initial deposition process, resulting in a surface roughness of approximately 1 to 3 nm. Therefore, placing the two-dimensional semiconductor material on such a rough electrode cannot achieve close contact and can only form spotty and non-uniform contacts, leading to local strain as well as random band structures and random electron transport behaviors. On the other hand, the traditional top metal electrodes of 2D vertical Schottky diodes are fabricated through high-energy deposition processes (such as chemical vapor deposition, thermal / electron beam evaporation, sputtering), which usually involve the bombardment of high-energy hot metal atoms / clusters, resulting in the diffusion of the metal into the 2D material channel and the formation of significant interface damage. Such a highly disordered interface will result in leakage current paths appearing below the contact region, which will become increasingly obvious as the diode length is shortened (the thickness of the 2D material is reduced), ultimately causing the electrodes between the diodes to short-circuit and leading to device failure. Therefore, the thinnest vertical 2D Schottky diode realized in the prior art (Nat. Commun. 2018, 9, 5371) using WSe2 as the channel material is 8.5 nm. When the thickness of the WSe2 material is less than 8.5 nm, the device loses the diode rectification effect. Therefore, improving the quality of the interface formed by the contact between the two-dimensional material and the metal is the key to miniaturizing the diode size.

[0004] To improve the quality of the interface between the metal and the two-dimensional material, two-dimensional metals (such as graphene) have been used to replace traditional metal electrodes in the prior art. However, the actual size of graphene diodes is limited by the lateral depletion length of graphene and the lithography accuracy between the two contact metal electrodes (exceeding 10 nm), resulting in large-sized graphene diodes. Therefore, exploring the length limit of vertical Schottky diodes remains a challenge, which restricts the understanding of fundamental semiconductor physics and the realization of ultra-miniaturized and high-integration-density vertical device circuits. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to overcome the above-mentioned defects existing in the prior art and provide a method for preparing a vertical Schottky diode with ultra-small size.

[0006] The technical solution adopted by the present invention is as follows:

[0007] A method for preparing a vertical Schottky diode with ultra-small size, comprising:

[0008] (1) Preparing an inverted bottom electrode:

[0009] Evaporating a patterned metal electrode 1 on an atomically flat sacrificial substrate and then performing a functionalization treatment;

[0010] Spin-coating an organic flexible adhesive layer on the functionalized sacrificial substrate and drying it, mechanically peeling off the organic flexible adhesive layer wrapping the metal electrode 1 and placing it upside down on a new substrate, so that the flat surface of the metal electrode 1 faces upward, and then performing an annealing treatment to form a bottom electrode.

[0011] (2) Transferring a thin two-dimensional semiconductor material without dangling bonds and with atomic-level flatness onto the bottom electrode:

[0012] Mechanically peeling off a thin two-dimensional semiconductor material without dangling bonds and with atomic-level flatness from a bulk two-dimensional semiconductor material by using an organic flexible adhesion layer, and aligning and bonding the thin two-dimensional semiconductor material without dangling bonds and with atomic-level flatness with the bottom electrode through an alignment component of a transfer platform.

[0013] (3) Preparing a top electrode:

[0014] Evaporating a patterned metal electrode 2 on an atomically flat sacrificial substrate and then performing a functionalization treatment; spin-coating an organic flexible adhesive layer on the functionalized sacrificial substrate and drying it, mechanically peeling off the organic flexible adhesive layer wrapping the metal electrode 2, transferring and laminating it onto the thin two-dimensional semiconductor material without dangling bonds and with atomic-level flatness through an alignment component of a transfer platform, and releasing the organic flexible adhesive layer and the metal electrode 2 to complete the preparation of the top electrode.

[0015] The work functions of the metal electrode 1 and the metal electrode 2 are different, and form an ohmic contact and a Schottky contact with the thin two-dimensional semiconductor material respectively.

[0016] Furthermore, the metal electrode 1 is a metal with a high work function, and the metal electrode 2 is a metal with a low work function; or the metal electrode 1 is a metal with a low work function, and the metal electrode 2 is a metal with a high work function.

[0017] Furthermore, the metal with a high work function is platinum, palladium or gold; the metal with a low work function is silver or copper.

[0018] Further, in steps (1) and (3), hexamethyldisilazane (HMDS) is used to functionalize the entire sacrificial substrate, so that the subsequently spin-coated organic flexible adhesive layer has a weak adhesion to the sacrificial substrate and can be easily mechanically peeled off from the sacrificial substrate.

[0019] Further, the organic flexible adhesive layer is a polymethyl methacrylate (PMMA) layer, and the organic flexible adhesion layer is a polydimethylsiloxane (PDMS) layer. Since the adhesion between PDMS and the thin-layer two-dimensional semiconductor material is less than the adhesion between the thin-layer two-dimensional semiconductor material and the bottom electrode, after lamination in step (2), the thin-layer two-dimensional semiconductor material remains on the bottom electrode, and the PDMS layer detaches from the thin-layer two-dimensional semiconductor material together with the departure of the transfer platform.

[0020] Further, in steps (1) and (3), the evaporation rate is The thickness of the metal electrode is greater than 5 nm to ensure that the evaporated metal forms a dense metal film; the spin-coating speed is 1000 rpm - 5000 rpm, the spin-coating time is 1 - 2 minutes, the drying temperature is 130 - 160 °C, and the drying time is 2 - 3 minutes, so as to form a uniform organic flexible adhesive layer.

[0021] Further, in step (1), the annealing temperature is 100 °C - 160 °C, and the time is 2 - 5 minutes, to increase the adhesion between the organic flexible adhesive layer and the metal electrode 1 and the new substrate.

[0022] Further, in step (2), the thin-layer two-dimensional semiconductor material is MoS2, InSe, WSe2 or WS2, and the thin-layer two-dimensional semiconductor material should completely cover the bottom electrode to prevent short-circuiting between the upper and lower electrodes.

[0023] Further, in step (2), the lamination is achieved by slowly applying pressure through a transfer platform, so as to form a flat and dense contact interface between the thin-layer two-dimensional semiconductor material and the bottom electrode. Avoid applying a large pressure rapidly, which may cause bubbles, wrinkles, etc. in the interface after the thin-layer two-dimensional semiconductor material contacts the bottom electrode, and an ideal contact interface cannot be formed.

[0024] Further, in step (3), the transfer and lamination time is less than 2 minutes. In a short time, the surrounding environment is not sufficient to affect the metal and the material.

[0025] Further, in step (3), the release is carried out by heating through a bottom heating device after the metal electrode 2 and the thin-layer two-dimensional semiconductor material are completely attached. The heating temperature is 100 °C - 160 °C, and the heating time is 1 - 3 minutes. This softens the organic flexible adhesive layer and releases the organic flexible adhesive layer and the metal electrode 2 onto the thin-layer two-dimensional semiconductor material.

[0026] The beneficial effects of the present invention are as follows:

[0027] (1) The present invention demonstrates a method for fabricating an ultra-small-sized vertical diode by double-sided electrode lamination. Inverting the metal electrode onto the substrate can ensure that the metal electrode has atomic-level flatness (replicating the atomic-level flat surface of the sacrificial substrate). The intermediate layer material is selected as an atomically thin, clean, and flat two-dimensional semiconductor material, thereby ensuring the quality of the contact interface. The top electrode breaks through the damage caused by traditional high-energy metal deposition processes and selects the metal PMMA transfer technology, which can well retain the inherent two-dimensional material-metal interface and also avoid problems such as damage caused by top metal electrode deposition or random contact caused by surface roughness.

[0028] (2) The method of the present invention not only scales down the length of the vertical diode but also provides a general double-sided electrode lamination method for other ultra-thin vertical devices.

[0029] (3) The method of the present invention provides an ideal metal-2D interface. Based on this, the size limit of the vertical diode device can be miniaturized to the atomic level, providing an important approach for realizing integrated devices and circuits with high current density, low power consumption, and high-frequency switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the preparation process flow of the vertical Schottky diode in Embodiment 1 of the present invention;

[0031] Figure 2 Process flow chart of the preparation of the bottom electrode of the vertical Schottky diode in Embodiment 1 of the present invention;

[0032] Figure 3 Optical image of the vertical Schottky diode in Embodiment 1 of the present invention, TEM cross-sectional characterization of the metal-2D contact interface, and electrical performance measurement of the diode; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0034] Embodiment 1

[0035] In this embodiment, a vertical Schottky diode with a Pt bottom electrode, an Ag top electrode, and a two-dimensional semiconductor layer of MoS2 is taken as an example. A Schottky contact is formed between the Pt electrode and MoS2, and an ohmic contact is formed between the Ag electrode and MoS2. Figure 1This is the preparation process of the vertical Schottky diode in Embodiment 1 of the present invention. The specific preparation process includes the following steps:

[0036] 1) Prepare the inverted bottom electrode Pt, as Figure 1 shown in a:

[0037] For the specific preparation process of the bottom electrode, as shown in the appendix Figure 2 shown, lithographically mask the surface of the SiO2 substrate and then evaporate a 50-nm-thick Pt metal electrode, as Figure 2 shown in a. Next, use a hexamethyldisilazane (HMDS) layer to functionalize the entire wafer at 120 °C for 5 minutes, and then spin-coat a polymethyl methacrylate (PMMA) layer on the Pt metal electrode at a speed of 2000 rpm for 2 minutes, as Figure 2 shown in b. Subsequently, perform a drying treatment, with a drying temperature of 140 °C and a drying time of 2 minutes. Then, with the help of tweezers, mechanically peel off the PMMA layer with the Pt electrode from the sacrificial substrate, as Figure 2 shown in c. Subsequently, flip it and place it on a new SiO2 substrate, as Figure 2 shown in d. Finally, anneal the inverted bottom electrode for 3 minutes at an annealing temperature of 150 °C to make the inverted bottom electrode fit better with the new SiO2 substrate. Finally, the flat-bottom electrode Pt is prepared.

[0038] 2) Transfer the two-dimensional semiconductor material MoS2 to the top of the Pt electrode, as Figure 1 shown in b.

[0039] Mechanically peel off the MoS2 layer without dangling bonds and atomically flat from the surface of the two-dimensional semiconductor material using PDMS. Locate the target MoS2 layer with a uniform thickness and appropriate size under a microscope (the size of the 2D material completely covers the bottom electrode). Finally, under a custom-designed transfer platform (model METATEST E1-T), transfer the 2D material to the fixed position of the bottom electrode at a fixed point through the microscope. The contact between the 2D material and the bottom electrode is controlled by the z-axis device of the transfer platform. By slowly applying a downward pressure, a flat and dense contact interface is formed between the 2D material and the bottom metal. Avoid applying too much pressure and too large a z-axis descent speed, which may cause bubbles, wrinkles, etc. in the interface after the 2D material contacts the metal, and an ideal contact interface cannot be formed.

[0040] 3) Prepare the top electrode Ag, as Figure 1 shown in c and 1d.

[0041] A photolithographic mask was fabricated on the surface of the SiO2 substrate, and then a 50-nm-thick Ag metal electrode was deposited. Next, the entire wafer was functionalized with a hexamethyldisilazane (HMDS) layer at 120 °C for 5 minutes. Subsequently, polymethyl methacrylate (PMMA) was spin-coated onto the Ag metal electrode at 3000 rpm for 2 minutes. Then, drying treatment was carried out at a drying temperature of 140 °C for 2 minutes. Then, with the help of tweezers, the PMMA layer with the Ag electrode was mechanically peeled off from the SiO2 substrate. Finally, a fixed mechanical force was applied under the transfer platform to transfer and laminate the PMMA layer with the Ag electrode onto the thin MoS2 material, as Figure 1 shown in Figs. 1c and 1d. After the Ag metal and MoS2 were in complete contact, the device was heated at 120 °C for 2 minutes to release the PMMA and the silver electrode, completing the fabrication of the Schottky diode device.

[0042] From the attached Figure 3 optical picture of the diode device fabricated by laminating flat electrodes on both sides of MoS2 can be seen, as Figure 3 shown in Fig. 2a. The middle dashed line encloses the region of the 2D material MoS2 we selected. To analyze the interface between the metal and the 2D semiconductor material formed by the double-sided metal lamination method, we cut the cross-section of the fabricated diode by focused ion beam (FIB) and then observed it under a high-resolution transmission electron microscope (HRTEM). As Figure 3 shown in Fig. 2b, we can clearly observe an atomically clean and electrically sharp metal-2D semiconductor interface, and the integrity of the semiconductor layer is well preserved. This is in sharp contrast to the traditional direct deposition process of metal electrodes, which usually involves repeated bombardment of the channel by high-energy thermal atoms or atomic clusters, and the diffusion of metal into the two-dimensional channel, resulting in considerable interface damage.

[0043] From the attached Figure 3 Fig. 1c, the electrical output curves of diodes with different thicknesses prepared by the double-sided electrode lamination process can be seen. As the thickness of the diode decreases from 20 nm to 2.6 nm, the diode still has rectifying characteristics. Therefore, the thinnest 2.6-nm-sized MoS2 Schottky diode can be realized by our double-sided metal lamination process, and still has a rectification ratio of approximately 20. The realization of the ultra-small-sized MoS2 Schottky diode further highlights that the double-sided metal transfer lamination technology forms an ideal metal-2D contact interface, which does no harm to the material and preserves the inherent properties of the two-dimensional material with atomic thickness. When the size of the diode is scaled down to the atomic thickness, it still has excellent diode rectifying performance.

Claims

1. A method for preparing a vertically-aligned Schottky diode with ultra-small size, comprising: (1) Preparing an inverted bottom electrode: Evaporating and patterning a metal electrode 1 on an atomically flat sacrificial substrate and then performing a functionalization treatment; Spin-coating and drying an organic flexible adhesive layer on the functionalized sacrificial substrate, mechanically peeling off the organic flexible adhesive layer wrapping the metal electrode 1 and placing it upside down on a new substrate, such that the flat surface of the metal electrode 1 faces upward, and then performing an annealing treatment to form the bottom electrode; (2) Transferring a thin two-dimensional semiconductor material with no dangling bonds and atomic flatness onto the bottom electrode: Mechanically peeling off a thin two-dimensional semiconductor material with no dangling bonds and atomic flatness from a bulk two-dimensional semiconductor material using an organic flexible adhesive layer, and aligning and bonding the thin two-dimensional semiconductor material with no dangling bonds and atomic flatness to the bottom electrode through an alignment component of a transfer platform; (3) Preparing a top electrode: Evaporating and patterning a metal electrode 2 on an atomically flat sacrificial substrate and then performing a functionalization treatment; spin-coating and drying an organic flexible adhesive layer on the functionalized sacrificial substrate, mechanically peeling off the organic flexible adhesive layer wrapping the metal electrode 2, transferring and laminating it onto the thin two-dimensional semiconductor material with no dangling bonds and atomic flatness through an alignment component of a transfer platform, and releasing the organic flexible adhesive layer and the metal electrode 2 to complete the preparation of the top electrode; The work functions of the metal electrode 1 and the metal electrode 2 are different, forming an ohmic contact and a Schottky contact with the thin two-dimensional semiconductor material respectively; The organic flexible adhesive layer is a polymethyl methacrylate (PMMA) layer.

2. The method for preparing a vertical Schottky diode with ultra-small size according to claim 1, characterized in that: The metal electrode 1 is a metal with a high work function, and the metal electrode 2 is a metal with a low work function; or the metal electrode 1 is a metal with a low work function, and the metal electrode 2 is a metal with a high work function.

3. The method for preparing a vertical Schottky diode with ultra-small size according to claim 2, wherein: The metal with a high work function is platinum, palladium or gold; the metal with a low work function is silver or copper.

4. A method for fabricating a vertical Schottky diode with ultra-small dimensions according to any one of claims 1-3, characterized in that: The organic flexible adhesive layer is a polydimethylsiloxane (PDMS) layer; in steps (1) and (3), hexamethyldisilazane (HMDS) is used to perform a functionalization treatment on the sacrificial substrate.

5. A method for fabricating a vertical Schottky diode with ultra-small dimensions according to any one of claims 1-4, characterized in that: In the said step (1) and step (3), the evaporation rate is the thickness of the metal electrode is greater than 5 nm; the spin coating speed is 1000 rpm - 5000 rpm, the spin coating time is 1 - 2 minutes, the drying temperature is 130 - 160 °C, and the drying time is 2 - 3 minutes.

6. A method for preparing a vertical Schottky diode with ultra-small size according to any one of claims 1-5, characterized in that: In step (1), the annealing temperature is 100°C - 160°C, and the time is 2 - 5 minutes.

7. A method for preparing a vertical Schottky diode with ultra-small size according to any one of claims 1-6, characterized in that: The thin two-dimensional semiconductor material is MoS2, InSe, WSe2 or WS2, and the thin two-dimensional semiconductor material completely covers the bottom electrode.

8. A method for fabricating a vertical Schottky diode with ultra-small size according to any one of claims 1-7, characterized in that: In step (2), the bonding is achieved by slowly applying pressure through a transfer platform, such that a flat and dense contact interface is formed between the thin two-dimensional semiconductor material and the bottom electrode.

9. A method for fabricating a vertical Schottky diode with ultra-small size according to any one of claims 1-8, characterized in that: In step (3), the transfer and lamination time is less than 2 minutes.

10. A method for fabricating a vertical Schottky diode with ultra-small size according to any one of claims 1-9, characterized in that: The release in step (3) is performed by heating through a bottom heating device when the metal electrode 2 and the thin two-dimensional semiconductor material are completely attached, with a heating temperature of 100°C - 160°C and a heating time of 1 - 3 minutes.

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