A method of adjusting product direction for improved warpage

By adjusting the chip arrangement direction and using an adhesive layer with a low coefficient of thermal expansion during the chip packaging process, the warpage problem was solved and warpage was improved.

CN114664672BActive Publication Date: 2026-02-27HEFEI SMAT TECH CO LTD
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Patent Information

Application Number
CN202210255113.0
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-03-16
Publication Date
2026-02-27
Estimated Expiration
2042-03-16

AI Technical Summary

Technical Problem

In the chip packaging process, the warpage problem is difficult to improve by changing the raw materials and process parameters due to the different volume ratios of raw materials in the row and column directions. In particular, the warpage in the row and column directions is significantly different in the substrate-level packaging process.

Method used

By applying an adhesive layer with a coefficient of thermal expansion lower than that of the encapsulation layer to the carrier plate and arranging the chips in a specific direction, a uniform encapsulation layer spacing is formed, and the chip arrangement is adjusted to balance the unevenness of thermal expansion and contraction.

Benefits of technology

It effectively reduces warpage by adjusting the chip arrangement to balance thermal expansion and contraction in the row and column directions, thus improving the warpage problem.

✦ Generated by Eureka AI based on patent content.

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Abstract

The application discloses a method for adjusting product direction to improve warping, which is characterized by comprising the following steps: a gluing step: providing a carrier plate capable of bearing multiple chips, and applying a bonding layer on the carrier plate; an adjusting product direction step: placing the chips according to the fact that the spacing areas formed between the four directions of adjacent chips are equal; and an encapsulating step: placing different chips on the carrier plate, forming encapsulating layers on the bonding layer and the surfaces of the chips, and ensuring that the spacing between adjacent encapsulating layers is equal. The volume ratio of different materials in two directions is balanced by changing the arrangement direction of the products, so that the warping degree is reduced.
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Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor packaging, and particularly relates to a method for adjusting product direction to improve warping. BACKGROUND

[0002] In the packaging process of chip processing, especially in the panel level package process, warping is one of the most important problems to be considered. Warping is affected by the selection of raw materials, production parameters, etc. At the same time, due to the design problem of the product, the warping of some products has a great difference in the row and column directions. This warping is difficult to improve by changing the raw materials and process parameters, and the fundamental reason is that the volume ratio of the raw materials in the row and column directions of the product is different.

[0003] Suppose the chip is a rectangle, then the expansion when heated and the contraction when cooled in the direction parallel to the long side of the chip is faster, and the expansion when heated and the contraction when cooled in the direction perpendicular to the long side of the chip is slower. Because the thermal expansion and contraction in different directions are different, a certain degree of warping is generated in the packaging process. SUMMARY

[0004] To solve the above problems in the prior art, the present application provides a method for adjusting product direction to improve warping.

[0005] To achieve the above purpose, the method for adjusting product direction to improve warping of the present application comprises the following steps:

[0006] The material taking step: providing a carrier plate capable of carrying multiple chips;

[0007] The gluing step: applying or pasting an adhesive layer on the carrier plate;

[0008] The product direction adjusting step: placing the chips so that the spacing areas formed by the spacings between the four directions of adjacent chips are equal;

[0009] The encapsulating step: placing different chips on the carrier plate to form encapsulating layers on the surface of the adhesive layer and the chips, and the spacings between adjacent encapsulating layers are equal.

[0010] Further, the encapsulating layers formed by each chip are bonded on the carrier plate in a matrix manner.

[0011] Further, when the encapsulating layer encloses a square and the chip is a rectangular chip, the product direction adjusting step: placing the chips so that the long side directions of adjacent chips are perpendicular to each other.

[0012] Further, when the encapsulation layer is a rectangle and the chip is a rectangle chip, the adjusting product direction step is: placing the adjacent chips in the long side direction of the chip parallel to each other, and the long side of the chip is parallel to the long side of the rectangle encapsulation layer.

[0013] Further, when the encapsulation layer is a rectangle and the chip is a square chip, the adjusting product direction step is: distributing the adjacent chips in each horizontal direction of the matrix according to the broken line, and the distance between the chips opposite to each other between the horizontal direction and the horizontal direction is alternately distributed according to L1 and L2.

[0014] Further, the thermal expansion coefficient of the bonding layer is lower than the thermal expansion coefficient of the encapsulation layer.

[0015] The present application balances the change in the thermal expansion and contraction in the row and column directions by changing the direction of the product arrangement. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A packaging flow chart of the method for adjusting the product direction to improve warping is provided for the present application;

[0017] Figure 2 An encapsulation cross-sectional view of the method for adjusting the product direction to improve warping is provided for the present application;

[0018] Figure 3 A product layout schematic diagram of the present application is provided, in which the encapsulation layer is a square and the chip is a rectangle;

[0019] Figure 4 A product layout schematic diagram of the present application is provided, in which the encapsulation layer is a rectangle and the chip is a rectangle;

[0020] Figure 5 A product layout schematic diagram of the present application is provided, in which the encapsulation layer is a rectangle and the chip is a square.

[0021] Marked in the figure: encapsulation layer 1, chip 2, carrier plate 3, bonding layer 4. DETAILED DESCRIPTION

[0022] In order to better understand the purpose, structure and function of the present application, the following will be combined with the accompanying drawings to make a detailed description. Figures 1-5 The method for adjusting the product direction to improve warping is further described in detail.

[0023] In the packaging process, the CTE of the chip is about 6, the CTE of the EMC plastic encapsulation material is about 10, and the warping problem of the chip 2 is affected by the selection of raw materials, production parameters, etc. At the same time, due to the design problem of the product, the warping of some products has a great difference in the row and column directions. This warping is difficult to improve by changing the raw materials and process parameters, and the fundamental reason is that the volume ratio of the raw materials in the row and column directions of the product is different.

[0024] Assuming that the chip 2 is rectangular, then the expansion when heated and the contraction when cooled is faster in the direction parallel to the long side of the chip 2, and slower in the direction perpendicular to the long side of the chip 2. Because the thermal expansion and contraction in different directions are different, a certain degree of warping is generated during the packaging process.

[0025] The patent designs a method for adjusting the direction of products to improve warping, characterized in that it comprises the following steps:

[0026] S1, taking material step: providing a carrier plate 3 that can carry multiple chips 2;

[0027] S2, gluing step: applying or pasting a bonding layer 4 on the carrier plate 3, wherein the thermal expansion coefficient of the bonding layer 4 is lower than the thermal expansion coefficient of the encapsulating layer 1.

[0028] S3, adjusting the direction of products step: placing the chips 2 according to the fact that the spacing areas formed by the spacing between the four directions of adjacent chips 2 are the same;

[0029] S4, encapsulating step: placing different chips 2 on the carrier plate 3 to form an encapsulating layer 1 on the surface of the bonding layer 4 and the chips 2, and the spacing between adjacent encapsulating layers 1 is equal, and the encapsulating layers 1 formed by each chip 2 are bonded on the carrier plate 3 in a matrix manner.

[0030] Example 1

[0031] When the encapsulating layer 1 forms a square and the chip 2 is a rectangular chip 2, the adjusting the direction of products step is: placing the chips 2 according to the fact that the long sides of adjacent chips 2 are perpendicular to each other.

[0032] Example 2

[0033] When the encapsulating layer 1 forms a rectangle and the chip 2 is a rectangular chip 2, the adjusting the direction of products step is: placing the chips 2 according to the fact that the long sides of adjacent chips 2 are parallel to each other, and the long side of the chip 2 is parallel to the long side of the rectangular encapsulating layer 1.

[0034] Example 3

[0035] When the encapsulating layer 1 forms a rectangle and the chip 2 is a square chip 2, the adjusting the direction of products step is: distributing the adjacent chips 2 in each horizontal direction of the matrix according to the broken line, and distributing the chips 2 opposite to each other between the horizontal directions according to two different spacings L1 and L2.

[0036] The patent balances the volume ratio of different materials in two directions by changing the direction of product arrangement, thereby reducing the warping degree.

[0037] It is to be understood that the present application is described by way of example only, and that modifications or alterations can be made to the features and embodiments described without departing from the spirit and scope of the application. In addition, modifications can be made to the features and embodiments described to accommodate specific situations and materials without departing from the spirit and scope of the application. Accordingly, the application is not limited to the specific embodiments disclosed herein, but rather, the scope of the application includes all embodiments falling within the scope of the claims.

Claims

1. A method for adjusting the orientation of a product to improve warpage, characterized in that, Includes the following steps: Material handling steps: Provide a carrier board (3) that can carry multiple chips (2); Adhesive application steps: Apply or attach adhesive layer (4) to carrier plate (3); Product orientation adjustment steps: Place the chips (2) so that the spacing area formed by the four directions of the adjacent chips (2) is the same; Encapsulation step: Place different chips (2) on a carrier plate (3) to form an encapsulation layer (1) on the adhesive layer (4) and the surface of the chip (2), with equal spacing between adjacent encapsulation layers (1); When the encapsulation layer (1) forms a rectangle and the chip (2) is a square chip (2), the adjacent chips (2) on each horizontal axis of the matrix are distributed according to the broken line, and the spacing between the opposing chips (2) between the horizontal axes is distributed alternately according to two different spacings, L1 and L2.

2. The method for adjusting product orientation to improve warping according to claim 1, characterized in that, The encapsulation layers (1) formed by each chip (2) are bonded to the carrier plate (3) in a matrix manner.

Citation Information

Patent Citations

  • Method suitable for IGBT stress counteracting

    CN113675085A

  • Chip package structure and manufacturing method therefor

    WO2018113356A1