A wide bandgap power semiconductor module based on bypass copper pillar heat spreading

Abstract

The application discloses a wide-bandgap power semiconductor module based on bypass copper column heat dissipation, a plurality of series or parallel wide-bandgap power semiconductor chips are arranged on a conductive metal substrate on the upper surface of a power substrate; the top and bottom power substrates are supported and connected by bypass copper columns and auxiliary copper columns; the layout design of the bypass copper columns makes the parallel chip heat dissipation environment similar and the thermal coupling consistent in the power module, so that the chip temperature equalization effect is achieved; the heat transfer capacity of the bypass copper columns provides a channel for the chip to conduct heat to the top power substrate, greatly improves the chip heat dissipation capacity, and is suitable for a large-current grade power module with a plurality of parallel wide-bandgap semiconductor power chips.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, and specifically relates to a wide bandgap power semiconductor module based on bypass copper pillar heat dissipation. Background Technology

[0002] A power module is a type of module formed by packaging and integrating a series of power semiconductor chips according to a specific topology to achieve a certain function. Compared with the topology composed of discrete power devices, power modules have high integration and offer significant advantages in terms of electrical performance, thermal performance, safety, device lifespan, and cost.

[0003] With the continuous development of semiconductor power devices, and driven by increasingly stringent application requirements in important fields such as new energy grid connection, high-voltage direct current transmission, electric vehicles, high-speed rail, aerospace, and pulse power (military and civilian applications), as well as the influence of energy conservation and the "dual-carbon" slogan, power modules are constantly evolving towards miniaturization, low loss, high power density, high reliability, and high integration. In particular, the emergence of a new generation of wide-bandgap semiconductor devices, represented by silicon carbide and gallium nitride materials, is gradually replacing silicon-based devices in various industrial fields, accelerating the development of power modules. This allows power modules using wide-bandgap power semiconductor chips to have smaller sizes at the same voltage and current ratings, operate at higher temperatures, and operate at higher switching frequencies, further reducing the size of passive components and improving converter efficiency. However, existing packaging still uses silicon-based packaging structures, which are far from fully utilizing the advantages of wide-bandgap power semiconductors, mainly in the following aspects:

[0004] 1. Traditional power modules are suitable for large-area silicon-based semiconductor power chips. These devices are usually connected in parallel in small numbers and require an anti-parallel power diode. In contrast, wide-bandgap power semiconductor switching chips have a small area and can be connected in series and parallel on the same substrate area. Furthermore, due to their excellent body diode characteristics, anti-parallel or non-anti-parallel power diode chips can be selected.

[0005] 2. Traditional power modules have only one bottom substrate. Heat dissipation of the power chip relies primarily on a single path: the bottom substrate and the heat sink. This cooling method, also known as single-sided cooling, has low efficiency and results in high thermal resistance between the power electronic chip and the surrounding environment, which is detrimental to the long-term reliable operation of the power module. When heat cannot be effectively dissipated, the bonding wires, which provide electrical connections, are prone to aging or even detachment at the bonding points, leading to power module failure. This is especially true for wide-bandgap power chips based on silicon carbide. Although their thermal conductivity is much higher than silicon, their significantly smaller chip area compared to silicon-based chips results in a smaller heat dissipation area, making the overall heat dissipation challenge even more severe than with silicon.

[0006] 3. Traditional power modules struggle to achieve uniform current and temperature distribution across chips, which is crucial in high-frequency and harsh environments. Uneven dynamic current distribution in chips is primarily due to the uneven distribution of parasitic inductance in the parallel branches. This uneven distribution causes unequal current and voltage stress on the power chip during switching transients, potentially leading to chip breakdown and failure. This effect is even more pronounced in wide-bandgap semiconductor power devices. Simultaneously, uneven dynamic current distribution leads to uneven chip losses, resulting in uneven chip temperature. This causes different rates of aging and failure of the bonding layers on different chips, and further exacerbates the uneven dynamic current distribution of parallel chips by affecting the chip's threshold voltage, ultimately accelerating the overall failure of the power module.

[0007] In summary, the excellent characteristics of wide-bandgap power semiconductors are limited by traditional packaging, failing to fully realize their superior electrical and thermal properties. Therefore, a novel packaging structure is needed to overcome the shortcomings of traditional power modules, increase the module's heat dissipation capacity, and thus fully utilize the superior characteristics of wide-bandgap devices. Summary of the Invention

[0008] The technical problem to be solved by this invention is to address the shortcomings of the prior art by providing a wide bandgap power semiconductor module based on bypass copper pillar heat dissipation, thereby improving and extending existing module heat dissipation technology. By using bypass copper pillar technology, the module's heat dissipation capacity is increased, achieving double-sided heat dissipation, thus enabling multi-chip, high-current power modules.

[0009] The present invention adopts the following technical solution:

[0010] A wide bandgap power semiconductor module based on bypass copper pillar heat dissipation includes several wide bandgap power semiconductor chips connected in series or parallel. The wide bandgap power semiconductor chips are disposed between a top power substrate and a bottom power substrate, and the top power substrate and the bottom power substrate are connected by bypass copper pillars and auxiliary copper pillars.

[0011] The wide bandgap power semiconductor chip is connected to the power circuit of the upper conductive metal region of the bottom power substrate by bonding wires, and the wide bandgap power semiconductor chip is connected to the power circuit of the upper conductive metal region of the top power substrate by bypass copper pillars and auxiliary copper pillars. The upper and lower bridge arms of the half-bridge structure are formed by several wide bandgap power semiconductor chips.

[0012] Power terminals are provided on the upper surface of the bottom power substrate; drive terminals are provided on the conductive metal area on the lower surface of the top power substrate and the conductive metal area on the upper surface of the bottom power substrate.

[0013] Specifically, the top power substrate consists of a top upper surface metal layer, a top insulating dielectric layer, and a top lower surface metal layer from top to bottom, with several conductive regions divided on the top lower surface metal layer.

[0014] Furthermore, the conductive regions include a first top conductive region, a second top conductive region, a third top conductive region, a fourth top conductive region, a fifth top conductive region, and a sixth top conductive region. The first top conductive region and the second top conductive region are connected to the drive terminal, the third top conductive region and the fourth top conductive region are connected to the heat conduction path of the wide bandgap power semiconductor chip, and the fifth top conductive region and the sixth top conductive region are connected to the drive circuit.

[0015] Specifically, the bottom power substrate comprises, from top to bottom, a bottom upper surface metal layer, a bottom insulating dielectric layer, and a bottom lower surface metal layer, with several conductive regions disposed on the bottom upper surface metal layer.

[0016] Furthermore, the conductive regions include a first bottom conductive region, a second bottom conductive region, a third bottom conductive region, a fourth bottom conductive region, a fifth bottom conductive region, a sixth bottom conductive region, a seventh bottom conductive region, an eighth bottom conductive region, a ninth bottom conductive region, and a tenth bottom conductive region; the first bottom conductive region, the fifth bottom conductive region, and the sixth bottom conductive region are connected to power terminals, the second bottom conductive region, the fourth bottom conductive region, the seventh bottom conductive region, the eighth bottom conductive region, the ninth bottom conductive region, and the tenth bottom conductive region are respectively connected to corresponding drive circuits, and the third bottom conductive region is connected to a bypass copper pillar; the wide bandgap semiconductor power chip includes several upper bridge arm chips disposed on the fifth bottom conductive region and several lower bridge arm chips disposed on the third bottom conductive region.

[0017] Furthermore, the number of upper bridge arm chips and lower bridge arm chips is the same, and the spacing between adjacent upper bridge arm chips and adjacent lower bridge arm chips is the same.

[0018] Specifically, the driving terminals include a Kelvin upper bridge arm source terminal and an upper bridge arm gate terminal disposed on the bottom upper surface metal layer of the bottom power substrate; and a Kelvin lower bridge arm source terminal and a lower bridge arm gate terminal disposed on the top lower surface metal layer of the top power substrate.

[0019] Specifically, the power terminals include a DC power negative terminal, a DC power positive terminal, and an AC power terminal respectively disposed on the metal layer on the bottom upper surface of the bottom power substrate, and a first coupling capacitor and a second coupling capacitor are disposed between the DC power positive terminal and the DC power negative terminal.

[0020] Specifically, the bypass copper pillars are arranged horizontally in relation to the parallel wide-bandgap semiconductor chipset, and vertically between the top power substrate and the bottom power substrate, and are disposed on the bottom upper surface metal layer of the bottom power substrate; there are multiple auxiliary copper pillars arranged parallel to the bypass copper pillars.

[0021] Specifically, the upper bridge arm has a first heat conduction path and a second heat conduction path at the wide bandgap power semiconductor chip. One end of the first heat conduction path is connected to the wide bandgap power semiconductor chip, and the other end conducts heat through the conductive area of ​​the bottom upper surface metal layer on the bottom power substrate, the bottom insulating dielectric layer of the bottom power substrate, and the bottom lower surface metal layer of the bottom power substrate. One end of the second heat conduction path is connected to the wide bandgap power semiconductor chip, and the other end conducts heat to the outside through the conductive area of ​​the bottom upper surface metal layer on the bottom power substrate laterally, and then through the bypass copper pillar, the conductive area of ​​the top lower surface metal layer, the top insulating dielectric layer of the top power substrate, and the top upper surface metal layer of the top power substrate.

[0022] The lower bridge arm has a first heat conduction path and a second heat conduction path at the wide bandgap power semiconductor chip. One end of the first heat conduction path is connected to the wide bandgap power semiconductor chip, and the other end sequentially passes longitudinally through the conductive area of ​​the bottom upper surface metal layer on the bottom power substrate, the bottom insulating dielectric layer of the bottom power substrate, and the bottom lower surface metal layer of the bottom power substrate to conduct heat outward. One end of the second heat conduction path is connected to the wide bandgap power semiconductor chip, and the other end transversely passes through the conductive area of ​​the bottom upper surface metal layer on the bottom power substrate, and then sequentially passes longitudinally through the bypass copper pillar, the conductive area of ​​the top lower surface metal layer on the top power substrate, the top insulating dielectric layer of the top power substrate, and the top upper surface metal layer of the top power substrate to conduct heat outward.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects:

[0024] This invention discloses a wide-bandgap power semiconductor module based on bypass copper pillar heat dissipation. By using bypass copper pillars and auxiliary copper pillars positioned next to the power semiconductor chips, the connection between the top and bottom power substrates is achieved. The bypass copper pillars provide two heat conduction paths for each wide-bandgap power semiconductor chip, thus achieving double-sided heat dissipation. This significantly reduces the overall thermal resistance of the module, enhances its heat dissipation capacity, reduces the possibility of bonding wire electrical interconnect failure, improves the reliability of the power module operating in extreme environments, and creates a three-dimensional conductive loop, reducing parasitic inductance caused by packaging. During current switching, the currents in the upper and lower bridge arms are in opposite directions in space, allowing the mutual inductance of the loop to cancel out parasitic inductance, greatly reducing the parasitic inductance of the commutation loop. The DC leads of the power loop (DC power positive and DC power negative terminals) are spatially compact, facilitating the design of stacked busbars and the installation of decoupling capacitors, thereby avoiding the introduction of loop inductance into the external circuitry during module application and reducing turn-on voltage oscillation and turn-off current oscillation.

[0025] Furthermore, the top power substrate is configured as a three-layer structure. The upper surface metal layer is connected to the substrate or directly to the heat sink to realize the heat dissipation function of the module. The middle ceramic layer is used for insulation and thermal conduction. The lower surface metal layer is divided into several metal regions for electrical connection and heat conduction of semiconductor chips.

[0026] Furthermore, several conductive metal regions are provided on the lower surface metal layer of the top power substrate for connecting the bypass copper pillars, auxiliary copper pillars, and lower bridge arm drive terminals. The conductive metal regions use copper with the largest possible area to enhance current flow capacity and module heat conduction capacity while meeting insulation requirements.

[0027] Furthermore, similar to the top power substrate, the bottom power substrate is a typical three-layer structure. The upper surface metal layer is divided into several metal regions for electrical connection and heat conduction of the semiconductor chip, the middle ceramic layer is used for insulation and heat conduction, and the lower surface metal layer is connected to the substrate or directly to the heat sink to realize the heat dissipation function of the module.

[0028] Furthermore, similar to the lower surface metal layer of the top power substrate, the upper surface metal layer of the bottom power substrate is provided with several conductive metal areas for connecting bypass copper pillars, auxiliary copper pillars, power terminals, upper bridge arm drive terminals, and power chips. The conductive metal areas use copper with the largest possible area to enhance current flow capacity and module heat conduction capacity while meeting insulation requirements.

[0029] Furthermore, all power chips connected in parallel on the same bridge arm have the same arrangement direction. Auxiliary copper pillars are set on the basis of the bypass copper pillars to realize the Kelvin connection between the gate lead and the source lead of the gate circuit (control circuit) or the gate lead and the emitter lead of the gate circuit (control circuit), thereby greatly reducing the common source inductance / common emitter inductance, making the module more reliable and achieving the effect of reliable driving.

[0030] Furthermore, the upper and lower bridge arm drive terminals are arranged on opposite sides in space and placed on different power substrates, thereby reducing the interference between drive signals of different bridge arm chipsets and further increasing the stability of module driving.

[0031] Furthermore, the DC positive power terminals and DC negative power terminals are arranged on the same side in space and respectively located on the bottom power substrate and the top power substrate. This allows for easy design of a stacked busbar structure, enabling the combination of multiple modules in series and parallel. The setting of coupling capacitors can minimize the introduction of inductors other than those at the power terminals into the commutation circuit, further improving the stability of the module.

[0032] Furthermore, the present invention uses bypass copper pillars. For each parallel branch of the chipset, a bypass copper pillar is set. The position of the copper pillar can be flexibly set according to the layout of the power chips in the module. Moreover, by flexibly changing the shape of the copper pillar, the parasitic inductance distribution of the parallel circuit branches can be made more uniform, and the heat dissipation environment of each chip can be basically the same, making it easy to achieve current sharing and temperature sharing for multiple chips in parallel.

[0033] Furthermore, each power chip in the upper and lower bridge arm chipsets has two main heat conduction paths. In addition to direct heat conduction and heat dissipation through the bottom power substrate, the power chip can also conduct heat to the top power substrate through the adjacent bypass copper pillars, thereby greatly reducing the thermal resistance of the chip to the outside world.

[0034] In summary, the present invention uses a power module based on bypass copper pillar heat dissipation. The bypass copper pillar not only provides mechanical support for the power module and enables double-sided heat dissipation, but also provides a three-dimensional conductive path and a double-sided thermal conductive path. The overall structure is compact, reducing the module size, thereby improving the electrical, thermal and mechanical performance of the entire module.

[0035] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the overall structure of an embodiment of the present invention;

[0037] Figure 2 This is a diagram showing the top power substrate structure and the layout of the conductive metal region in an embodiment of the present invention;

[0038] Figure 3 This is a diagram showing the bottom power substrate structure and the layout of the conductive metal region in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram showing the positions of the wide bandgap power chip, driver terminal, power terminal, and bypass copper pillar in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram showing the structure and position of the bypass copper pillar and the auxiliary copper pillar in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the heat conduction path of the parallel chip in the upper bridge arm in an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of the heat conduction path of the parallel chip in the lower bridge arm in an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of adding a coupling capacitor to the DC power terminal in an embodiment of the present invention;

[0044] Figure 9 This is a schematic diagram illustrating the integration of the power module and the finned liquid cooler in an embodiment of the present invention.

[0045] Wherein: 100. Top power substrate; 101. Top upper surface metal layer; 102. Top insulating dielectric layer; 103. Top lower surface metal layer; 111. Top first conductive region; 112. Top second conductive region; 113. Top third conductive region; 114. Top fourth conductive region; 115. Top fifth conductive region; 116. Top sixth conductive region; 200. Bottom power substrate; 201. Bottom upper surface metal layer; 202. Bottom insulating dielectric layer; 203. Bottom lower surface metal layer; 204. AC power terminal; 205. DC power positive terminal; 206. DC power negative terminal; 211. Bottom first conductive region; 212. Bottom second conductive region; 213. Bottom third conductive region; 214. Bottom fourth conductive region; 21 5. Bottom fifth conductive region; 216. Bottom sixth conductive region; 217. Bottom seventh conductive region; 218. Bottom eighth conductive region; 219. Bottom ninth conductive region; 220. Bottom tenth conductive region; 301. Upper bridge arm bypass copper pillar; 302. Lower bridge arm bypass copper pillar; 501. First semiconductor chip; 502. Second semiconductor chip; 503. Third semiconductor chip; 504. Fourth semiconductor chip; 505. Fifth semiconductor chip; 506. Sixth semiconductor chip; 601. First heat conduction path of upper bridge arm semiconductor chip; 602. Second heat conduction path of upper bridge arm semiconductor chip; 603. First heat conduction path of lower bridge arm semiconductor chip; 604. Second heat conduction path of lower bridge arm semiconductor chip; 701. First coupling capacitor; 702. Second coupling capacitor. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "one side," "one end," and "one side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0048] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0049] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0050] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0051] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0052] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0053] This invention provides a wide bandgap power semiconductor module based on bypass copper pillar heat dissipation, suitable for high-current power modules with multiple wide bandgap semiconductor power chips connected in parallel; several wide bandgap power semiconductor chips connected in series or parallel are arranged on a conductive metal substrate on the upper surface of a power substrate; the top power substrate and the bottom power substrate are supported and connected by bypass copper pillars and auxiliary copper pillars; the layout design of the bypass copper pillars makes the heat dissipation environment of the parallel chips in the power module similar and the thermal coupling consistent, achieving the effect of chip temperature uniformity; the heat transfer capability of the bypass copper pillars provides a channel for the chips to conduct heat to the top power substrate, greatly improving the chip heat dissipation capability.

[0054] Please see Figure 1 The present invention discloses a wide bandgap power semiconductor module based on bypass copper pillar heat dissipation, comprising:

[0055] Top power substrate 100, bottom power substrate 200, bypass copper pillars, auxiliary copper pillars, drive terminals, power terminals, and wide bandgap semiconductor chips.

[0056] A wide-bandgap semiconductor chip is disposed between a top power substrate 100 and a bottom power substrate 200. The wide-bandgap power semiconductor chip is connected to the power circuit of the conductive metal region on the bottom power substrate 200 via bonding wires. The wide-bandgap power semiconductor chip is connected to the power circuit of the conductive metal region on the top power substrate 100 via bypass copper pillars and auxiliary copper pillars. Power terminals are disposed on the upper surface of the bottom power substrate 200 for connecting DC and AC power. Drive terminals are respectively disposed on the conductive metal region on the lower surface of the top power substrate 100 and the conductive metal region on the upper surface of the bottom power substrate 200. The upper and lower bridge arms of the half-bridge structure are formed by several wide-bandgap power semiconductor chips.

[0057] Please see Figure 2 The top power substrate 100 includes, from top to bottom, a top upper surface metal layer 101, a top insulating dielectric layer 102, and a top lower surface metal layer 103. The top upper surface metal layer 101 and the top lower surface metal layer 103 are made of copper or aluminum. The top insulating dielectric layer 102 is made of aluminum oxide, aluminum nitride, or silicon nitride.

[0058] The top lower surface metal layer 103 is divided into several conductive regions, including a top first conductive region 111, a top second conductive region 112, a top third conductive region 113, a top fourth conductive region 114, a top fifth conductive region 115, and a top sixth conductive region 116.

[0059] Please see Figure 3 The bottom power substrate 200 includes, from top to bottom, a bottom upper surface metal layer 201, a bottom insulating dielectric layer 202, and a bottom lower surface metal layer 203. The bottom upper surface metal layer 201 and the bottom lower surface metal layer 203 are made of copper or aluminum, and the bottom insulating dielectric layer 202 is made of aluminum oxide, aluminum nitride, or silicon nitride.

[0060] The bottom upper surface metal layer 201 is provided with a number of conductive regions, including the bottom first conductive region 211, the bottom second conductive region 212, the bottom third conductive region 213, the bottom fourth conductive region 214, the bottom fifth conductive region 215, the bottom sixth conductive region 216, the bottom seventh conductive region 217, the bottom eighth conductive region 218, the bottom ninth conductive region 219 and the bottom tenth conductive region 220.

[0061] Please see Figure 3 and Figure 4 The wide bandgap semiconductor power chip includes a plurality of upper bridge arm chips disposed in the bottom fifth conductive region 215 and a plurality of lower bridge arm chips disposed in the bottom third conductive region 213. The number of upper bridge arm chips and lower bridge arm chips is the same, and the spacing between adjacent upper bridge arm chips and adjacent lower bridge arm chips is the same.

[0062] Please see Figure 4 The drive terminals include:

[0063] Kelvin upper bridge arm source terminals are located at the bottom seventh conductive region 217 and the bottom tenth conductive region 220;

[0064] Upper bridge arm gate terminals are disposed at the bottom eighth conductive region 218 and the bottom ninth conductive region 219.

[0065] The Kelvin lower bridge arm source terminal is located at the top first conductive region 111;

[0066] The lower bridge arm gate terminal is located at the top second conductive region 112.

[0067] Power terminals include:

[0068] DC power negative terminal 206 is disposed at the bottom first conductive region 211;

[0069] DC power positive terminal 205 is located at the bottom fifth conductive region 215;

[0070] AC power terminal 204 is located at the sixth conductive area 216 at the bottom.

[0071] Please see Figure 4 and Figure 5 The bypass copper pillars are positioned horizontally in relation to the parallel wide-bandgap semiconductor chipset and vertically between the top power substrate 100 and the bottom power substrate 200; the bypass copper pillars are made of pure copper or copper alloy.

[0072] The bypass copper pillars include an upper bridge arm bypass copper pillar 301 and a lower bridge arm bypass copper pillar 302; the upper bridge arm bypass copper pillar 301 is located at the fifth conductive area 215 at the bottom; the lower bridge arm bypass copper pillar 302 is located at the third conductive area 213 at the bottom.

[0073] Multiple auxiliary copper pillars are arranged parallel to the bypass copper pillars. These auxiliary copper pillars, together with the bypass copper pillars, serve to provide mechanical and electrical connections between the top power substrate 100 and the bottom power substrate 200.

[0074] The working principle of the wide bandgap power semiconductor module based on bypass copper pillar heat dissipation in this invention is as follows:

[0075] When the module is connected to the circuit, the wide-bandgap semiconductor chip located on the bottom power substrate generates a large amount of heat, becoming the main heat source inside the module. To prevent the module from failing due to overheating, the heat generated by the chip must be quickly conducted away. In this module, in addition to the traditional heat conduction path through its power substrate, the chip can also conduct heat to another power substrate located opposite its own power substrate through bypass copper pillars. This allows for rapid heat conduction within a compact spatial layout, significantly improving the module's heat dissipation capacity and enabling a high-power-density, high-current-level power module.

[0076] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0077] Example

[0078] Please see Figure 1 and Figure 4 The packaging structure in this embodiment consists of two groups of six wide-bandgap power semiconductor chips, two bypass copper pillars, two power substrates, and three power terminals.

[0079] The six wide-bandgap power semiconductor chips are specifically the first semiconductor chip 501, the second semiconductor chip 502, the third semiconductor chip 503, the fourth semiconductor chip 504, the fifth semiconductor chip 505, and the sixth semiconductor chip 506.

[0080] The two bypass copper pillars are specifically the upper bridge arm bypass copper pillar 301 and the lower bridge arm bypass copper pillar 302;

[0081] The two power substrates are specifically the top power substrate 100 and the bottom power substrate 200;

[0082] The three power terminals are specifically the DC power positive terminal 205, the DC power negative terminal 206, and the AC power terminal 204.

[0083] This embodiment includes two groups of three parallel wide-bandgap power semiconductor chips, totaling eight, forming the upper and lower bridge arm switching transistors of a classic half-bridge structure. In actual operation, the number of parallel chips can be increased or decreased to change the current carrying capacity, or the number of series chips can be increased or decreased to change the voltage withstand capacity. Anti-parallel diode chips can also be added as needed.

[0084] It should be noted that the wide bandgap semiconductor power chip mentioned in this invention can also be replaced with a non-wide bandgap semiconductor power chip according to actual needs.

[0085] The function of bypass copper pillars is to conduct heat, provide electrical connections, and provide mechanical support. They can be made of pure copper or other metals and alloys with good thermal and electrical conductivity. Different materials are selected according to the usage environment and reliability requirements. In the example, the bypass copper pillar is a long rectangular shape, but the shape can also be flexibly adjusted according to the actual chip location and the layout of the conductive metal area.

[0086] The top power substrate 100 and the bottom power substrate 200 are typically, but are not limited to, directly bonded copper ceramic substrates, active metal brazed ceramic copper-clad substrates, etc.

[0087] The top insulating dielectric layer 102 and the bottom insulating dielectric layer 202 are made of ceramic materials such as alumina, aluminum nitride, and silicon nitride, or other insulating media, and perform the functions of insulation and heat conduction.

[0088] The conductive metal layers on the upper and lower surfaces of the top power substrate 100 and the bottom power substrate 200 are conductive metals, mostly copper and aluminum.

[0089] The top upper surface metal layer 101 of the top power substrate 100 and the bottom lower surface metal layer 203 of the bottom power substrate 200 are used to perform the function of connecting the heat sink and improving heat dissipation efficiency.

[0090] The top lower surface metal layer 103 of the top power substrate 100 and the bottom upper surface metal layer 201 of the bottom power substrate 200 are used to perform electrical connection and heat conduction functions.

[0091] Bypass copper pillars and auxiliary copper pillars

[0092] Please see Figure 4 and Figure 5 The bypass copper pillar is the core technology of the packaging structure in this invention; the top power substrate 100 and the bottom power substrate 200 are supported and connected by the bypass copper pillar; the bypass copper pillar is set next to the parallel semiconductor chip of the bridge arm and located in the same conductive area of ​​the bottom power substrate;

[0093] The design principle of bypass copper pillars is to maximize the base area of ​​the copper pillars, place them close to the chipsets that are electrically connected, and make their shapes similar or consistent with the heat dissipation environment of the parallel chipsets, while ensuring electrical clearance and creepage distance.

[0094] The design principles of the bypass copper pillars align with improving space utilization, achieving at least two thermal performance advantages within a compact layout. First, it provides an upward top-level heat conduction path for the chip, building upon the existing downward heat conduction path. Under the same operating conditions and with the same power semiconductor chip, the thermal resistance from the chip to the environment is significantly reduced compared to traditional power modules, resulting in lower chip temperatures and enabling the module to handle higher power levels. Second, it ensures similar heat dissipation environments and consistent thermal coupling among the parallel chips forming the bridge arm. Uniform chip temperatures during operation significantly improve the overall reliability of the power module. Specifically, consistent chip temperatures guarantee consistent output characteristics, ensuring dynamic current sharing among parallel chips. Furthermore, consistent chip temperatures ensure the reliability of the chip-substrate and bonding layer connections, preventing thermal runaway due to failure in any bonding layer. The height of the auxiliary copper pillars is the same as that of the two bypass copper pillars, primarily serving electrical connection and auxiliary mechanical support functions.

[0095] In this embodiment, each semiconductor chip has two main heat conduction paths:

[0096] One method is to dissipate heat to the bottom through the conductive metal area of ​​the bottom power substrate where the chip is located.

[0097] Secondly, heat is dissipated to the top through bypass copper pillars located in the same conductive metal region as the chip on the bottom power substrate.

[0098] The heat dissipation paths of the three parallel branches of semiconductor chips 501, 502, and 503 on the upper bridge arm are consistent. Taking the third semiconductor chip 503 as an example, the main heat conduction path of the upper bridge arm chip is explained as follows:

[0099] Please see Figure 6 The first heat conduction path 601 of the upper bridge arm semiconductor chip starts from the third semiconductor chip 503, passes longitudinally through the bottom fifth conductive area 215, the bottom insulating dielectric layer 202, and the bottom lower surface metal layer 203 in sequence, and then conducts heat to the external environment.

[0100] The second heat conduction path 602 of the upper bridge arm semiconductor chip starts from the third semiconductor chip 503, passes horizontally through the bottom fifth conductive region 215, and then vertically through the upper bridge arm bypass copper pillar 301, the top fourth conductive region 114, the top insulating dielectric layer 102 and the top upper surface metal layer 101 to conduct heat to the outside.

[0101] The lower bridge arm chip and the upper bridge arm chip have similar main heat conduction paths. Taking the fourth semiconductor chip 504 as an example, the two main heat conduction paths of the lower bridge arm chip are explained:

[0102] Please see Figure 7 The first heat conduction path 603 of the lower bridge arm semiconductor chip starts from the fourth semiconductor chip 504 and sequentially passes through the bottom third conductive region 213, the bottom insulating dielectric layer 202 and the bottom lower surface metal layer 203 to conduct heat to the external environment.

[0103] The second heat conduction path 604 of the lower bridge arm semiconductor chip starts from the fourth semiconductor chip 504, passes laterally through a local part of the bottom third conductive area 213, and then longitudinally passes through the lower bridge arm bypass copper pillar 302, the top third conductive area 113, the top insulating dielectric layer 102 and the top upper surface metal layer 101 to conduct heat to the outside.

[0104] The drive circuit includes the upper arm drive circuit and the lower arm drive circuit.

[0105] The upper arm drive circuit includes:

[0106] The upper bridge arm gate drive terminal, the bottom eighth conductive region 218 and the bottom ninth conductive region 219, the auxiliary copper pillar, the top sixth conductive region 116 and the top fifth conductive region 115, the auxiliary copper pillar, the bottom fourth conductive region 214, the gate bonding line; the source bonding line, the bottom third conductive region 213, the auxiliary copper pillar, the top third conductive region 113, the auxiliary copper pillar, the bottom seventh conductive region 217 and the bottom tenth conductive region 220, and the upper bridge arm source drive terminal.

[0107] The lower arm drive circuit specifically includes:

[0108] The lower bridge arm gate drive terminal, the top second conductive region 112, the auxiliary copper pillar, the bottom second conductive region 212, and the gate bonding line; the source bonding line, the bottom first conductive region 211, the auxiliary copper pillar, the top first conductive region 111, and the lower bridge arm source drive terminal.

[0109] Using auxiliary copper pillars allows the drive circuit to be easily connected using Kelvin connections between the gate and source leads, greatly reducing the common-source inductance and eliminating the negative impact of the power circuit on the drive circuit. This improves the current sharing effect of multiple chips and the operational reliability of the power module under different operating conditions.

[0110] Power terminals and decoupling capacitors

[0111] Please see Figure 8 and Figure 9 The DC power positive terminal 205 and DC power negative terminal 206 integrate a first coupling capacitor 701 and a second coupling capacitor 702. This compact arrangement facilitates the design of multilayer busbars to reduce the impact of parasitic inductance introduced by the power terminals on the power module, and can easily integrate decoupling capacitors, thereby further eliminating the impact of parasitic inductance introduced by external circuits of the power terminals on the power module and reducing the impact of high-frequency electromagnetic interference from the power module on other components.

[0112] This invention implements a half-bridge structure, which (can be composed of one or more structures connected in series and parallel) can form, but is not limited to, three-phase inverter full-bridge circuits, synchronous rectifiers, single-phase inverter full-bridges, and other DC-AC, DC-DC, AC-AC, and AC-DC converter circuits.

[0113] In the packaging structure of this invention, bypass copper pillars are used to provide two main heat conduction paths for each chip, as well as mechanical connections between the top and bottom power substrates, thermal connections between the chip and the top power substrate, and electrical connections, significantly reducing the thermal resistance from the chip to the environment. The position, shape, and height of the bypass copper pillars can be flexibly set according to the layout of the chip and conductive metal areas, improving space utilization.

[0114] In the packaging structure of this invention, the thermal coupling of all chips is significantly reduced, and the degree of thermal coupling between all chips is relatively uniform, thus achieving high heat transfer efficiency and uniform chip junction temperature. In the packaging structure of this invention, the heat generated by all semiconductor chips has two transfer paths, thereby significantly reducing the thermal resistance from the chip to the environment.

[0115] In summary, the present invention provides a wide bandgap power semiconductor module based on bypass copper pillar heat dissipation. The package structure can reliably operate at very high current levels and very high switching frequencies, and can also operate at chip junction temperatures of 200℃ to 350℃ (depending on the packaging material, operating environment, etc.), thereby fully leveraging the superior performance of wide bandgap power semiconductors.

[0116] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.

Claims

1. A wide-bandgap power semiconductor module based on bypass copper pillar heat dissipation, characterized in that, It includes several wide bandgap power semiconductor chips connected in series or in parallel. The wide bandgap power semiconductor chips are disposed between a top power substrate (100) and a bottom power substrate (200). The top power substrate (100) and the bottom power substrate (200) are connected by a bypass copper pillar and an auxiliary copper pillar. The wide bandgap power semiconductor chip is connected to the power circuit of the upper conductive metal region of the bottom power substrate (200) by bonding wires, and the wide bandgap power semiconductor chip is connected to the power circuit of the upper conductive metal region of the top power substrate (100) by bypass copper pillars and auxiliary copper pillars. The upper and lower bridge arms of the half-bridge structure are formed by several wide bandgap power semiconductor chips. A power terminal is provided on the upper surface of the bottom power substrate (200); a drive terminal is provided on the conductive metal area on the lower surface of the top power substrate (100) and the conductive metal area on the upper surface of the bottom power substrate (200); The upper and lower bridge arm drive terminals are arranged on opposite sides in space and are disposed on different power substrates; The top power substrate (100) includes, from top to bottom, a top upper surface metal layer (101), a top insulating dielectric layer (102), and a top lower surface metal layer (103). The top lower surface metal layer (103) is divided into several conductive regions, including a top first conductive region (111), a top second conductive region (112), a top third conductive region (113), a top fourth conductive region (114), a top fifth conductive region (115), and a top sixth conductive region (116). The top first conductive region (111) and the top second conductive region (112) are connected to the driving terminal, the top third conductive region (113) and the top fourth conductive region (114) are connected to the heat conduction path of the wide bandgap power semiconductor chip, and the top fifth conductive region (115) and the top sixth conductive region (116) are connected to the driving circuit. The bottom power substrate (200) comprises, from top to bottom, a bottom upper surface metal layer (201), a bottom insulating dielectric layer (202), and a bottom lower surface metal layer (203). The bottom upper surface metal layer (201) has a plurality of conductive regions, including a bottom first conductive region (211), a bottom second conductive region (212), a bottom third conductive region (213), a bottom fourth conductive region (214), a bottom fifth conductive region (215), a bottom sixth conductive region (216), a bottom seventh conductive region (217), a bottom eighth conductive region (218), a bottom ninth conductive region (219), and a bottom tenth conductive region (220). The bottom first conductive region (211), bottom fifth conductive region (215) and bottom sixth conductive region (216) are connected to the power terminal, the bottom second conductive region (212), bottom fourth conductive region (214), bottom seventh conductive region (217), bottom eighth conductive region (218), bottom ninth conductive region (219) and bottom tenth conductive region (220) are respectively connected to the corresponding drive circuit, and the bottom third conductive region (213) is connected to the bypass copper pillar; the wide bandgap semiconductor power chip includes a number of upper bridge arm chips disposed on the bottom fifth conductive region (215) and a number of lower bridge arm chips disposed on the bottom third conductive region (213).

2. The wide bandgap power semiconductor module based on bypass copper pillar heat dissipation according to claim 1, characterized in that, The number of upper bridge arm chips and lower bridge arm chips is the same, and the spacing between adjacent upper bridge arm chips and adjacent lower bridge arm chips is the same.

3. The wide bandgap power semiconductor module based on bypass copper pillar heat dissipation according to claim 1, characterized in that, The driving terminals include a Kelvin upper bridge arm source terminal and an upper bridge arm gate terminal disposed on the bottom upper surface metal layer (201) of the bottom power substrate (200); and a Kelvin lower bridge arm source terminal and a lower bridge arm gate terminal disposed on the top lower surface metal layer (103) of the top power substrate (100).

4. The wide bandgap power semiconductor module based on bypass copper pillar heat dissipation according to claim 1, characterized in that, The power terminals include a DC power negative terminal (206), a DC power positive terminal (205), and an AC power terminal (204) respectively disposed on the bottom upper surface metal layer (201) of the bottom power substrate (200). A first coupling capacitor (701) and a second coupling capacitor (702) are disposed between the DC power positive terminal (205) and the DC power negative terminal (206).

5. The wide bandgap power semiconductor module based on bypass copper pillar heat dissipation according to claim 1, characterized in that, The bypass copper pillars are arranged in the horizontal direction corresponding to the parallel wide bandgap semiconductor chipset, and in the vertical direction between the top power substrate (100) and the bottom power substrate (200), and are arranged on the bottom upper surface metal layer (201) of the bottom power substrate (200); there are multiple auxiliary copper pillars arranged in parallel with the bypass copper pillars.

6. The wide bandgap power semiconductor module based on bypass copper pillar heat dissipation according to claim 1, characterized in that, The upper bridge arm has a first heat conduction path (601) and a second heat conduction path (602) at the wide bandgap power semiconductor chip. One end of the first heat conduction path (601) is connected to the wide bandgap power semiconductor chip, and the other end passes sequentially through the conductive region of the bottom upper surface metal layer (201) of the bottom power substrate (200), the bottom insulating dielectric layer (202) of the bottom power substrate (200), and the bottom lower surface metal layer of the bottom power substrate (200). Layer (203) conducts heat; one end of the second heat conduction path (602) of the upper bridge arm semiconductor chip is connected to the wide bandgap power semiconductor chip, and the other end passes laterally through the conductive area of ​​the bottom upper surface metal layer (201) on the bottom power substrate (200), and then longitudinally passes through the bypass copper pillar, the conductive area of ​​the top lower surface metal layer (103), the top insulating dielectric layer (102) of the top power substrate (100), and the top upper surface metal layer (101) of the top power substrate (100) to conduct heat to the outside. A first heat conduction path (603) and a second heat conduction path (604) are provided at the wide bandgap power semiconductor chip at the lower bridge arm. One end of the first heat conduction path (603) is connected to the wide bandgap power semiconductor chip, and the other end passes longitudinally through the conductive area at the bottom upper surface metal layer (201) of the bottom power substrate (200), the bottom insulating dielectric layer (202) of the bottom power substrate (200), and the bottom lower surface metal layer (204) of the bottom power substrate (200). 3) Conducting heat outward; One end of the second heat conduction path (604) of the lower bridge arm semiconductor chip is connected to the wide bandgap power semiconductor chip, and the other end passes laterally through the conductive area at the bottom upper surface metal layer (201) of the bottom power substrate (200), and then sequentially passes longitudinally through the bypass copper pillar, the conductive area at the top lower surface metal layer (103) of the top power substrate (100), the top insulating dielectric layer (102) of the top power substrate (100), and the top upper surface metal layer (101) of the top power substrate (100) to conduct heat outward.

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