Grooved-gate power device and manufacturing method thereof

Abstract

The present invention discloses a trench gate power device. The gate trench is formed by superimposing a top trench and a bottom trench, and the width of the top trench is greater than that of the bottom trench; a trench gate is formed in the bottom trench; a channel region and a source region are formed in the epitaxial layer; the source region is located on the surface of the channel region; the gate conductive material layer passes through the channel region; a top dielectric layer is filled in the top trench at the top of the gate conductive material layer; the source region is connected to the source electrode through a first contact hole; the first contact hole passes through the source region and is in contact with the channel region; the first contact hole is shared by two adjacent device units, and the bottom width of the first contact hole is defined by self-alignment with the spacing of the top dielectric layers in two adjacent gate trenches. The present invention also discloses a manufacturing method of a trench gate power device. The present invention can self-align and define the source contact hole, which is beneficial to reducing the size of the source contact hole and can reduce the size of the source contact hole to be smaller than the minimum size required by the lithography process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a trench gate power device; the present invention also relates to a method for manufacturing a trench gate power device. Background Art

[0002] The gate structure of a trench gate power device adopts a trench gate, and the trench gate includes a gate dielectric layer and a gate conductive material layer formed in the gate trench. The gate dielectric layer usually adopts a gate oxide layer, and the gate conductive material layer usually adopts a polysilicon gate.

[0003] In a trench gate (SGT) power device with a shield gate, a source conductive material layer is further formed in the gate trench. The source conductive material layer is located on top of the gate conductive material layer and usually adopts source polysilicon. The source conductive material layer is connected to the source composed of a front metal layer through a contact hole. The source conductive material layer can further improve the breakdown voltage of the device and reduce the drift region resistance.

[0004] In a trench gate power device, the trench gate penetrates through the channel region, and the source region is formed on the surface of the channel region.

[0005] The gate conductive material layer is connected to the gate composed of a front metal layer through a contact hole. The contact holes of the source conductive material layer and the gate conductive material layer are usually arranged in the peripheral area of the device cell region.

[0006] The device cell region includes a plurality of parallel device cells, i.e., cells. Each device cell has a gate trench, and the width and pitch of the gate trench are the step of the cell. The same source region often serves two adjacent cells. At the top of the source region, it is connected to the source through a contact hole, i.e., a source contact hole. With the progress of technology, as the size of the device becomes smaller and smaller, the step of the cell will become smaller and smaller, and the size of the contact hole at the top of the source region, such as the width, will become smaller and smaller, and the distance between the contact hole and the gate conductive material layers on both sides will also become smaller and smaller. Thus, the requirements for contact hole lithography in device design will become higher and higher. Existing trench gate power devices, such as trench gate MOSFETs, have the following problems:

[0007] For existing trench gate MOSFETs, generally speaking, when the width of the contact hole is less than 0.2 μm, the requirements for device design and lithography technology will increase significantly.

[0008] Expensive lithography machines and high-standard lithography alignment deviations are important considerations for device design. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a trench gate power device that can self-align and define source contact holes, which is beneficial to reducing the size of the source contact holes and can reduce the size of the source contact holes to be smaller than the minimum size required by the lithography process, and finally utilize the size reduction of the device. For this purpose, the present invention also provides a manufacturing method of a trench gate power device.

[0010] To solve the above technical problem, the device unit area of the trench gate power device provided by the present invention includes a plurality of parallel device units, and each of the device units includes:

[0011] A gate trench formed in an epitaxial layer of a first conductivity type, which is formed by superimposing a top trench and a bottom trench, and the width of the top trench is greater than the width of the bottom trench.

[0012] A trench gate is formed in the bottom trench, and the trench gate includes a gate conductive material layer filled in the bottom trench and a gate dielectric layer located between the gate conductive material layer and the side surface of the bottom trench.

[0013] A bottom dielectric layer is isolated between the gate conductive material layer and the bottom surface of the bottom trench.

[0014] A channel region doped with a second conductivity type and a source region heavily doped with a first conductivity type are formed in the epitaxial layer.

[0015] The source region is located on the surface of the channel region.

[0016] In the longitudinal direction, the gate conductive material layer passes through the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel.

[0017] A top dielectric layer is filled in the top trench on the top of the gate conductive material layer.

[0018] The source region is connected to a source electrode composed of a front metal layer through a first contact hole.

[0019] The first contact hole passes through the source region and contacts the channel region.

[0020] The first contact hole is shared by two adjacent device units, and the bottom width of the first contact hole is self-aligned and defined by the spacing of the top dielectric layers in two adjacent gate trenches.

[0021] A further improvement is that the trench-gate power device is a trench-gate power device with a shield gate, and a source conductive material layer is further formed in the bottom trench. The source conductive material layer is located at the bottom of the gate conductive material layer, and an intermediate dielectric layer is isolated between the gate conductive material layer and the source conductive material layer; a bottom dielectric layer is isolated between the source conductive material layer and the inner surface of the bottom trench.

[0022] A further improvement is that the trench-gate power device is a trench-gate MOSFET.

[0023] A heavily doped drain region of the first conductivity type is formed at the bottom of the epitaxial layer.

[0024] A drift region is composed of the epitaxial layer between the channel region and the drain region.

[0025] A back metal layer is formed on the back surface of the drain region and the drain is composed of the back metal layer.

[0026] A further improvement is that the minimum value of the bottom width of the first contact hole reaches below 0.2 micrometers.

[0027] A further improvement is that the top dielectric layer includes an oxide layer.

[0028] A further improvement is that the epitaxial layer is formed on the surface of the semiconductor substrate.

[0029] The semiconductor substrate has a heavy doping of the first conductivity type, and the drain region is composed of the semiconductor substrate after back thinning; or, the drain region is composed of a back ion implantation region formed by performing a first conductivity type heavy doping back ion implantation on the basis of the semiconductor substrate after back thinning.

[0030] A further improvement is that the material of the gate conductive material layer includes polysilicon, and the material of the source conductive material layer includes polysilicon; a metal silicide is formed on the polysilicon surface of the gate conductive material layer.

[0031] A further improvement is that there is a source conductive material layer lead-out region outside the device unit region. The gate trench and the source conductive material layer are also formed in the source conductive material layer lead-out region; in the source conductive material layer lead-out region, the bottom trench at the top of the source conductive material layer is filled with a protective dielectric layer and the top trench is filled with the top dielectric layer.

[0032] The source conductive material layer in the device unit region is connected to the source conductive material layer in the source conductive material layer lead-out region and is connected to the source through a second contact hole formed at the top of the source conductive material layer in the source conductive material layer lead-out region.

[0033] A further improvement is that an ohmic contact region composed of a heavily doped region of the second conductivity type is further formed at the bottom of the first contact hole.

[0034] A further improvement is that the semiconductor substrate includes a silicon substrate, and the epitaxial layer includes a silicon epitaxial layer.

[0035] To solve the above technical problems, the manufacturing method of the trench-gate power device provided by the present invention includes the following steps:

[0036] Step 1: Form a gate trench formed by superimposing a bottom trench and a top trench in an epitaxial layer of the first conductivity type, where the width of the top trench is greater than the width of the bottom trench.

[0037] The device unit region includes a plurality of parallel device units, and each device unit includes one of the gate trenches.

[0038] Step 2: Form a trench gate, including:

[0039] Form a bottom dielectric layer on the bottom surface of the bottom trench and form a gate dielectric layer on the side surface of the bottom trench.

[0040] Form a gate conductive material layer to fill the bottom trench.

[0041] Step 3: Perform ion implantation of the second conductivity type to form a channel region in the epitaxial layer; longitudinally, the gate conductive material layer passes through the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel.

[0042] Step 4: Perform heavy doping ion implantation of the first conductivity type to form a source region in the epitaxial layer on the surface of the channel region.

[0043] Step 5: Fill the top trench with a top dielectric layer.

[0044] Step 6: Form an interlayer film, contact holes, and a front metal layer, and pattern the front metal layer to form a source electrode and a gate electrode.

[0045] The formation process of the contact hole includes: performing etching to form an opening of the contact hole, and filling the opening of the contact hole with metal to form the contact hole.

[0046] The source region is connected to the source electrode through a first contact hole that passes through the source region and contacts the channel region, and the first contact hole is shared by two adjacent device units; during the etching process of the opening of the first contact hole, the bottom opening of the first contact hole is formed by etching the epitaxial layer with the top dielectric layer in two adjacent gate trenches as the self-alignment condition, and the bottom opening of the first contact hole passes through the source region and exposes the channel region.

[0047] A further improvement is that step one includes the following sub-steps:

[0048] Step 11: Form a first hard mask layer on the surface of the epitaxial layer and pattern the first hard mask layer. After patterning, the first hard mask layer opens the formation region of the top trench and covers the outside of the formation region of the top trench.

[0049] Step 12: Etch the epitaxial layer using the first hard mask layer as a mask to form the top trench.

[0050] Step 13: Form a second hard mask layer on the inner surface of the top trench and pattern the second hard mask layer. After patterning, the second hard mask layer opens the formation region of the bottom trench and covers the inner surface of the top trench outside the formation region of the bottom trench; the formation region of the bottom trench is located in the top trench and the width of the formation region of the top trench is smaller than the width of the top trench.

[0051] Step 14: Etch the epitaxial layer using the first hard mask layer and the second hard mask layer as masks to form the bottom trench at the bottom of the top trench.

[0052] A further improvement is that the trench-gate power device is a trench-gate power device with a shield gate; in step two, a shield gate needs to be formed before forming the trench gate, and step two includes the following sub-steps:

[0053] Form the bottom dielectric layer on the bottom surface and side surface of the bottom trench.

[0054] Form a source electrode conductive material layer in the bottom region of the bottom trench.

[0055] Form an intermediate dielectric layer on the surface of the source electrode conductive material layer.

[0056] Remove the bottom dielectric layer on the side surface of the bottom trench at the top of the intermediate dielectric layer.

[0057] Form the gate dielectric layer on the side surface of the bottom trench at the top of the intermediate dielectric layer.

[0058] Form the gate conductive material layer in the bottom trench.

[0059] A further improvement is that the trench gate power device is a trench gate MOSFET; after step six, the following backside process is further included:

[0060] The epitaxial layer is formed on the surface of the semiconductor substrate.

[0061] The semiconductor substrate has a heavily doped first conductivity type. Thinning the backside of the semiconductor substrate, and directly forming the drain region by the thinned semiconductor substrate; or, thinning the backside of the semiconductor substrate, and performing backside ion implantation of the first conductivity type heavy doping to form the drain region.

[0062] Form a backside metal layer on the backside of the drain region and form the drain electrode by the backside metal layer.

[0063] A further improvement is that the minimum value of the bottom width of the first contact hole reaches below 0.2 micrometers.

[0064] A further improvement is that the top dielectric layer includes an oxide layer.

[0065] A further improvement is that the material of the gate conductive material layer includes polysilicon, and the material of the source conductive material layer includes polysilicon.

[0066] After forming the gate conductive material layer in the bottom trench, a step of forming a metal silicide on the polysilicon surface of the gate conductive material layer is further included.

[0067] A further improvement is that there is a source conductive material layer lead-out region outside the device cell region.

[0068] In step one, the gate trench is also formed in the source conductive material layer lead-out region.

[0069] In step two, in the source conductive material layer lead-out region, after forming the source conductive material layer, the gate trench on the top of the source conductive material layer is filled with a protective dielectric layer.

[0070] After forming the gate conductive material layer in the device cell region, the protective dielectric layer in the top trench, the second hard mask layer, and the first hard mask layer outside the gate trench are removed.

[0071] In step six, in the formation process of the contact hole, a step of forming a second contact hole on the top of the source conductive material layer in the source conductive material layer lead-out region is included.

[0072] A further improvement is that in step six, after the bottom opening of the first contact hole is formed, it further includes a step of performing a second-conductivity-type heavy doping implantation to form an ohmic contact region.

[0073] A further improvement is that the semiconductor substrate includes a silicon substrate, and the epitaxial layer includes a silicon epitaxial layer.

[0074] In the present invention, the gate trench is divided into a top trench and a bottom trench, and the width of the top trench is set to be greater than the width of the bottom trench. The trench gate is disposed in the bottom trench, and the top trench is filled with a top dielectric layer. In this way, the bottom region of the source contact hole, i.e., the first contact hole, in the device cell region can be self-alignedly defined by the top dielectric layers in two adjacent top trenches. The bottom region of the first contact hole is a region passing through the epitaxial layer. Since the materials of the top dielectric layer and the epitaxial layer are different, the epitaxial layer can be etched under the self-aligned definition of the top dielectric layer to form the bottom region of the first contact hole. Therefore, the present invention can self-align and define the source contact hole, which is beneficial to reducing the size of the source contact hole and can reduce the size of the source contact hole to be smaller than the minimum size required by the lithography process, such as 2 microns, and finally utilize the reduction of the device size.

[0075] Since the source contact hole of the present invention is formed by self-alignment, compared with the prior art that defines the source contact hole by lithography process, the present invention does not require very high requirements for the lithography machine equipment, can save costs, and thus can improve the minimum contact hole lithography alignment error. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The present invention will be further described in detail below with reference to the drawings and specific embodiments:

[0077] Figure 1 is a schematic structural diagram of a trench gate power device according to an embodiment of the present invention;

[0078] Figures 2A - 2Q is a schematic structural diagram of the device in each step of the manufacturing method of the trench gate power device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0079] As Figure 1 shown, it is a schematic structural diagram of a trench gate power device according to an embodiment of the present invention; The device cell region of the trench gate power device according to the embodiment of the present invention includes a plurality of parallel device cells, and each of the device cells includes:

[0080] A gate trench formed in an epitaxial layer 2 of a first conductivity type, which is formed by superimposing a top trench 3 and a bottom trench 4, and the width of the top trench 3 is greater than the width of the bottom trench 4. Figure 1 Two device cells are shown in

[0081] In an embodiment of the present invention, the epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. Preferably, the semiconductor substrate 1 includes a silicon substrate, and the epitaxial layer 2 includes a silicon epitaxial layer 2.

[0082] A trench gate is formed in the bottom trench 4. The trench gate includes a gate conductive material layer 9 filled in the bottom trench 4 and a gate dielectric layer 8 located between the gate conductive material layer 9 and the side surface of the bottom trench 4.

[0083] A bottom dielectric layer 5 is isolated between the gate conductive material layer 9 and the bottom surface of the bottom trench 4.

[0084] A channel region 11 doped with a second conductivity type and a source region 12 heavily doped with a first conductivity type are formed in the epitaxial layer 2.

[0085] The source region 12 is located on the surface of the channel region 11.

[0086] In the longitudinal direction, the gate conductive material layer 9 passes through the channel region 11, and the surface of the channel region 11 covered by the side surface of the gate conductive material layer 9 is used to form a conductive channel.

[0087] A top dielectric layer 13 is filled in the top trench 3 on the top of the gate conductive material layer 9.

[0088] The source region 12 is connected to a source electrode composed of a front metal layer 17 through a first contact hole 15.

[0089] The first contact hole 15 passes through the source region 12 and contacts the channel region 11.

[0090] The first contact hole 15 is shared by two adjacent device units, and the bottom width of the first contact hole 15 is defined by self-alignment with the spacing of the top dielectric layers 13 in the two adjacent gate trenches. Figure 1 The cross-sectional view only shows the formation region of the first contact hole 15; generally, in the top view, the first contact hole 15 is only provided in a partial region of the source region 12, and the top view structure of the first contact hole 15 is a small block structure.

[0091] In the embodiment of the present invention, the trench gate power device is a trench gate power device with a shield gate. An anode conductive material layer 6 is further formed in the bottom trench 4. The anode conductive material layer 6 is located at the bottom of the gate conductive material layer 9, and an intermediate dielectric layer 7 is isolated between the gate conductive material layer 9 and the anode conductive material layer 6; a bottom dielectric layer 5 is isolated between the anode conductive material layer 6 and the inner surface of the bottom trench 4. That is, in the embodiment of the present invention, due to the setting of the anode conductive material layer 6, the gate conductive material layer 9 does not directly contact the bottom dielectric layer 5, but the anode conductive material layer 6 directly contacts the bottom dielectric layer 5. In other embodiments, if the shield gate is not provided, both the anode conductive material layer 6 and the intermediate dielectric layer 7 can be cancelled.

[0092] In the embodiment of the present invention, the trench gate power device is a trench gate MOSFET.

[0093] A drain region with a first conductivity type heavily doped is formed at the bottom of the epitaxial layer 2. The semiconductor substrate 1 has a first conductivity type heavily doped, and the drain region is composed of the semiconductor substrate 1 after back thinning; alternatively, the drain region is composed of a backside ion implantation region formed by performing a first conductivity type heavy doping on the semiconductor substrate 1 after back thinning by backside ion implantation.

[0094] The drift region is composed of the epitaxial layer 2 between the channel region 11 and the drain region.

[0095] A back metal layer is formed on the back of the drain region and the drain electrode is composed of the back metal layer.

[0096] The minimum value of the bottom width of the first contact hole 15 reaches less than 0.2 micrometers, that is, the bottom width of the first contact hole 15 in the embodiment of the present invention can be less than the minimum value that can be achieved by the lithography process equipment.

[0097] The material of the gate conductive material layer 9 includes polysilicon, and the material of the anode conductive material layer 6 includes polysilicon; a metal silicide 10 is formed on the polysilicon surface of the gate conductive material layer 9.

[0098] The top dielectric layer 13 includes an oxide layer.

[0099] The bottom dielectric layer 5 includes an oxide layer.

[0100] The gate dielectric layer 8 includes an oxide layer.

[0101] The intermediate dielectric layer 7 includes an oxide layer.

[0102] An ohmic contact region 16 composed of a second conductivity type heavily doped region is further formed at the bottom of the first contact hole 15.

[0103] There is a source conductive material layer lead-out region outside the device unit region, and the gate trench and the source conductive material layer 6a are also formed in the source conductive material layer lead-out region. Figure 1 The source conductive material layer in the source conductive material layer lead-out region is separately marked with 6a. In the source conductive material layer lead-out region, the bottom trench 4 at the top of the source conductive material layer 6a is filled with a protective dielectric layer and the top trench 3 is filled with the top dielectric layer 13. The protective dielectric layer includes an oxide layer, which can be deposited by the same oxide layer deposition process as the intermediate dielectric layer 7, such as high-density plasma (HDP) chemical vapor deposition (CVD) process, and is separately etched after deposition.

[0104] The source conductive material layer 6 in the device unit region is connected to the source conductive material layer 6 in the source conductive material layer lead-out region and is connected to the source through a second contact hole formed at the top of the source conductive material layer 6 in the source conductive material layer lead-out region.

[0105] The gate conductive material layer 9 generally also extends outside the device unit region and is connected to the gate composed of the front metal layer 17 through a third contact hole formed at the top of the gate conductive material layer 9 outside the device unit region.

[0106] The first contact hole 15, the second contact hole, and the third contact hole all pass through the interlayer film 14.

[0107] Now, the device of the embodiment of the present invention will be further described with specific parameters:

[0108] The device of the embodiment of the present invention is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments, it can also be a P-type device. At this time, the first conduction type is P-type and the second conduction type is N-type.

[0109] The semiconductor substrate 1 is highly doped, i.e., N+ doped. The doping of the semiconductor substrate 1 can be phosphorus or arsenic, and the resistivity of the semiconductor substrate 1 is 0.001 - 0.003 ohm·cm; among them, in low-voltage devices, a red phosphorus substrate can be used, and at this time, the resistivity can be less than 0.0017 ohm·cm.

[0110] The doping impurity of the epitaxial layer 2 is phosphorus or arsenic. The resistivity and thickness of the epitaxial layer 2 are selected according to the structure of the device and the breakdown voltage of the device. In a device with a breakdown voltage of 40V - 60V, the resistivity of the epitaxial layer 2 is 0.1 ohm·cm - 0.15 ohm·cm, and the thickness of the epitaxial layer 2 is 3 μm - 5 μm.

[0111] The contact holes, including the first contact hole 15, the second contact hole, and the third contact hole, are formed by filling metal in the openings of the contact holes. The metal filled in the contact holes includes W; the metal of the front metal layer 17 includes AlCu. Additionally, the metal filled in the contact holes and the metal of the front metal layer 17 can also use the same metal layer, as long as it can be filled into the openings of the contact holes and a good ohmic contact can be formed in the device area; if there is also a Schottky region, a good Schottky contact can be formed between the bottom of the contact hole and the silicon substrate in the Schottky region.

[0112] In the embodiment of the present invention, the gate trench is divided into a top trench 3 and a bottom trench 4, and the width of the top trench 3 is set to be greater than the width of the bottom trench 4. The trench gate is disposed in the bottom trench 4, and the top trench 3 is filled with a top dielectric layer 13. In this way, the bottom region of the source contact hole, i.e., the first contact hole 15, in the device cell area can be self-alignedly defined by the top dielectric layers 13 in two adjacent top trenches 3. The bottom region of the first contact hole 15 is the region passing through the epitaxial layer 2. Since the materials of the top dielectric layer 13 and the epitaxial layer 2 are different, the epitaxial layer 2 can be etched under the self-alignment definition of the top dielectric layer 13 to form the bottom region of the first contact hole 15. Therefore, the embodiment of the present invention can self-align and define the source contact hole, which is beneficial to reducing the size of the source contact hole and can reduce the size of the source contact hole to be smaller than the minimum size required by the lithography process, such as 2 microns, and finally, the size of the device is reduced by using this.

[0113] Since the source contact hole in the embodiment of the present invention is formed by self-alignment, compared with the prior art that uses the lithography process to define the source contact hole, the embodiment of the present invention does not require a very high requirement for the lithography machine equipment, can save costs, and thus can improve the minimum contact hole lithography alignment error.

[0114] As Figures 2A through 2Q shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the trench gate power device according to the embodiment of the present invention; the manufacturing method of the trench gate power device according to the embodiment of the present invention includes the following steps:

[0115] Step 1: Form a gate trench formed by superimposing a bottom trench 4 and a top trench 3 in the epitaxial layer 2 of the first conductivity type, and the width of the top trench 3 is greater than the width of the bottom trench 4.

[0116] The device cell area includes a plurality of parallel device cells, and each device cell includes one of the gate trenches.

[0117] Step 1 includes the following sub-steps:

[0118] Step 11: As Figure 2AAs shown, the epitaxial layer 2 is provided, and the epitaxial layer 2 is formed on the surface of the semiconductor substrate 1. Preferably, the semiconductor substrate 1 includes a silicon substrate, and the epitaxial layer 2 includes a silicon epitaxial layer 2.

[0119] In the method of the embodiment of the present invention, the device is an N-type device, the first conduction type is N-type, and the second conduction type is P-type. In other embodiments, it can also be a P-type device. At this time, the first conduction type is P-type, and the second conduction type is N-type.

[0120] The semiconductor substrate 1 is highly doped, i.e., N+ doped. The doping of the semiconductor substrate 1 can be phosphorus or arsenic, and the resistivity of the semiconductor substrate 1 is 0.001 - 0.003 ohm·cm; among them, in low-voltage devices, a red phosphorus substrate can be used, and at this time, the resistivity can be less than 0.0017 ohm·cm.

[0121] The doping impurity of the epitaxial layer 2 is phosphorus or arsenic. The resistivity and thickness of the epitaxial layer 2 are selected according to the structure of the device and the breakdown voltage of the device. In a device of 40V - 60V, the resistivity of the epitaxial layer 2 is 0.1 ohm·cm - 0.15 ohm·cm, and the thickness of the epitaxial layer 2 is 3 μm - 5 μm.

[0122] As Figure 2B shown, a first hard mask layer is formed on the surface of the epitaxial layer 2.

[0123] As Figure 2C shown, the first hard mask layer is patterned. After patterning, the first hard mask layer opens the formation region of the top trench 3 and covers the outside of the formation region of the top trench 3.

[0124] In the embodiment of the present invention, the first hard mask layer is composed of an oxide layer 101 and a nitride layer 102 stacked. The thickness of the oxide layer 101 is 50nm - 150nm, and the thickness of the nitride layer 102 can be 150nm.

[0125] Step 12, as Figure 2C shown, using the first hard mask layer as a mask, the epitaxial layer 2 is etched to form the top trench 3.

[0126] In the embodiment of the present invention, the top trench 3 is formed by wet etching. The width of the top trench 3 is about 1.0 μm, and the depth is about 0.3 μm - 0.5 μm.

[0127] Step 13, as Figure 2D shown, a second hard mask layer is formed on the inner surface of the top trench 3.

[0128] In the embodiment of the present invention, the second hard mask layer is composed of an oxide layer 103 and a nitride layer 104 stacked.

[0129] As shown Figure 2E in the figure, the second hard mask layer is patterned. After patterning, the second hard mask layer opens the formation region of the bottom trench 4 and covers the inner surface of the top trench 3 outside the formation region of the bottom trench 4; the formation region of the bottom trench 4 is located in the top trench 3 and the width of the formation region of the top trench 3 is smaller than the width of the top trench 3.

[0130] Step 14, as Figure 2F shown in the figure, using the first hard mask layer and the second hard mask layer as masks, the epitaxial layer 2 is etched to form the bottom trench 4 at the bottom of the top trench 3.

[0131] The bottom trench 4 is a deep trench. After the etching of the bottom trench 4 is completed, a sacrificial oxide layer growth and removal process is usually performed to eliminate the defects on the inner surface of the bottom trench 4.

[0132] Step two, forming a trench gate, includes:

[0133] Forming a bottom dielectric layer 5 on the bottom surface of the bottom trench 4 and forming a gate dielectric layer 8 on the side surface of the bottom trench 4.

[0134] Forming a gate conductive material layer 9 to fill the bottom trench 4.

[0135] In the method of the embodiment of the present invention, the trench gate power device is a trench gate power device with a shield gate; before forming the trench gate in step two, a step of forming a shield gate is further included; thus, the entire step two includes the following sub-steps:

[0136] As Figure 2F shown in the figure, forming the bottom dielectric layer 5 on the inner surface of the bottom trench 4. In the method of the embodiment of the present invention, the bottom dielectric layer 5 is an oxide layer and is formed by an oxide layer growth process.

[0137] As Figure 2G shown in the figure, forming a source conductive material layer 6 in the bottom region of the bottom trench 4. In the method of the embodiment of the present invention, the source conductive material layer 6 is made of polysilicon. The step of forming the source conductive material layer 6 includes: depositing polysilicon to fill the trench, then planarizing the polysilicon on the surface by CMP, and then removing the excess polysilicon by wet etching.

[0138] There is a source conductive material layer lead-out region outside the device cell region. In step one, the gate trench is also formed in the source conductive material layer lead-out region. In step two, a source conductive material layer 6a is also formed in the source conductive material layer lead-out region at the same time. Figure 2GAmong them, the source conductive material layer formed in the source conductive material layer lead-out area is separately marked with 6a.

[0139] After that, an intermediate dielectric layer 7 is formed on the surface of the source conductive material layer 6. The intermediate dielectric layer 7 is composed of an oxide layer. Combining the structure in the source conductive material layer lead-out area, that is, the subsequent trench gate formation process is not required in the source conductive material layer lead-out area. The formation of the intermediate dielectric layer 7 includes the following sub-steps:

[0140] As Figure 2H shown, an oxide layer 105 is formed to completely fill the gate trench on the top of the source conductive material layers 6 and 6a. Preferably, the oxide layer 105 is formed by the HDPCVD process, and then the surface oxide layer 105 is polished flat by the chemical mechanical polishing process (CMP).

[0141] As Figure 2I shown, an oxide layer 106 is formed. The thickness of the oxide layer 106 is 100 nm to 200 nm, and the thickness depends on the amount of undercut of the oxide layer next. To ensure the protection of the source conductive material layer lead-out area.

[0142] As Figure 2J shown, a photoresist pattern 107 is formed to open the device cell area and cover the source conductive material layer lead-out area.

[0143] The oxide layer 106 in the device cell area is removed and the oxide layer 105 in the gate trench is etched to form the intermediate dielectric layer 7. After the oxide layer 106 is etched, an undercut will be formed at the bottom of the photoresist pattern 107. The thickness of the intermediate dielectric layer 7 is greater than 300 nm.

[0144] In this way, the formation process of the intermediate dielectric layer 7 is completed, and at the same time, the protection of the source conductive material layer lead-out area is realized; that is, in the source conductive material layer lead-out area, after the source conductive material layer 6 is formed, the gate trench on the top of the source conductive material layer 6 is filled with a protective dielectric layer, and the protective dielectric layer is composed of the oxide layer 105.

[0145] Continue with the following process:

[0146] As Figure 2J shown, the bottom dielectric layer 5 on the side of the bottom trench 4 on the top of the intermediate dielectric layer 7 is removed.

[0147] As Figure 2K shown, the photoresist pattern 107 is removed. A gate dielectric layer 8 is formed on the side of the bottom trench 4 on the top of the intermediate dielectric layer 7.

[0148] As shown Figure 2L In the bottom trench 4, the gate conductive material layer 9 is formed. The gate conductive material layer 9 is made of polysilicon and is formed by polysilicon deposition and etching processes.

[0149] In the method of the embodiment of the present invention, as shown Figure 2M On the top of the gate conductive material layer 9, a metal silicide 10 is also formed.

[0150] After the gate conductive material layer 9 in the device unit area is formed, the protective dielectric layer and the second hard mask layer in the top trench 3 and the first hard mask layer outside the gate trench are removed. As shown Figure 2N The oxide layer 101 and nitride layer 102 of the first hard mask layer, the oxide layer 103 and nitride layer 104 of the second hard mask layer, the oxide layer 106 and the oxide layer 105 in the top trench 3 are all removed. The oxide layer 105 in the bottom trench remains and serves as the protective dielectric layer.

[0151] Step three: As shown Figure 2N Before performing subsequent ion implantation into the channel region 11 and the source region 12, an oxide layer 108 is formed first.

[0152] As shown Figure 2O Second-conductivity-type ion implantation is performed to form a channel region 11 in the epitaxial layer 2. In the longitudinal direction, the gate conductive material layer 9 passes through the channel region 11, and the surface of the channel region 11 covered by the side of the gate conductive material layer 9 is used to form a conductive channel.

[0153] The implantation energy of the channel region 11 needs to be set, taking into account not passing through the oxide layer 108 and implanting into other regions, and only forming the channel region 11 at the bottom of the top trench 3.

[0154] The thickness of the channel region 11 needs to be achieved through ion implantation and subsequent thermal process diffusion. This channel region 11 needs to withstand voltage when the device is reverse-biased.

[0155] Step four: As shown Figure 2O First-conductivity-type heavy-doped ion implantation is performed to form a source region 12 in the epitaxial layer 2 on the surface of the channel region 11.

[0156] In the method of the embodiment of the present invention, the device is an N-type device, the first conductivity type is N-type, the ion implantation impurity of the source region 12 is phosphorus or arsenic, and the dose is generally several E15 cm -2 .

[0157] Step five: As shown Figure 2PAs shown, the oxide layer 108 is removed. After that, the top trench 3 is filled with a top dielectric layer 13. In the method according to an embodiment of the present invention, the top dielectric layer 13 is an oxide layer; the forming process can include: forming an oxide layer to fill the gate trench, then planarizing the oxide layer on the surface by CMP, and then removing the excess oxide layer by wet etching. The height of the oxide layer should be slightly lower than the device surface.

[0158] Step Six: Form an interlayer dielectric 14, contact holes, and a front metal layer 17, and pattern the front metal layer 17 to form a source electrode and a gate electrode.

[0159] The forming process of the contact holes includes: etching to form the openings of the contact holes, and filling the openings of the contact holes with metal to form the contact holes.

[0160] The source region 12 is connected to the source electrode through a first contact hole 15. The first contact hole 15 passes through the source region 12 and contacts the channel region 11. The first contact hole 15 is shared by two adjacent device units; during the etching process of the opening of the first contact hole 15, the bottom opening of the first contact hole 15 is etched through the epitaxial layer 2 with the top dielectric layer 13 in two adjacent gate trenches as the self-alignment condition, and the bottom opening of the first contact hole 15 passes through the source region 12 and exposes the channel region 11.

[0161] In the method according to an embodiment of the present invention, the bottom opening of the first contact hole 15 is formed before the interlayer dielectric 14 is formed, as Figure 2Q shown, etching the epitaxial layer 2 with the top dielectric layer 13 in two adjacent gate trenches as the self-alignment condition to form the bottom opening of the first contact hole 15. The minimum value of the bottom width of the first contact hole 15 reaches less than 0.2 micrometers. After the bottom opening of the first contact hole 15 is formed, it further includes the step of performing a second conductive type heavy doping implantation to form an ohmic contact region 16.

[0162] As Figure 1 shown, after that, the interlayer dielectric 14 is formed, and then the etching of the openings of the subsequent contact holes is performed, including the etching of the top opening of the first contact hole 15, the second contact hole, and the third contact hole.

[0163] After that, the openings of the contact holes are filled with metal, which generally includes: depositing Ti / TiN and W to fill the openings of the contact holes, and then back-etching to remove W.

[0164] After that, the front metal layer 17 is formed, which generally includes: depositing metal AlCu, and then forming the source electrode and the gate electrode of the device through photolithography and etching.

[0165] In other embodiments of the method, the opening of the contact hole can also be directly filled with the front metal layer 17, as long as it can be filled into the opening of the contact hole and a good ohmic contact can be formed in the device area; and a good Schottky contact can be formed with the silicon substrate in the Schottky area.

[0166] The second contact hole is located on the top of the source conductive material layer 6a in the lead-out area of the source conductive material layer and contacts the source conductive material layer 6a and is used to connect the source conductive material layer 6a to the source.

[0167] The third contact hole is generally located outside the device cell area and contacts the gate conductive material layer 9 extending outside the device cell area and is connected to the gate.

[0168] The trench gate power device is a trench gate MOSFET; the following back-end process is further included after step six:

[0169] The semiconductor substrate 1 has a heavily doped first conductivity type. The semiconductor substrate 1 is back-thinned, and the back-thinned semiconductor substrate 1 directly forms the drain region; or, the semiconductor substrate 1 is back-thinned, and a back ion implantation of the first conductivity type is performed to form the drain region.

[0170] A back metal layer is formed on the back of the drain region and the drain is formed by the back metal layer.

[0171] The method of the embodiment of the present invention can realize the manufacture of the device through 7 photolithographies, including: Figure 2C The photolithography process corresponding to the top trench 3; Figure 2E The photolithography process corresponding to the bottom trench 4; Figure 2G The photolithography process corresponding to the source conductive material layer 6; Figure 2J The photolithography process corresponding to the protective oxide layer; Figure 2O The photolithography process corresponding to the source region 12; Figure 2Q The photolithography process for the opening etching of the contact hole afterwards; Figure 1 The photolithography process of the front metal layer 17 in. Compared with the prior art, Figure 2C One more photolithography layout needs to be added, but finally a self-aligned source contact hole can be formed in the device wafer, so as to meet the requirement of further reducing the device size. The embodiment of the present invention realizes the requirement of a source contact hole less than 0.2 um through a self-alignment technique on a traditional lithography machine, so that the device size can be further reduced, and a new research direction is developed for the future new generation of integrated circuits.

[0172] The present invention has been described in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A trench-gate power device, characterized in that, The device unit region includes a plurality of device units connected in parallel, and each of the device units includes: A gate trench formed in an epitaxial layer of a first conductivity type, which is formed by superimposing a top trench and a bottom trench, and the width of the top trench is greater than the width of the bottom trench; A trench gate is formed in the bottom trench, and the trench gate includes a gate conductive material layer filled in the bottom trench and a gate dielectric layer located between the gate conductive material layer and the side surface of the bottom trench; A bottom dielectric layer is isolated between the gate conductive material layer and the bottom surface of the bottom trench; A channel region doped with a second conductivity type and a source region heavily doped with a first conductivity type are formed in the epitaxial layer; The source region is located on the surface of the channel region; Longitudinally, the gate conductive material layer passes through the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel; A top dielectric layer is filled in the top trench on the top of the gate conductive material layer; The source region is connected to a source electrode composed of a front metal layer through a first contact hole; The first contact hole passes through the source region and contacts the channel region; The first contact hole is shared by two adjacent device units, and the bottom width of the first contact hole is defined by self-alignment with the spacing between the top dielectric layers in two adjacent gate trenches.

2. The trench-gate power device according to claim 1, characterized in that: The trench gate power device is a trench gate power device with a shield gate. An anode conductive material layer is further formed in the bottom trench. The anode conductive material layer is located at the bottom of the gate conductive material layer, and an intermediate dielectric layer is isolated between the gate conductive material layer and the anode conductive material layer; The bottom dielectric layer is isolated between the anode conductive material layer and the inner surface of the bottom trench.

3. The trench-gate power device according to claim 1 or 2, characterized in that: The trench gate power device is a trench gate MOSFET; A drain region heavily doped with a first conductivity type is formed at the bottom of the epitaxial layer; A drift region is composed of the epitaxial layer between the channel region and the drain region; A back metal layer is formed on the back surface of the drain region and the drain electrode is composed of the back metal layer.

4. The trench-gate power device according to claim 1 or 2, characterized in that: The minimum value of the bottom width of the first contact hole reaches less than 0.2 micrometers.

5. The trench-gate power device according to claim 1 or 2, characterized in that: The top dielectric layer includes an oxide layer.

6. The trench-gate power device according to claim 3, characterized in that: The epitaxial layer is formed on the surface of a semiconductor substrate; The semiconductor substrate is heavily doped with a first conductivity type, and the drain region is composed of the semiconductor substrate after back thinning; or, the drain region is composed of a back ion implantation region formed by first conductivity type back ion implantation on the basis of the semiconductor substrate after back thinning.

7. The trench-gate power device according to claim 2, characterized in that: The material of the gate conductive material layer includes polysilicon, and the material of the anode conductive material layer includes polysilicon; a metal silicide is formed on the polysilicon surface of the gate conductive material layer.

8. The trench-gate power device according to claim 2, characterized in that: There is a source electrode conductive material layer lead-out region outside the device unit region, and the gate trench and the source electrode conductive material layer are also formed in the source electrode conductive material layer lead-out region; In the source electrode conductive material layer lead-out region, a protective dielectric layer is filled in the bottom trench at the top of the source electrode conductive material layer and the top dielectric layer is filled in the top trench; The source conductive material layer in the device unit region is connected to the source conductive material layer in the source conductive material layer lead-out region and is connected to the source through a second contact hole formed on the top of the source conductive material layer in the source conductive material layer lead-out region.

9. The trench-gate power device according to claim 1, characterized in that: An ohmic contact region composed of a second conductive type heavily doped region is further formed at the bottom of the first contact hole.

10. The trench-gate power device according to claim 6, characterized in that: The semiconductor substrate includes a silicon substrate, and the epitaxial layer includes a silicon epitaxial layer.

11. A manufacturing method of a trench-gate power device, characterized in that, It includes the following steps: Step 1: Form a gate trench formed by superimposing a bottom trench and a top trench in an epitaxial layer of a first conductive type, and the width of the top trench is greater than the width of the bottom trench; The device unit region includes a plurality of parallel device units, and each device unit includes one of the gate trenches; Step 2: Form a trench gate, including: Form a bottom dielectric layer on the bottom surface of the bottom trench and form a gate dielectric layer on the side surface of the bottom trench; Form a gate conductive material layer to fill the bottom trench; Step 3: Perform a second conductive type ion implantation to form a channel region in the epitaxial layer; longitudinally, the gate conductive material layer passes through the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel; Step 4: Perform a first conductive type heavy doping ion implantation to form a source region in the epitaxial layer on the surface of the channel region; Step 5: Fill the top trench with a top dielectric layer; Step 6: Form an interlayer film, contact holes, and a front metal layer, and pattern the front metal layer to form a source and a gate; The formation process of the contact hole includes: performing etching to form an opening of the contact hole, and filling the opening of the contact hole with metal to form the contact hole; The source region is connected to the source through a first contact hole, the first contact hole passes through the source region and contacts the channel region, and the first contact hole is shared by two adjacent device units; during the etching process of the opening of the first contact hole, the bottom opening of the first contact hole is formed by etching the epitaxial layer with the top dielectric layer in two adjacent gate trenches as a self-alignment condition, and the bottom opening of the first contact hole passes through the source region and exposes the channel region.

12. The manufacturing method of the trench-gate power device according to claim 11, wherein: Step 1 includes the following sub-steps: Step 11: Form a first hard mask layer on the surface of the epitaxial layer and pattern the first hard mask layer. After patterning, the first hard mask layer opens the formation region of the top trench and covers the outside of the formation region of the top trench; Step 12: Use the first hard mask layer as a mask to etch the epitaxial layer to form the top trench; Step 13: Form a second hard mask layer on the inner surface of the top trench and pattern the second hard mask layer. After patterning, the second hard mask layer opens the formation region of the bottom trench and covers the inner surface of the top trench outside the formation region of the bottom trench; the formation region of the bottom trench is located in the top trench and the width of the formation region of the top trench is smaller than the width of the top trench; Step 14: Using the first hard mask layer and the second hard mask layer as masks, etch the epitaxial layer to form the bottom trench at the bottom of the top trench.

13. The manufacturing method of the trench-gate power device according to claim 12, wherein: The trench-gate power device is a trench-gate power device with a shield gate; in step two, a shield gate needs to be formed before forming the trench gate. Step two includes the following sub-steps: Form the bottom dielectric layer on the bottom surface and side surface of the bottom trench; Form the source conductive material layer in the bottom region of the bottom trench; Form the intermediate dielectric layer on the surface of the source conductive material layer; Remove the bottom dielectric layer on the side surface of the bottom trench at the top of the intermediate dielectric layer; Form the gate dielectric layer on the side surface of the bottom trench at the top of the intermediate dielectric layer; Form the gate conductive material layer in the bottom trench.

14. The manufacturing method of the trench-gate power device according to claim 11 or 12 or 13, wherein: The trench-gate power device is a trench-gate MOSFET; after step six, the following back-end process is also included: The epitaxial layer is formed on the surface of the semiconductor substrate; The semiconductor substrate has a heavily doped first conductive type. The semiconductor substrate is thinned on the back side, and the thinned semiconductor substrate directly forms the drain region; Alternatively, the semiconductor substrate is thinned on the back side, and a back-side ion implantation of the first conductive type is performed to form the drain region; Form a back-side metal layer on the back side of the drain region and form the drain electrode from the back-side metal layer.

15. The manufacturing method of the trench-gate power device according to claim 11 or 12 or 13, wherein: The minimum value of the bottom width of the first contact hole reaches less than 0.2 micrometers.

16. The manufacturing method of the trench-gate power device according to claim 11 or 12 or 13, wherein: The top dielectric layer includes an oxide layer.

17. The manufacturing method of the trench-gate power device according to claim 13, wherein: The material of the gate conductive material layer includes polysilicon, and the material of the source conductive material layer includes polysilicon; After forming the gate conductive material layer in the bottom trench, it further includes the step of forming a metal silicide on the polysilicon surface of the gate conductive material layer.

18. The manufacturing method of the trench gate power device according to claim 13, characterized in that: There is a source conductive material layer lead-out region outside the device cell region; In step one, the gate trench is also formed in the source conductive material layer lead-out region; In step two, in the source conductive material layer lead-out region, after forming the source conductive material layer, the gate trench at the top of the source conductive material layer is filled with a protective dielectric layer; After forming the gate conductive material layer in the device cell region, the protective dielectric layer in the top trench, the second hard mask layer, and the first hard mask layer outside the gate trench are removed; In step six, in the process of forming the contact hole, it includes the step of forming a second contact hole on the top of the source conductive material layer in the source conductive material layer lead-out region.

19. The manufacturing method of the trench gate power device according to claim 11, characterized in that: In step six, after the bottom opening of the first contact hole is formed, it further includes the step of performing a second conductive type heavy doping injection to form an ohmic contact region.

20. The manufacturing method of the trench gate power device according to claim 14, characterized in that: The semiconductor substrate includes a silicon substrate, and the epitaxial layer includes a silicon epitaxial layer.

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