Split-gate memory and method of manufacturing the same

Abstract

The application provides a split-gate memory and a manufacturing method thereof. The manufacturing method of the split-gate memory comprises the following steps: providing a substrate, wherein a word line is formed on the substrate, and a vertically-stacked floating gate, a control gate and a first side wall are formed on the substrate on both sides of the word line; removing part of the first side wall to expose part of the surface of the control gate on the side different from the word line; forming a second side wall on the sidewall of the floating gate and the control gate on the side different from the word line; and forming a metal silicide layer on the exposed part of the control gate. The application forms a metal silicide layer on the control gate to reduce the resistance of the control gate, thereby reducing the number of contact holes and the area of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing technology, and in particular to a split-gate memory and a manufacturing method thereof. BACKGROUND

[0002] As a kind of non-volatile memory, flash memory device has the characteristics of convenience, high storage density and strong reliability, and is widely used. The structure of the existing flash memory device usually includes a split-gate structure, a stacked-gate structure or a combination thereof, wherein the split-gate flash memory device has the characteristics of high programming efficiency.

[0003] Each word line (WL) of the split-gate flash memory device is provided with a control gate (CG) on both sides. In order to reduce the resistance while ensuring the transmission efficiency, a contact hole (CT) is needed every 128 bits on the control gate to connect the control gate out. However, referring to Figure 1 , the area occupied by the position of the contact hole 1 is relatively large, about 13% of the area of 128 bits. Therefore, reducing the number of contact holes can effectively reduce the area of the split-gate flash memory device, thereby improving the competitiveness of the split-gate flash memory device by reducing the device area while increasing the storage capacity.

[0004] Therefore, a method is needed to reduce the number of contact holes in the flash memory device, thereby reducing the area of the flash memory device. SUMMARY

[0005] The present application aims to provide a split-gate memory and a manufacturing method thereof, which forms a metal silicide layer on the control gate to reduce the resistance of the control gate, thereby reducing the number of contact holes and further reducing the area of the semiconductor device.

[0006] In order to achieve the above-mentioned purpose, the present application provides a manufacturing method of a split-gate memory, comprising:

[0007] providing a substrate, the substrate being provided with a word line, and the substrate on both sides of the word line being provided with a vertically stacked floating gate, control gate and first side wall;

[0008] removing part of the first side wall to expose part of the surface of the control gate other than the side of the word line;

[0009] forming a second side wall on the sidewall of the control gate other than the side of the word line; and

[0010] forming a metal silicide layer on the exposed part of the control gate.

[0011] Optionally, a wet etching process is used to remove part of the first side wall.

[0012] Optionally, after forming the metal silicide layer, further comprising:

[0013] forming an interlayer dielectric layer on the substrate, the first sidewall, the second sidewall, the metal silicide layer and the word line;

[0014] forming a contact hole exposing the control gate in the interlayer dielectric layer, and forming an electrical connector in the contact hole.

[0015] Optionally, the material of the first sidewall and the second sidewall are different.

[0016] Optionally, the first sidewall is a silicon oxide layer, and the second sidewall is a silicon oxide layer or a silicon nitride layer.

[0017] Optionally, the material of the metal silicide layer comprises nickel silicide or platinum silicide.

[0018] Optionally, the process of forming the word line, the floating gate and the control gate comprises:

[0019] forming a floating gate material layer, a control gate material layer and a hard mask layer on the substrate in sequence, and forming an opening on the hard mask layer;

[0020] forming the first sidewall on the sidewall of the opening, etching the control gate material layer with the hard mask layer and the first sidewall as masks, so that the opening exposes the floating gate material layer, and forming a third sidewall on the sidewall of the opening;

[0021] etching the floating gate material layer with the hard mask layer, the first sidewall and the third sidewall as masks, so that the opening exposes the substrate, and forming a fourth sidewall on the sidewall and the bottom of the opening;

[0022] forming a word line in the opening; and,

[0023] removing the hard mask layer and the control gate material layer and the floating gate material layer under the hard mask layer, to form the floating gate and the control gate.

[0024] Correspondingly, the application further provides a split-gate memory, comprising:

[0025] a substrate;

[0026] a word line arranged on the surface of the substrate;

[0027] a floating gate arranged on the surface of the substrate on both sides of the word line;

[0028] a control gate arranged on the surface of the floating gate, and a metal silicide layer arranged on the part of the surface of the control gate other than the side of the word line;

[0029] a first side wall disposed on a surface of the control gate near the word line;

[0030] a second side wall disposed on a sidewall of the floating gate and the control gate away from the word line.

[0031] Optionally, the method further comprises a third side wall disposed on a sidewall of the control gate and the first side wall near the word line, and a fourth side wall disposed on a sidewall of the floating gate and the third side wall near the word line.

[0032] Optionally, a floating gate oxide layer is further disposed between the substrate and the floating gate, and a control gate oxide layer is further disposed between the floating gate and the control gate.

[0033] In summary, the present application provides a split-gate memory and a manufacturing method thereof. The manufacturing method of the split-gate memory comprises: providing a substrate, wherein the substrate is formed with a word line, and the substrate on both sides of the word line is formed with a vertically stacked floating gate, control gate and first side wall; removing part of the first side wall to expose part of the surface of the control gate away from the word line; forming a second side wall on the sidewall of the floating gate and the control gate away from the word line; and forming a metal silicide layer on the exposed part of the control gate. The present application reduces the resistance of the control gate by forming a metal silicide layer on the control gate, thereby reducing the number of contact holes and further reducing the area of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 Fig. 1 is a structural schematic diagram of a flash memory device;

[0035] Figure 2 Fig. 2 is a flow chart of a manufacturing method of a split-gate memory according to an embodiment of the present application;

[0036] Figures 3-9 Fig. 3 is a structural schematic diagram corresponding to each step of the manufacturing method of the split-gate memory according to an embodiment of the present application;

[0037] In the drawings, the following reference signs are used:

[0038] 1 - contact hole;

[0039] 100 - substrate; 110 - floating gate material layer; 111 - floating gate; 120 - control gate material layer; 121 - control gate; 122 - metal silicide layer; 130 - hard mask layer; 131 - opening; 140 - first side wall; 141 - third side wall; 142 - fourth side wall; 143 - second side wall; 150 - word line. DETAILED DESCRIPTION

[0040] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0041] Figure 2 This is a flowchart illustrating a method for manufacturing a grid-based memory according to an embodiment of the present invention. (See attached document.) Figure 2 The manufacturing method of the gate-based memory described in this embodiment includes:

[0042] Step S01: Provide a substrate on which word lines are formed, and on the substrates on both sides of the word lines, vertically stacked floating gates, control gates, and first sidewalls are formed.

[0043] Step S02: Remove a portion of the first sidewall to expose a portion of the surface of the control grid that is different from the side of the word line;

[0044] Step S03: Form a second sidewall on the sidewall of the floating gate and the control gate that is different from the word line; and,

[0045] Step S04: Form a metal silicide layer on the exposed portion of the control gate.

[0046] Figures 3-9 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of a gate-type memory provided in an embodiment of the present invention. The following is in conjunction with... Figures 3-9 The manufacturing method of the grid-type memory described in this embodiment is explained in detail.

[0047] First, refer to Figures 3-6 In step S01, a substrate 100 is provided, on which word lines 150 are formed, and on the substrates 100 on both sides of the word lines 150, vertically stacked floating gates 111, control gates 121 and first sidewalls 140 are formed.

[0048] In this embodiment, a self-aligned process is used to form the basic structure of the segmented memory, that is, the process of forming the word line 150, the floating gate 111, and the control gate 121 includes: First, referring to... Figure 3 A floating gate material layer 110, a control gate material layer 120, and a hard mask layer 130 are sequentially formed on the substrate 100, and an opening 131 is formed on the hard mask layer 130; then, refer to Figure 4 A first sidewall 140 is formed on the sidewall of the opening 131. The control gate material layer 120 is etched using the hard mask layer 130 and the first sidewall 140 as a mask to expose the floating gate material layer 110 at the opening 131. A third sidewall 141 is formed on the sidewall of the opening 131. (See also...)Figure 5 The hard mask layer 130, the first side wall 140 and the third side wall 141 are used as masks to etch the floating gate material layer 110, so that the opening 131 exposes the substrate 100, and a fourth side wall 142 is formed on the sidewall and bottom of the opening 131; refer to Figure 6 A word line 150 is formed in the opening 131; and the hard mask layer 130, the control gate material layer 120 and the floating gate material layer 110 under the hard mask layer 130 are removed to form the floating gate 111 and the control gate 121.

[0049] It should be noted that in other embodiments of the present application, the method for forming the word line 150, the floating gate 111 and the control gate 121 can be adjusted according to actual needs, and the present application does not limit this. Optionally, a floating gate oxide layer (not labeled in the figure) is further formed between the substrate 100 and the floating gate 111, and a control gate oxide layer (not labeled in the figure) is further formed between the floating gate 111 and the control gate 121.

[0050] In the embodiment, the substrate 100 is a silicon substrate, the first side wall 140 is a silicon oxide layer, and the floating gate 111 and the control gate 121 are both polycrystalline silicon layers. In other embodiments of the present application, the material of the substrate 100 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and the substrate 100 can also be a multilayer structure composed of these semiconductor materials or a silicon-on-insulator (SOI), a silicon-on-silicon-on-insulator (SSOI), a silicon germanium-on-silicon-on-insulator (S-SiGeOI), a silicon germanium-on-insulator (SiGeOI) and a germanium-on-insulator (GeO), and the present application does not limit this.

[0051] Subsequently, refer to Figure 7 Step S02 is performed to remove part of the first side wall 140 to expose part of the surface of the control gate 121 other than the side of the word line 150. In the embodiment, a wet etching process is used to remove part of the first side wall 140.

[0052] Next, refer to Figure 8In step S03, a second sidewall 143 is formed on the sidewall of the floating gate 111 and the control gate 121 which is opposite to the side of the word line 150. In the embodiment, the first sidewall 140 and the second sidewall 143 are made of different materials, the first sidewall 140 is made of silicon oxide, and the second sidewall 143 is made of silicon nitride. In other embodiments of the present application, the materials of the first sidewall 140 and the second sidewall 143 can be selected according to actual needs, for example, the material of the second sidewall 143 can also be silicon oxide, and the present application is not limited in this aspect.

[0053] Next, referring to Figure 9 In step S03, a metal silicide layer 122 is formed on the exposed part of the control gate 121 to reduce the resistance of the control gate 121. In the embodiment, the material of the metal silicide layer 122 includes nickel silicide or platinum silicide. It should be noted that between step S02 and step S03, there is also a process for other semiconductor structures, which includes multiple wet etching processes. In the embodiment, the process time of the above-mentioned wet etching process can be appropriately extended to further remove the first sidewall 140 on the control gate 121 before forming the metal silicide layer 122.

[0054] In addition, referring to Figure 9 After forming the metal silicide layer 122, the manufacturing method of the semiconductor device further includes: forming an interlayer dielectric layer (not shown in the figure) on the substrate 100, the first sidewall 140, the second sidewall 143, the metal silicide layer 122 and the word line 150; forming a contact hole (not shown in the figure) exposing the control gate 121 in the interlayer dielectric layer, and forming an electrical connector (not shown in the figure) in the contact hole. Optionally, the interlayer dielectric layer is a silicon oxide layer, and the material of the electrical connector includes tungsten.

[0055] Correspondingly, referring to Figure 9 The embodiment also provides a split-gate memory, including:

[0056] a substrate 100;

[0057] a word line 150 arranged on the surface of the substrate 100;

[0058] a floating gate 111 arranged on the surface of the substrate 100 on both sides of the word line 150;

[0059] a control gate 121 arranged on the surface of the floating gate 111, and a metal silicide layer 122 is arranged on the part of the surface of the control gate 121 which is opposite to the side of the word line 150;

[0060] A first sidewall 140 is disposed on a surface of the control gate 121 near the word line 150.

[0061] A second sidewall 143 is disposed on a sidewall of the floating gate 111 and the control gate 121 away from the word line 150.

[0062] In the embodiment, the split-gate memory further comprises a third sidewall 141 and a fourth sidewall 142. The third sidewall 141 is disposed on a sidewall of the control gate 121 and the first sidewall 140 near the word line 150. The fourth sidewall 142 is disposed on a sidewall of the floating gate 111 and the third sidewall 141 near the word line 150. Optionally, a floating gate oxide layer (not labeled in the figure) is formed between the substrate 100 and the floating gate 111, and a control gate oxide layer (not labeled in the figure) is formed between the floating gate 111 and the control gate 121.

[0063] It should be noted that in other embodiments of the present application, the manufacturing method of the split-gate memory can be used to manufacture other semiconductor devices with the same structure, and the present application does not limit this. Compared with the existing flash memory devices, the resistance of the control gate in the split-gate memory of the embodiment is lower, thereby reducing the number of contact holes and further reducing the area of the split-gate memory.

[0064] In summary, the present application provides a split-gate memory and a manufacturing method thereof. The manufacturing method of the split-gate memory comprises: providing a substrate, the substrate having a word line formed thereon, the substrate on both sides of the word line having a vertically stacked floating gate, a control gate and a first sidewall; removing the first sidewall to expose a part of the surface of the control gate away from the word line; forming a second sidewall on the sidewall of the floating gate and the control gate away from the word line; and forming a metal silicide layer on the exposed part of the control gate. The present application reduces the resistance of the control gate by forming a metal silicide layer on the control gate, thereby reducing the number of contact holes and further reducing the area of the semiconductor device.

[0065] The above merely describes the preferred embodiments of the present application and does not limit the present application in any way. Any person skilled in the art can make any equivalent replacement, modification or change to the technical solutions and technical contents disclosed in the present application without departing from the scope of the technical solutions of the present application, and such changes still fall within the protection scope of the present application.

Claims

1. A manufacturing method of a split-gate memory, characterized by, The method comprises: providing a substrate having a word line formed thereon, and a vertically stacked floating gate, control gate and first sidewall formed on the substrate on both sides of the word line, the floating gate, the control gate and the first sidewall being aligned with the sidewall on the side opposite to the word line; removing part of the first sidewall along the sidewall of the first sidewall to expose part of the surface of the control gate on the side opposite to the word line; forming a second sidewall on the sidewall of the floating gate and the control gate on the side opposite to the word line; and, forming a metal silicide layer on the exposed part of the control gate.

2. The manufacturing method of the split-gate memory according to claim 1, wherein Part of the first sidewall is removed by using a wet etching process.

3. The manufacturing method of the split-gate memory as claimed in claim 1, wherein, After forming the metal silicide layer, the method further comprises: forming an interlayer dielectric layer on the substrate, the first sidewall, the second sidewall, the metal silicide layer and the word line; forming a contact hole exposing the control gate in the interlayer dielectric layer, and forming an electrical connector in the contact hole.

4. The manufacturing method of the split-gate memory as claimed in claim 1, wherein, The material of the first sidewall and the second sidewall is not the same.

5. The method of claim 1, wherein the first sidewall is a silicon oxide layer, and the second sidewall is a silicon oxide layer or a silicon nitride layer.

6. The manufacturing method of the split-gate memory as claimed in claim 1, wherein, The material of the metal silicide layer comprises nickel silicide or platinum silicide.

7. The manufacturing method of the split-gate memory as claimed in claim 1, wherein, The process of forming the word line, the floating gate and the control gate comprises: forming a floating gate material layer, a control gate material layer and a hard mask layer on the substrate in sequence, and forming an opening on the hard mask layer; forming the first sidewall on the sidewall of the opening, etching the control gate material layer with the hard mask layer and the first sidewall as masks to expose the floating gate material layer with the opening, and forming a third sidewall on the sidewall of the opening; etching the floating gate material layer with the hard mask layer, the first sidewall and the third sidewall as masks to expose the substrate with the opening, and forming a fourth sidewall on the sidewall and the bottom of the opening; forming a word line in the opening; and, removing the hard mask layer and the control gate material layer and the floating gate material layer under the hard mask layer to form the floating gate and the control gate.

8. A split-gate memory, characterized by, The method comprises: a substrate; a word line arranged on the surface of the substrate; a floating gate arranged on the surface of the substrate on both sides of the word line; a control gate arranged on the surface of the floating gate, part of the surface of the control gate on the side opposite to the word line being provided with a metal silicide layer, the floating gate and the control gate being aligned with the sidewall on the side opposite to the word line; a first sidewall arranged on the surface of the control gate close to the side of the word line, and the metal silicide layer being exposed along the sidewall of the first sidewall; a second sidewall arranged on the sidewall of the floating gate and the control gate on the side opposite to the word line.

9. The split-gate memory of claim 8, wherein, The method further comprises a third sidewall and a fourth sidewall, the third sidewall being arranged on the sidewall of the control gate and the first sidewall close to the side of the word line, and the fourth sidewall being arranged on the sidewall of the floating gate and the third sidewall close to the side of the word line.

10. The split-gate memory of claim 8 or 9, wherein, A floating gate oxide layer is further arranged between the substrate and the floating gate, and a control gate oxide layer is further arranged between the floating gate and the control gate.

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