Semiconductor structure and method of making the same, three-dimensional memory

Abstract

The disclosure provides a semiconductor structure and a preparation method thereof, and a three-dimensional memory, and relates to the technical field of semiconductor chips, aiming to improve the stability of the mark, and thus improve the yield level of the semiconductor structure. The preparation method of the semiconductor structure comprises the following steps: forming a first stack structure on a substrate; forming a mark in a mark area, the mark penetrating through the first stack structure; sequentially forming a protective layer and a first mask layer on a side of the first stack structure away from the substrate; etching a second sub-layer based on the first mask layer, so that the thickness of the second sub-layer is smaller than the thickness of a first sub-layer; removing the first mask layer; etching the first sub-layer, the second sub-layer and the first stack structure below the second sub-layer, so as to expose an end of the mark away from the substrate, and so that a part of the first stack structure located in an array area is still covered by the first sub-layer. The semiconductor structure is applied to a three-dimensional memory, so as to realize the preparation of the three-dimensional memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to semiconductor structures and their fabrication methods, and three-dimensional memory. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] Improving the process yield of 3D memory is a technical problem that needs to be solved. Summary of the Invention

[0005] Embodiments of this disclosure provide a semiconductor structure and its fabrication method, as well as a three-dimensional memory, aimed at improving the stability of the marker in use, thereby improving the yield of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0007] On the one hand, a method for fabricating a semiconductor structure is provided. The method for fabricating the semiconductor structure includes:

[0008] A first stacked structure is formed on a substrate, the first stacked structure comprising alternating layers of first insulating layers and layers of first sacrificial layers; the first stacked structure has an array region and a marker region.

[0009] A mark is formed in the marked area, and the mark extends through the first stacked structure.

[0010] A protective layer and a first mask layer are sequentially formed on the side of the first stacked structure away from the substrate; the protective layer includes a first sub-layer located in the array region and a second sub-layer located in the marking region, and the first mask layer exposes the marking region.

[0011] The second sub-layer is etched based on the first mask layer, so that the thickness of the second sub-layer is less than the thickness of the first sub-layer.

[0012] Remove the first mask layer.

[0013] The first sublayer, the second sublayer, and the first stacked structure beneath the second sublayer are etched to expose the end of the mark away from the substrate, while the portion of the first stacked structure located in the array region is still covered by the first sublayer.

[0014] The semiconductor structure fabrication method of the above embodiments of this disclosure first etches a protective layer based on a first mask layer, making the thickness of the second sub-layer located in the marking region less than the thickness of the first sub-layer. Then, it etches the first sub-layer, the second sub-layer, and the first stacked layer below the second sub-layer to expose the end of the mark away from the substrate. Compared with directly removing the second sub-layer in the protective layer using the first mask layer to expose the end of the mark away from the substrate, this method effectively avoids the problem of damage to the end of the mark away from the substrate during the removal of the first mask layer, improves the stability of the mark, ensures the accuracy of the mask placement position in the photolithography process and the accuracy of the measurement results during overlay (OVL) measurement, and helps to improve the OVL compensation results and increase the yield of semiconductor structure fabrication.

[0015] Meanwhile, the markers made using the semiconductor structure fabrication methods provided in some embodiments of this disclosure penetrate the first stacked structure, with the ends of the markers protruding from the first stacked structure. This allows for the deposition of a second stacked structure on the first stacked structure, and the formation of a hard mask layer on the second stacked structure. When the second mask layer is formed on the hard mask layer, the portion of the second mask layer located in the marked area will also exhibit protrusions and depressions. Therefore, during the photolithography process, the photolithography equipment can directly detect the morphology of the second mask layer located in the marked area and determine the mask placement position based on this morphology. Overlay measurement after the photolithography process can also be performed using the morphology of the second mask layer located in the marked area, thereby effectively improving the accuracy of OVL measurement after development, improving OVL compensation results, and ultimately improving the final yield level of the semiconductor structure.

[0016] In some embodiments, the film layer closest to the protective layer in the first stacked structure is a first insulating layer; the etching of the first sub-layer, the second sub-layer, and the first stacked structure below the second sub-layer includes: using a first etching process to etch the first sub-layer, the second sub-layer, and the first insulating layer below the second sub-layer until the first sacrificial layer below the first insulating layer is exposed; using a second etching process to etch the portion of the first sacrificial layer exposed in the marking area.

[0017] In some embodiments, the material of the first insulating layer is the same as the material of the protective layer.

[0018] In some embodiments, the first etching process and the second etching process are wet etching processes; the etching solution used in the first etching process includes hydrofluoric acid; and / or, the etching solution used in the second etching process includes phosphoric acid.

[0019] In some embodiments, the film layer closest to the protective layer in the first stacked structure is the first insulating layer; after etching the second sub-layer based on the first mask layer, the sum of the thickness of the second sub-layer and the thickness of the first insulating layer is less than the thickness of the first sub-layer.

[0020] In some embodiments, while forming a mark in the marked area, the preparation method further includes:

[0021] Multiple preset channel pillars are formed in the array region, and the multiple preset channel pillars penetrate the first stacked structure.

[0022] In some embodiments, forming the mark and forming the plurality of preset channel posts includes: forming a mark hole penetrating the first stacked structure in the mark area, and forming a plurality of first channel holes penetrating the first stacked structure in the array area; filling the mark hole and the plurality of first channel holes with sacrificial material to form the mark and the plurality of preset channel posts.

[0023] In some embodiments, after filling the marking holes and the plurality of first channel holes with sacrificial material, the preparation method further includes: using a chemical mechanical polishing process to remove the sacrificial material covering the first stacked structure.

[0024] In some embodiments, the fabrication method further includes: forming a second stacked structure on the side of the first stacked structure away from the substrate, the second stacked structure comprising alternating layers of second insulating layers and layers of second sacrificial layers; in the marking region, the surface of the second stacked structure away from the substrate has a raised and recessed morphology, the raised and the marking corresponding to each other in a direction perpendicular to the substrate.

[0025] In some embodiments, the method for fabricating the semiconductor structure further includes:

[0026] A hard mask layer is formed on the side of the second stacked structure away from the substrate.

[0027] The hard mask layer is patterned, the hard mask layer includes a plurality of first openings, and the orthographic projection of the plurality of first openings on the substrate overlaps with the orthographic projection of the plurality of preset channel pillars on the substrate.

[0028] Based on the hard mask layer, the second stacked structure is etched to form a plurality of second channel holes, each second channel hole exposing a preset channel post.

[0029] Remove the plurality of preset channel posts to form a channel structure in the second channel hole and the first channel hole where the preset channel posts are located.

[0030] In some embodiments, the fabrication method further includes, prior to patterning the hard mask layer:

[0031] A second mask layer is formed to cover the hard mask layer; in the marked area, the second mask layer has a raised and recessed morphology, with the raised and the marked positions corresponding in a direction perpendicular to the substrate.

[0032] Based on the topography of the second mask layer in the marking area, the second mask layer is patterned to form an overlay mark and a plurality of second openings; the overlay mark is located in the marking area, and the orthographic projection of the overlay mark on the substrate is offset from the orthographic projection of the mark on the substrate; the plurality of second openings are located in the array area and expose the portion of the hard mask layer to be formed with a plurality of first openings.

[0033] In some embodiments, after forming the overlay marks and the plurality of second openings, and before patterning the hard mask layer, the fabrication method further includes:

[0034] Based on the relative positions of the overlay marks and the second mask layer in the topography of the marked area, it is verified whether the plurality of second openings in the direction perpendicular to the substrate correspond to the positions of the plurality of preset channel pillars.

[0035] If the test result is negative, the second mask layer is removed to form a second mask layer including overlay marks and multiple second openings, and the test is performed until the test result is positive.

[0036] In some embodiments, the material of the protective layer includes silicon oxide.

[0037] In some embodiments, the material of the marker includes carbon or polycrystalline silicon.

[0038] In some embodiments, the material of the first sacrificial layer is different from the material of the marker, and the material of the first sacrificial layer includes silicon nitride, silicon oxide, or polycrystalline silicon.

[0039] In some embodiments, the material of the first mask layer includes photoresist.

[0040] On the other hand, a semiconductor structure is provided, the semiconductor structure having an array region and a marking region; the semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a plurality of channel structures, and a marking. The first stacked structure is disposed on the substrate and includes alternating stacked multiple layers of first insulating layers and multiple layers of first gate lines. The second stacked structure is disposed on the side of the first stacked structure away from the substrate and includes alternating stacked multiple layers of second insulating layers and multiple layers of second gate lines. The plurality of channel structures penetrate the first stacked structure and the second stacked structure and are located in the array region. The marking penetrates the first stacked structure and is located in the marking region; the end face of the marking away from the substrate protrudes from the surface of the first stacked structure away from the substrate.

[0041] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in any of the above embodiments and peripheral circuitry electrically connected to the semiconductor structure.

[0042] It is understood that the beneficial effects of the semiconductor structure and three-dimensional memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0044] Figure 1 This is a flowchart of a method for preparing a marker according to some embodiments;

[0045] Figures 2-9 for Figure 1 The diagram shows the state of the preparation method of the marker.

[0046] Figure 10 This is a flowchart of another method for preparing a marker according to some embodiments;

[0047] Figure 11 for Figure 10 The diagram shows the state of the preparation method of the marker.

[0048] Figure 12 This is a flowchart of another method for preparing a marker according to some embodiments;

[0049] Figure 13 for Figure 12 The diagram shows the state of the preparation method of the marker.

[0050] Figure 14 This is a flowchart of another method for preparing a marker according to some embodiments;

[0051] Figure 15 for Figure 14 The diagram shows the state of the preparation method of the marker.

[0052] Figure 16 This is a flowchart of another method for preparing a marker according to some embodiments;

[0053] Figure 17 This is a structural diagram of a marker according to some embodiments;

[0054] Figure 18 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0055] Figure 19 for Figure 18 A state diagram illustrating the fabrication method of the semiconductor structure shown;

[0056] Figure 20 This is a flowchart of a method for fabricating another semiconductor structure according to some embodiments;

[0057] Figures 21-24 for Figure 20 A state diagram illustrating the fabrication method of the semiconductor structure shown;

[0058] Figure 25 This is a flowchart of another method for fabricating a semiconductor structure according to some embodiments;

[0059] Figures 26-28 for Figure 25 A state diagram illustrating the fabrication method of the semiconductor structure shown;

[0060] Figure 29 This is a flowchart of a method for fabricating another semiconductor structure according to some embodiments;

[0061] Figure 30 This is a structural diagram of a semiconductor structure according to some embodiments;

[0062] Figure 31 This is a structural diagram of a three-dimensional memory according to some embodiments. Detailed Implementation

[0063] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0064] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0065] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0066] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0067] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0068] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0069] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0070] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0071] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0072] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0073] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0074] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0075] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0076] Three-dimensional memory overcomes the limitations of two-dimensional or planar flash memory by vertically stacking multiple layers of data storage cells, enabling higher storage capacity within smaller gaps, thereby effectively reducing cost and power consumption. However, as the number of stacked layers continues to increase, the difficulty of deep-hole etching to form channel holes in the stacked structure becomes increasingly high.

[0077] The inventors of this application discovered through research that, in order to meet the requirements of high aspect ratio and high selectivity in the etching process, thicker and denser hard masks are needed in the manufacturing process of 3D memory. However, as the material thickness and density increase, the absorption of light by the hard mask also increases, while the reflection decreases, thus greatly affecting the photolithography process.

[0078] For example, during the photolithography process, the light source of the photolithography equipment (such as a photolithography machine) is used to acquire image information of the alignment pattern pre-formed in the semiconductor structure, and the image information of the alignment pattern is compared with the information of the required mask. Based on the comparison result, the placement position of the mask is determined to ensure the accuracy of the mask placement, and thus ensure the accuracy of transferring the pattern in the mask to the photoresist.

[0079] Because hard masks absorb more light and reflect less, the accuracy of photolithography equipment in detecting and aligning patterns decreases. This can easily lead to deviations in the placement of the mask, reducing the accuracy of transferring the pattern from the mask to the photoresist.

[0080] Similarly, the increased absorption and reduced reflection of light by the hard mask also makes OVL measurement after the photolithography process more difficult. The OVL measurement accuracy of the developed pattern is relatively low, which affects the OVL compensation result and thus affects the final yield level of the semiconductor structure.

[0081] To address the aforementioned issues, related technologies have incorporated a mark that penetrates the stacked structure within the semiconductor structure, with a height difference between the end face of the mark away from the substrate and the surface of the stacked structure away from the substrate.

[0082] However, during the formation of this mark, the exposed end of the mark is easily damaged, which can cause the mark to fail. This can lead to problems such as the inability to confirm the mask placement position during the photolithography process, or the mask placement position being offset. It can also cause inaccurate measurement results during OVL measurement, misalignment of the channel holes in the upper and lower parts of the stacked structure, and defects in the semiconductor structure.

[0083] Based on the above, this disclosure provides a method for fabricating a semiconductor structure. In some embodiments, such as... Figure 1 As shown, the method for fabricating the above-mentioned semiconductor structure may include a method for fabricating a marker. The method for fabricating the marker includes:

[0084] S100, such as Figure 2 and Figure 3 As shown, a first stacked structure 20 is formed on the substrate 10. The first stacked structure 20 includes multiple layers of first insulating layers 21 and multiple layers of first sacrificial layers 22 stacked alternately. The first stacked structure 20 has an array region 201 and a marker region 202.

[0085] For example, the material of the first sacrificial layer 22 may include silicon nitride, silicon oxide, or polycrystalline silicon.

[0086] For example, the material of the first insulating layer 21 may include silicon oxide.

[0087] The first insulating layer 21 and the first sacrificial layer 22 can be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), high-density plasma-chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), or sputtering.

[0088] This disclosure does not limit the number of the first insulating layer 21 and the first sacrificial layer 22 in the first stacked structure 20. For example, the number of the first insulating layer 21 or the first sacrificial layer 22 in the first stacked structure 20 may be 8, 16, 24, 32, 48, 64, or more than 64 layers.

[0089] Understandable Figure 3 The number of the first insulating layer 21 and the first sacrificial layer 22 shown is merely an example and does not limit the number of the first insulating layer 21 and the first sacrificial layer 22 in this disclosure.

[0090] For example, the first stack structure 20 may have one or more array regions 201 and one or more marker regions 202. For instance, as... Figure 2 As shown, the first stacking structure 20 may have one array region 201 and four marker regions 202. The array region 201 and the marker regions 202 are staggered.

[0091] This disclosure does not limit the position or shape of the array region 201. In some examples, such as Figure 2 As shown, array region 201 may be located in the central region of the first stacking structure 20. In other examples, array region 201 may be located in the edge region of the first stacking structure 20. In still other examples, a portion of array region 201 may be located in the edge region of the first stacking structure 20, and another portion of array region 201 may be located in the central region of the first stacking structure 20.

[0092] In some examples, such as Figure 2 As shown, the array area 201 can be approximately rectangular. "Approximately rectangular" means that the array area 201 is generally rectangular in shape, but it is not limited to a standard rectangle. That is, "rectangular" here includes not only the basic rectangular shape, but also shapes similar to rectangles, considering process conditions. Alternatively, in some other examples, the marking area 202 can be approximately circular.

[0093] Similarly, this disclosure does not limit the position and shape of the marker region 202, as long as it is offset from the array region 201. In some examples, such as Figure 2 As shown, the marking area 202 may be located in the edge region of the first stacking structure 20, for example, at one of the four corners of the first stacking structure 20. In other examples, the marking area 202 may be located in the center region of the first stacking structure 20. In still other examples, some of the marking areas 202 may be located in the edge region of the first stacking structure 20, while others may be located in the center region of the first stacking structure 20. In yet other examples, the marking area 202 may also be located within the cutting channels of the first stacking structure 20.

[0094] In some examples, such as Figure 2 As shown, the marking area 202 can be roughly rectangular. "Roughly rectangular" means that the overall shape of the marking area 202 is rectangular, but it is not limited to a standard rectangle. That is, "rectangular" here includes not only the basic rectangular shape, but also shapes similar to rectangles, taking into account process conditions.

[0095] Alternatively, in other examples, the marking area 202 may be approximately circular. Here, "approximately circular" means that the overall shape of the marking area 202 is circular, but it is not limited to a standard circle. That is, "circular" here includes not only the basic circular shape, but also, considering process conditions, shapes resembling a circle.

[0096] S200, such as Figure 4 and Figure 5 As shown, a mark 30 is formed in the mark area 202, and the mark 30 penetrates the first stack structure 20.

[0097] The number of markers 30 in each marker area 202 can be one or more.

[0098] This disclosure does not limit the distribution method and location of the markers 30 in the marker area 202. For example, when each marker area 202 includes multiple markers 30, the distance between different markers 30 can be different, that is, multiple markers 30 can be unevenly arranged in the marker area 202.

[0099] In some embodiments of this disclosure, the positions of multiple markers 30 can be adjusted so that their positions correspond to the light emitted by the photolithography equipment. This facilitates the photolithography equipment's identification of the markers 30 and allows for the confirmation of the mask's placement using the markers 30. For example,... Figure 5 As shown, multiple marks 30 can be divided into multiple groups, and each group of marks 30 is arranged into graphics of different shapes and sizes, which facilitates detection by photolithography equipment.

[0100] Some embodiments of this disclosure can also improve the accuracy of OVL measurement of the developed pattern by adjusting the positions of multiple markers 30, thereby improving the OVL compensation results and ultimately improving the final yield level of the semiconductor structure.

[0101] The shape of the mark 30 is not limited in this disclosure; in some examples, such as Figure 5 As shown, the orthographic projection of mark 30 on substrate 10 can be approximately rectangular. Here, "approximately rectangular" means that the overall orthographic projection of mark 30 on substrate 10 is rectangular, but it is not limited to a standard rectangle. That is, "rectangular" here includes not only the basic rectangular shape, but also shapes resembling rectangles, taking into account process conditions.

[0102] In other examples, the orthographic projection of mark 30 onto substrate 10 may be approximately circular. Here, "approximately circular" means that the orthographic projection of mark 30 onto substrate 10 is circular overall, but is not limited to a standard circle. That is, "circular" here includes not only a basic circular shape, but also, considering process conditions, shapes resembling a circle.

[0103] For example, the material marked 30 may include carbon or polycrystalline silicon.

[0104] In some embodiments, the material of the first sacrificial layer 22 is different from the material of the marker 30.

[0105] S300, such as Figure 6 As shown, a protective layer 40 and a first mask layer 50 are sequentially formed on the side of the first stacked structure 20 away from the substrate 10. The protective layer 40 includes a first sub-layer 41 located in the array region 201 and a second sub-layer 42 located in the marking region 202, and the first mask layer 50 exposes the marking region 202.

[0106] For example, the protective layer 40 can be formed by CVD process, spin coating process, etc.

[0107] In some examples, forming the first mask layer 50 may include: forming the first mask layer 50 on the protective layer 40, and patterning the first mask layer 50. For example, the first mask layer 50 may be patterned through processes such as exposure and development.

[0108] For example, the material of the protective layer 40 may include silicon oxide. The material of the first mask layer 50 may include photoresist.

[0109] S400, such as Figure 7 As shown, the second sub-layer 42 is etched based on the first mask layer 50, so that the thickness h1 of the second sub-layer 42 is less than the thickness h2 of the first sub-layer 41.

[0110] For example, the second sublayer 42 can be etched using a dry etching process based on the first mask layer 50.

[0111] S500, see reference Figure 7 and Figure 8 Remove the first mask layer 50.

[0112] For example, the first mask layer 50 can be removed by an ashing process and / or a stripping process.

[0113] S600, such as Figure 9 As shown, the first sublayer 41, the second sublayer 42, and the first stacked structure 20 below the second sublayer 42 are etched to expose the end 301 of the mark 30 away from the substrate 10, while the portion of the first stacked structure 20 located in the array region 201 is still covered by the first sublayer 41.

[0114] In some embodiments of this disclosure, the protective layer 40 is first etched based on the first mask layer 50, such that the thickness of the second sub-layer 42 located in the marking region 202 is less than the thickness of the first sub-layer 41. Then, the first sub-layer 41, the second sub-layer 42, and the first stacked layer below the second sub-layer 42 are etched to expose the end 301 of the marker 30 away from the substrate 10. Compared with directly removing the second sub-layer in the protective layer using the first mask layer to expose the end of the marker away from the substrate, this effectively avoids the problem of damage to the end of the marker away from the substrate during the removal of the first mask layer 50, improves the stability of the marker 30, ensures the accuracy of the mask placement in the photolithography process and the accuracy of the measurement results during OVL measurement, and is conducive to improving the OVL compensation results and increasing the yield of semiconductor structure fabrication.

[0115] The marker 30, fabricated using the methods provided in some embodiments of this disclosure, penetrates the first stacked structure 20, with its end protruding from the first stacked structure 20. A second stacked structure is then deposited on the first stacked structure 20, forming a hard mask layer on the second stacked structure. A second mask layer is then formed on the hard mask layer, and the portion of the second mask layer located in the marked area also exhibits protrusions and depressions. Therefore, during the photolithography process, the photolithography equipment can directly detect the morphology of the second mask layer located in the marked area 202 and determine the mask placement position based on this morphology. Overlay measurement after the photolithography process can also be performed using the morphology of the second mask layer located in the marked area 202, thereby effectively improving the accuracy of OVL measurement after development, improving OVL compensation results, and ultimately improving the final yield level of the semiconductor structure.

[0116] In some embodiments, such as Figure 9 As shown, in the first stacked structure 20, the film layer closest to the protective layer 40 is the first insulating layer 21. Based on this, as... Figure 10 As shown, step S600, etching the first sub-layer 41, the second sub-layer 42, and the first stacked structure 20 below the second sub-layer 42, includes:

[0117] S610, such as Figure 11 As shown, a first etching process is used to etch the first sub-layer 41, the second sub-layer 42, and the first insulating layer 21 below the second sub-layer 42 until the first sacrificial layer 22 below the first insulating layer 21 is exposed.

[0118] S620, such as Figure 9 As shown, the second etching process is used to etch the portion of the first sacrificial layer 22 in the marking area 202 that is exposed.

[0119] For example, the material of the first insulating layer 21 is the same as the material of the protective layer 40. In this way, the etching rate of the first insulating layer 21 can be approximately the same as the etching rate of the protective layer 40, avoiding the problem that the etching rate at the beginning and end of the first etching process is different due to the different materials of the first insulating layer 21 and the protective layer 40, resulting in a longer etching time for the first etching process, and greatly improving the etching efficiency of the first etching process.

[0120] In some embodiments, both the first etching process and the second etching process are wet etching processes. For example, the etching solution used in the first etching process may include hydrofluoric acid. For example, the etching solution used in the second etching process may include phosphoric acid.

[0121] This disclosure discloses some embodiments in which different etching solutions are used to remove portions of the first sublayer 41, the second sublayer 42, and the first insulating layer 21 below the second sublayer 42 in the first etching process, and to remove the exposed portion of the first sacrificial layer 22 in the second etching process, thereby avoiding excessive etching of the first stacked structure and reducing the number of memory cells in the semiconductor structure.

[0122] In some embodiments, such as Figure 8 As shown, the film layer closest to the protective layer 40 in the first stacked structure 20 is the first insulating layer 21. After etching the second sub-layer 42 based on the first mask layer 50, the sum of the thickness h1 of the second sub-layer 42 and the thickness h3 of the first insulating layer 21 is less than the thickness h2 of the first sub-layer 41.

[0123] This configuration helps ensure that, during the subsequent etching of the first sublayer 41, the second sublayer 42, and the first stacked structure 20 below the second sublayer 42, the first sublayer 41 located in the array region 201 is preserved after the first stacked structure 20 below the second sublayer 42 is removed. This helps prevent the first stacked structure 20 located in the array region 201 from being etched, ensuring that the height of the portion of the first stacked structure 20 located in the array region 201 is greater than the height of the portion of the first stacked structure 20 located in the marking region 202. This facilitates the detection of the marking region 202 by the detection device during the semiconductor structure fabrication process, and consequently, facilitates the identification of the marking 30 by the detection device.

[0124] In some embodiments, such as Figure 12 and Figure 13 As shown, while the marker 30 is formed in the marker region 202, the marker preparation method also includes:

[0125] S200', Multiple preset channel pillars 60 are formed in the array region 201, and the multiple preset channel pillars 60 penetrate the first stacking structure 20.

[0126] In this way, the marker 30 and the preset channel pillar 60 are formed simultaneously, and the same mask can be used in the formation process of the two, thereby reducing the number of masks used, reducing the fabrication cost of the marker 30, and further simplifying the fabrication process of the semiconductor structure with the marker 30, thus reducing the fabrication cost of the semiconductor structure.

[0127] In some embodiments, such as Figure 14 As shown, forming the mark 30 and forming a plurality of preset channel posts 60 includes:

[0128] S210, such as Figure 15 As shown, a marking hole 31 penetrating the first stacked structure 20 is formed in the marking area 202, and a plurality of first channel holes 61 penetrating the first stacked structure 20 are formed in the array area 201.

[0129] S220, such as Figure 13 As shown, sacrificial material is filled into the marking hole 31 and the plurality of first channel holes 61 to form a marking 30 and a plurality of preset channel posts 60.

[0130] When the marker 30 and the preset channel pillar 60 are formed simultaneously, the material of the preset channel pillar 60 may also include carbon or polycrystalline silicon. That is, the sacrificial material includes carbon or polycrystalline silicon.

[0131] When the material of the preset channel pillar 60 includes carbon or polycrystalline silicon, the preset channel pillar 60 can be removed more easily when the preset channel pillar is removed to form a channel structure.

[0132] In some embodiments, such as Figure 16 As shown, after step S220, filling the marking holes 31 and the plurality of first channel holes 61 with sacrificial material, the preparation method further includes:

[0133] S230. A chemical mechanical polishing process is used to remove the sacrificial material covering the first stacked structure 20.

[0134] This design serves several purposes. First, it avoids electrical interconnections between multiple channel structures during the subsequent removal of the pre-set channel pillars 60 to form the channel structure. Second, the removal of sacrificial material through chemical mechanical polishing (CMP) flattens the top of the first stacked structure 20, facilitating the formation of a protective layer on the first stacked structure 20. Third, CMP also prevents the sacrificial material from protecting the underlying first stacked structure during subsequent etching of the first sublayer 41, the second sublayer 42, and the first stacked structure 20 below the second sublayer 42 to expose the end 301 of the marker 30 away from the substrate 10, thus preventing the exposure of the end 301 of the marker 30 away from the substrate 10.

[0135] In some embodiments, the orthographic projection of the preset channel pillar 60 on the substrate 10 and the orthographic projection of the mark 30 on the substrate 10 can have the same shape and size. In this way, the mark 30 is smaller, and more marks 30 can be set in the mark area 202, which helps to improve the accuracy of the mask placement, improve the accuracy of OVL measurement of the pattern after development, improve the OVL compensation result, and thus improve the final yield level of the semiconductor structure.

[0136] like Figure 17 As shown, some embodiments of this disclosure provide a mark 30 disposed on a substrate 10 and extending through a first stacked structure 20. The end 301 of the mark 30 remote from the substrate 10 protrudes from the surface of the first stacked structure 20 remote from the substrate 10.

[0137] In some embodiments of this disclosure, the marker 30 penetrates the first stacked structure 20, and the end of the marker 30 protrudes from the first stacked structure 20. Thus, a second stacked structure is deposited on the first stacked structure 20, a hard mask layer is formed on the second stacked structure, and a second mask layer is formed on the hard mask layer. The portion of the second mask layer located in the marker region will have protrusions and depressions. Therefore, during the photolithography process, the photolithography equipment can detect the morphology of the second mask layer located in the marker region 202 and determine the mask placement position based on this morphology. Simultaneously, overlay measurement after the photolithography process can also be performed using the morphology of the second mask layer located in the marker region 202, thereby effectively improving the accuracy of OVL measurement after development, improving OVL compensation results, and ultimately improving the final yield level of the semiconductor structure 100.

[0138] like Figure 18 As shown, in some embodiments, the method for fabricating the semiconductor structure 100 further includes:

[0139] S01, such as Figure 19 As shown, a second stacked structure 70 is formed on the side of the first stacked structure 20 away from the substrate 10. The second stacked structure 70 includes multiple layers of second insulating layers 71 and multiple layers of second sacrificial layers 72 stacked alternately. In the marking region 202, the surface of the second stacked structure 70 away from the substrate 10 has a morphology of protrusions 701 and recesses 702, and the protrusions 701 and the markings 30 are positioned corresponding to each other in a direction perpendicular to the substrate 10.

[0140] It is worth noting that in the method for fabricating the semiconductor structure 100 provided in some embodiments of this disclosure, a first stacked structure 20 is first formed and a preset channel pillar 60 is formed in the first stacked structure 20, and then a second stacked structure 70 is formed. This allows the number of film layers etched each time in the etching process to be reduced when forming the channel structure of the semiconductor structure 100, which is beneficial to improving the morphology of the channel structure and improving the yield of the semiconductor structure 100.

[0141] In some embodiments, such as Figure 20 As shown, the method for fabricating semiconductor structures also includes:

[0142] S02, such as Figure 21 As shown, a hard mask layer 80 is formed on the side of the second stacked structure 70 away from the substrate 10.

[0143] For example, a hard mask layer 80 can be formed by a deposition process.

[0144] For example, the above deposition process can be: chemical vapor deposition, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition, sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD).

[0145] S03, such as Figure 22 As shown, a patterned hard mask layer 80 is provided, which includes a plurality of first openings 81. The orthographic projection of the plurality of first openings 81 on the substrate 10 overlaps with the orthographic projection of the plurality of preset channel pillars 60 on the substrate 10.

[0146] S04, such as Figure 23 As shown, based on the hard mask layer 80, the second stacked structure 70 is etched to form a plurality of second channel holes 703, each second channel hole 703 exposing a preset channel post 60.

[0147] S05, such as Figure 24 As shown, multiple preset channel posts 60 are removed, and a channel structure 90 is formed in the second channel hole 703 and the first channel hole 61 where the preset channel posts 60 are located.

[0148] In some examples, the channel structure 90 may include a barrier layer, a charge storage layer, a tunneling layer, and a channel layer arranged sequentially. The barrier layer prevents charge from being transferred into the gate layer. The charge storage layer covers the barrier layer and stores the charge. The tunneling layer covers the charge storage layer.

[0149] In some embodiments, such as Figure 25 As shown, before step S03 and the patterned hard mask layer 80, the fabrication method further includes:

[0150] S31, such as Figure 26As shown, a second mask layer 51 is formed covering the hard mask layer 80. In the marking region 202, the second mask layer 51 has a morphology of protrusions 511 and recesses 512, with the protrusions 511 and the markings 30 corresponding to each other in a direction perpendicular to the substrate 10.

[0151] For example, the material of the second mask layer 51 may include photoresist.

[0152] S32, such as Figure 27 and Figure 28 As shown, based on the morphology of the second mask layer 51 in the marking region 202, the second mask layer 51 is patterned to form overlay marks 52 and a plurality of second openings 53. The overlay marks 52 are located in the marking region 202, and the orthographic projection of the overlay marks 52 on the substrate 10 is offset from the orthographic projection of the mark 30 on the substrate 10. The plurality of second openings 53 are located in the array region 201 and expose portions of the hard mask layer 80 to be formed with a plurality of first openings 81.

[0153] The number of overprinted marks 52 can be one or more.

[0154] This disclosure does not limit the distribution method and position of the overprinted marks 52 in the marking area 202. For example, when each marking area 202 includes multiple overprinted marks 52, the distance between different overprinted marks 52 can be different, that is, the multiple overprinted marks 52 can be unevenly arranged in the marking area 202.

[0155] The shape of the overlay mark 52 is not limited in this disclosure; in some examples, such as Figure 28 As shown, the orthographic projection of the overlay mark 52 on the substrate 10 can be approximately rectangular. Here, "approximately rectangular" means that the overall orthographic projection of the overlay mark 52 on the substrate 10 is rectangular, but it is not limited to a standard rectangle. That is, the term "rectangle" here includes not only the basic rectangular shape, but also, considering process conditions, shapes similar to rectangles.

[0156] In other examples, the orthographic projection of the overlay mark 52 onto the substrate 10 may be approximately circular. Here, "approximately circular" means that the overall orthographic projection of the overlay mark 52 onto the substrate 10 is circular, but it is not limited to a standard circle. That is, "circular" here includes not only a basic circular shape, but also, considering process conditions, shapes resembling circles.

[0157] In some examples, the overlay mark 52 may be a portion retained after the second mask layer 51 has been patterned. In other examples, the overlay mark 52 may be an opening formed in the second mask layer 51 after it has been patterned.

[0158] In some embodiments, such as Figure 29As shown, after forming the overlay mark 52 and the plurality of second openings 53, and before the patterned hard mask layer 80, the fabrication method further includes:

[0159] S33. Based on the relative positions of the overlay mark 52 and the second mask layer 51 in the marking area 202, check whether the multiple second openings 53 in the direction perpendicular to the substrate 10 correspond to the positions of the multiple preset channel pillars 60.

[0160] S34. Based on the negative test result, remove the second mask layer 51 to form a second mask layer 51 including overlay marks 52 and multiple second openings 53, and perform a test until the test result is positive.

[0161] In this way, by repeatedly checking the relative positional relationship between the overlay mark 52 and the second mask layer 51 in the mark area 202, the accuracy of OVL measurement of the developed pattern is effectively improved, the OVL compensation result is improved, and the final yield of the semiconductor structure is improved.

[0162] like Figure 30 As shown, some embodiments of this disclosure provide a semiconductor structure 100 having an array region 201 and a marker region 202.

[0163] The array region 201 and the marker region 202 of the semiconductor structure 100 correspond to the array region 201 and the marker region 202 of the first stacked structure 20.

[0164] Semiconductor structure 100 includes a substrate 10, a first stacked structure 20, a second stacked structure 70, and a marker 30. The first stacked structure 20, disposed on the substrate 10, includes alternating layers of first insulating layers 21 and multiple layers of first gate layers 23. The second stacked structure 70, disposed on the side of the first stacked structure 20 away from the substrate 10, includes alternating layers of second insulating layers 71 and multiple layers of second gate layers 73. A plurality of channel structures 90 penetrate the first stacked structure 20 and the second stacked structure 70, and are located in an array region 201. The marker 30 penetrates the first stacked structure 20 and is located in a marker region 202. The end 301 of the marker 30 away from the substrate 10 protrudes from the surface of the first stacked structure 20 away from the substrate 10. The marker 30 is the marker 30 described in any of the above embodiments.

[0165] In this configuration, the first gate line layer 23 is replaced by the first sacrificial layer 22, and the second gate line layer 73 is replaced by the second sacrificial layer 72.

[0166] The beneficial effects that the semiconductor structure 100 provided in this disclosure can achieve are the same as those that can be achieved by the preparation method of the semiconductor structure 100 described in any of the above embodiments, and will not be repeated here.

[0167] like Figure 31 As shown, some embodiments of this disclosure provide a three-dimensional memory 200, including a semiconductor structure 100 as described in any of the above embodiments, and peripheral circuitry 300 electrically connected to the semiconductor structure 100. The peripheral circuitry 300 is electrically connected to the semiconductor structure 100 to provide functional support for the semiconductor structure 100, such as reading, writing, and erasing data in the memory cells.

[0168] In some embodiments, such as Figure 31 As shown, the three-dimensional memory 200 also includes an array interconnect layer 400 on the side of the semiconductor structure 100 near the peripheral circuit 300, and the semiconductor structure 100 is electrically connected to the array interconnect layer 400. The peripheral circuit 300 includes a series of circuits 310 such as page buffers, and a peripheral interconnect layer 320 disposed on the side of the series of circuits 310 near the array interconnect layer 400, and the series of circuits 310 is electrically connected to the peripheral interconnect layer 320. The semiconductor structure 100 and the peripheral circuit 300 are electrically connected through the array interconnect layer 400 and the peripheral interconnect layer 320, thereby achieving electrical connection between the semiconductor structure 100 and the series of circuits 310.

[0169] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first stacked structure is formed on a substrate, the first stacked structure comprising alternating stacked multiple layers of first insulating layers and multiple layers of first sacrificial layers; The first stacked structure has an array area and a marker area; A mark is formed in the marking area, the mark penetrating the first stacked structure; A protective layer and a first mask layer are sequentially formed on the side of the first stacked structure away from the substrate; the protective layer includes a first sub-layer located in the array region and a second sub-layer located in the marking region, and the first mask layer exposes the marking region; The second sub-layer is etched based on the first mask layer, so that the thickness of the second sub-layer is less than the thickness of the first sub-layer; Remove the first mask layer; The first sublayer, the second sublayer, and the first stacked structure beneath the second sublayer are etched to expose the end of the mark away from the substrate, while the portion of the first stacked structure located in the array region is still covered by the first sublayer.

2. The preparation method according to claim 1, characterized in that, The film layer closest to the protective layer in the first stacked structure is the first insulating layer; The etching of the first sublayer, the second sublayer, and the first stacked structure beneath the second sublayer includes: The first etching process is used to etch the first sub-layer, the second sub-layer, and the first insulating layer below the second sub-layer until the first sacrificial layer below the first insulating layer is exposed. A second etching process is used to etch the portion of the first sacrificial layer in the marked area that is exposed.

3. The preparation method according to claim 2, characterized in that, The material of the first insulating layer is the same as the material of the protective layer.

4. The preparation method according to claim 2, characterized in that, The first etching process and the second etching process are wet etching processes; The etching solution used in the first etching process includes hydrofluoric acid; and / or, the etching solution used in the second etching process includes phosphoric acid.

5. The preparation method according to claim 1, characterized in that, The film layer closest to the protective layer in the first stacked structure is the first insulating layer; After etching the second sub-layer based on the first mask layer, the sum of the thickness of the second sub-layer and the thickness of the first insulating layer is less than the thickness of the first sub-layer.

6. The preparation method according to claim 1, characterized in that, While forming the mark in the marked area, the preparation method further includes: Multiple preset channel pillars are formed in the array region, and the multiple preset channel pillars penetrate the first stacked structure.

7. The preparation method according to claim 6, characterized in that, Forming the marker and forming the plurality of pre-defined channel posts includes: A marking hole is formed in the marking area, penetrating the first stacked structure, and a plurality of first channel holes are formed in the array area, penetrating the first stacked structure. Sacrificial material is filled into the marking holes and the plurality of first channel holes to form the markings and the plurality of preset channel posts.

8. The preparation method according to claim 7, characterized in that, After filling the marking holes and the plurality of first channel holes with sacrificial material, the preparation method further includes: A chemical mechanical polishing process is used to remove the sacrificial material covering the first stacked structure.

9. The preparation method according to claim 6, characterized in that, Also includes: A second stacked structure is formed on the side of the first stacked structure away from the substrate, the second stacked structure comprising alternating layers of second insulating layers and layers of second sacrificial layers; In the marked area, the surface of the second stacked structure away from the substrate has a raised and recessed morphology, with the raised and marked positions corresponding in a direction perpendicular to the substrate.

10. The preparation method according to claim 9, characterized in that, Also includes: A hard mask layer is formed on the side of the second stacked structure away from the substrate; The hard mask layer is patterned, the hard mask layer includes a plurality of first openings, and the orthographic projection of the plurality of first openings on the substrate overlaps with the orthographic projection of the plurality of preset trench pillars on the substrate; Based on the hard mask layer, the second stacked structure is etched to form a plurality of second channel holes, each second channel hole exposing a preset channel pillar; Remove the plurality of preset channel posts to form a channel structure in the second channel hole and the first channel hole where the preset channel posts are located.

11. The preparation method according to claim 10, characterized in that, Before patterning the hard mask layer, the fabrication method further includes: A second mask layer is formed to cover the hard mask layer; in the marked area, the second mask layer has a morphology of protrusions and depressions, and the positions of the protrusions and the marks correspond to each other in a direction perpendicular to the substrate; Based on the topography of the second mask layer in the marking area, the second mask layer is patterned to form an overlay mark and a plurality of second openings; the overlay mark is located in the marking area, and the orthographic projection of the overlay mark on the substrate is offset from the orthographic projection of the mark on the substrate; the plurality of second openings are located in the array area and expose the portion of the hard mask layer to be formed with a plurality of first openings.

12. The preparation method according to claim 11, characterized in that, After forming the overlay marks and multiple second openings, and before patterning the hard mask layer, the fabrication method further includes: Based on the relative positions of the overlay marks and the second mask layer in the topography of the marked area, check whether the plurality of second openings in the direction perpendicular to the substrate correspond to the positions of the plurality of preset channel pillars; If the test result is negative, the second mask layer is removed to form a second mask layer including overlay marks and multiple second openings, and the test is performed until the test result is positive.

13. The preparation method according to any one of claims 1 to 12, characterized in that, The material of the protective layer includes silicon oxide.

14. The preparation method according to any one of claims 1 to 12, characterized in that, The material of the marking includes carbon or polycrystalline silicon.

15. The preparation method according to any one of claims 1 to 12, characterized in that, The material of the first sacrificial layer is different from the material of the mark. The material of the first sacrificial layer includes silicon nitride, silicon oxide, or polycrystalline silicon.

16. The preparation method according to any one of claims 1 to 12, characterized in that, The material of the first mask layer includes photoresist.

17. A semiconductor structure, characterized in that, The semiconductor structure has an array region and a marking region; The semiconductor structure includes: Substrate; A first stacked structure is disposed on the substrate, comprising alternating stacked multiple layers of first insulating layers and multiple layers of first gate lines; The second stacked structure is disposed on the side of the first stacked structure away from the substrate, and includes multiple layers of second insulating layers and multiple layers of second gate lines that are alternately stacked. Multiple channel structures penetrate the first stacked structure and the second stacked structure, and are located in the array region; A mark extends through the first stacked structure and is located in the marking area; the end of the mark away from the substrate protrudes from the surface of the first stacked structure away from the substrate.

18. A three-dimensional memory, characterized in that, include: The semiconductor structure as described in claim 17; Peripheral circuits electrically connected to the semiconductor structure.

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