An acoustic resonator, its manufacturing method and application

Abstract

This invention relates to an acoustic resonator, which is a fundamental component of an FBAR filter, the FBAR filter including a well-rich layer to avoid parasitic resistance by reducing free charge lifetime. The acoustic resonator has a first electrode, a second electrode, and a piezoelectric layer. The first electrode forms a first plane, the second electrode is disposed parallel to a portion of the first plane, and the piezoelectric layer is disposed between and in contact with the first and second planar electrodes. A silicon-based support layer including a well-rich region is bonded to the second electrode. The acoustic resonator can be manufactured by: (a) depositing the well-rich region on the silicon-based support layer; (b) oxidizing the surface of the well-rich region; (c) depositing a bonding layer on the oxidized surface of the well-rich region; (d) bonding the first electrode to one side of the silicon-based oxide layer containing the well-rich layer; (e) contacting the first electrode with a first side of the piezoelectric layer; and (f) contacting the second electrode with a second side of the piezoelectric layer.

Description

Background Technology

[0001] Wireless communication devices, such as cellular phones, typically include radio frequency (RF) filters to improve both signal reception and transmission. RF filters can select desired frequencies while rejecting unwanted ones, enabling band selection and allowing the cellular phone to process only the intended signal. A preferred filter system utilizes piezoelectric-based resonators because these systems facilitate overall system miniaturization. In piezoelectric-based resonators, acoustic resonance modes are generated in the piezoelectric material. Sound waves are converted into electrical signals for use in electrical applications.

[0002] Two common types of acoustic resonators are surface acoustic wave (SAW) resonators and bulk acoustic wave (BAW) resonators. In a SAW resonator, the acoustic signal is carried by surface waves. In a BAW resonator, the acoustic signal is carried through the bulk of the resonator diaphragm. One type of BAW is the diaphragm bulk acoustic resonator (FBAR). An FBAR consists of an acoustic stack having a layer of piezoelectric material disposed between two electrodes. Sound waves achieve resonance across the acoustic stack, where the resonant frequency of the wave is determined by the materials constituting the stack and their arrangement. FBARs typically resonate at gigahertz (GHz) frequencies.

[0003] The FBAR and manufacturing method are presented in U.S. Patent No. 10,389,331B2, entitled "Single Crystal Piezoelectric RF Resonators and Filters," by the applicant of this patent application, Dror Hurwitz. The entire contents of US10,389,331B2 are incorporated herein by reference.

[0004] Silicon is the most common material in the semiconductor industry and is widely used in silicon-based semiconductor manufacturing plants. Silicon's thermal expansion coefficient is ideally suited as a base substrate for FBARs. Silicon wafers in diameters of 6 inches, 8 inches, and 12 inches are inexpensive and readily available. The ease of operation of MEMS (Micro-Electro-Mechanical Systems) components (such as TSVs (Through Silicon Vias) for membrane release) further supports silicon as a base substrate for FBAR filters. Currently, the vast majority of FBARs are built on silicon. Although FBARs can be fabricated on other insulating materials, these alternatives do not possess the advantages of silicon. For all these reasons, it makes sense to use Si. However, silicon is conductive. Even when using high-resistivity silicon (HR-Si), conductivity can still cause a decrease in FBAR performance.

[0005] Using SiO2 for film release provides an opportunity to generate a fully isolated substrate. The isolation layer is constructed on a high-resistivity silicon substrate. However, the HR-Si oxide substrate is affected by parasitic surface conduction due to the attraction of fixed oxide charges on free carriers near the Si / SiO2 interface.

[0006] When high-resistivity silicon is used as a substrate to form inversion or accumulation regions, parasitic surface conduction problems arise because the signal voltage in the active structure affects free carriers. The degree of charge carrier displacement in the inversion or accumulation regions is directly affected by the signal in the active structure. Therefore, the parasitic capacitance between the substrate layer and the active structure depends on the electric field originating from the active structure. This capacitance leads to nonlinearity in the FBAR filter and increased insertion loss, as well as a loss of signal purity. Furthermore, the electric field can reverse this interface on the side of the substrate layer and generate a channeling effect in the inversion or accumulation regions, allowing free carriers to move in the lateral direction, even though the substrate layer 101 is high-resistivity. This effect can lead to signal attenuation and crosstalk in RF communication circuits, and the Q (quality) factor of the FBAR filter will decrease. Summary of the Invention

[0007] This document discloses an acoustic resonator as a component of an FBAR filter. The acoustic resonator has a first electrode, a second electrode, and a piezoelectric layer. The first electrode has a first planar portion, and the second electrode has a second planar portion disposed parallel to the first planar portion. The piezoelectric layer is disposed between and in contact with the first and second planar portions. A silicon-based support layer is present and bonded to the second electrode. This support layer has well-rich regions that reduce the lifetime of free charge carriers.

[0008] An acoustic resonator can be manufactured by: (a) depositing a well-rich region on a substrate, wherein the well-rich region effectively reduces the lifetime of free charge carriers; (b) oxidizing the surface of the well-rich region; (c) depositing a bonding layer on the oxide surface of the well-rich region; (d) bonding a first electrode to the bonding layer, the first electrode having a first planar portion; (e) contacting a first side of a piezoelectric layer with the first planar portion; and (f) contacting a second side of a piezoelectric layer with the first planar portion of a second electrode. Attached Figure Description

[0009] Figure 1 This refers to an FBAR filter with parasitic surface conduction, as known in the prior art.

[0010] Figure 2 An FBAR filter with a well-rich layer is used to avoid parasitic surface conduction.

[0011] Figure 3 This is a flowchart illustrating the process steps for manufacturing an FBAR filter with a well-rich layer.

[0012] Figure 4 This is a cross-sectional view of a high-resistivity silicon substrate, also known as a carrier wafer.

[0013] Figure 5 This is a cross-sectional view of the well-rich layer deposited on the carrier wafer.

[0014] Figure 6 This is a cross-sectional view of the buried oxide layer formed on the surface of the well-rich layer.

[0015] Figure 7 This is a cross-sectional view of the gold bonding layer formed on the surface of the buried oxide layer.

[0016] Figure 8 This is a cross-sectional view of the active stack bonded to the carrier wafer.

[0017] Figure 9 For the FBAR filter during the temporary assembly step, where the sapphire support layer has been removed.

[0018] Figure 10 This is a temporary assembly step following the removal of the gallium nitride layer.

[0019] Figure 11 To trim the piezoelectric layer to achieve the desired filter performance.

[0020] Figure 12 The back-end of the line (BEOL) is processed to provide electrical interconnection for the piezoelectric layer.

[0021] Figure 13 BEOL treatment is used to form an acoustic cavity beneath the piezoelectric layer.

[0022] Figure 14 Another BEOL treatment was performed to remove the remaining passivation layer and gold bonding layer from the acoustic cavity.

[0023] Figure 15 The cap bond is used to seal the acoustic cavity.

[0024] Figure 16 The image is a micrograph showing the surface roughness of the buried oxide layer when the well-rich layer is amorphous silicon.

[0025] Figure 17 The image is a micrograph showing the surface roughness of the buried oxide layer when the well-rich layer is polycrystalline silicon.

[0026] Figure 18 Organic-based wafer-level packaging for encapsulating FBAR filters. Detailed Implementation

[0027] Figure 1This is an FBAR filter 100 known from the prior art. This prior art FBAR filter 100 has the risk of parasitic surface conduction. In this FBAR filter 100, a substrate layer 101 is formed of high resistivity silicon. Inversion or accumulation regions 110 appear because the charge carriers are affected by the signal voltage of the active resonator structure 103. The inversion region is a conduction channel 104, which connects the two n-type regions of the source and drain, thereby allowing the free flow of electron charge. The accumulation region blocks the flow of electron charge through the conduction channel, causing them to accumulate on the surface adjacent to the channel 104. The magnitude and change of the displacement of the charge carriers in region 110 are directly related to the signal in the active structure 103. Therefore, the capacitance of the SiO2 buried oxide (BOX) layer 102 between the substrate layer 101 and the active resonator structure 103 depends on the electric field originating from the active resonator structure 103.

[0028] This capacitance causes nonlinearity in the FBAR filter 100 and an increase in insertion loss, along with a loss of signal purity. Furthermore, the electric field can reverse this interface on the side of the substrate layer 101, thereby creating a conductive path 104 within region 110, where charges can easily move in the lateral direction L, despite the high resistance of the substrate layer 101. This effect can lead to signal attenuation and crosstalk in RF communication circuits, and the Q factor of the FBAR filter 100 will decrease.

[0029] Figure 2 An FBAR filter 120 with a well-rich layer is shown to avoid parasitic surface conduction. A high-resistivity silicon substrate has a resistivity exceeding 3000 ohms*cm. To prevent charging side effects between the high-resistivity silicon substrate 101 and the SiO2 buried oxide (BOX) layer 102, a well-rich layer 112 (such as amorphous silicon (a-Si) or polycrystalline silicon (multi-Si)) is formed within region 110. This well-rich layer 112 has a thickness between 500 nanometers (nm) and 800 nm. The well-rich layer 112 prevents the entry of charge carriers attracted at the Si surface 114. Parasitic surface conduction is effectively interfered with because the well-rich layer significantly reduces the lifetime of free charge carriers in region 110. Because the charge carriers fail to migrate far before being trapped, the effective resistivity of the substrate 101 is preserved, and the capacitance is independent of the signal in the active resonator structure 103. Therefore, the quality factor (Q) of the FBAR filter 120 is improved.

[0030] Figure 3 This is a flowchart illustrating one embodiment of the process steps for manufacturing an FBAR filter with a well-rich layer. Figure 4As shown, the first process step is the fabrication of a high-resistivity silicon substrate 101, also referred to as a carrier wafer. The substrate is a silicon wafer having an exemplary diameter of 150 mm + / - 0.2 mm and a thickness of 1000 μm + / - 15 μm. The silicon may be doped to P-type or N-type, and it has… <l-0-0>Crystal orientation of + / -0.05°. Crystal orientation is <1-1-0>. Other exemplary properties include resistivity exceeding 5000 ohm-cm, total thickness deformation less than 5 μm, warpage less than 50 μm, and bowing less than 50 μm.

[0031] refer to Figure 3 and Figure 5 A well-rich layer 112 is deposited on a carrier wafer 101. The well-rich layer 112 may be amorphous silicon or polycrystalline silicon deposited by a process such as low-pressure chemical vapor deposition (LPCVD), such that the compressive stress of the deposited layer is between -200 MPa and -400 MPa. An exemplary thickness of the well-rich layer is 650 nm + / - 50 nm.

[0032] refer to Figure 3 and Figure 6 A buried oxide SiO2 layer 102 is formed in the surface 116 of the well-rich layer 112. The oxide layer is formed to a thickness of 400 nm ± 40 nm, resulting in an unoxidized portion of the well-rich layer of 330 nm ± 30 nm. Figure 16 and Figure 17 The micrographs show that when the well-rich layer is amorphous silicon, the surface roughness of the oxide (Ra) is less than 2.8 nm, as measured by atomic force measurement with a measurement area of ​​10 μm × 10 μm. When the well-rich layer is polycrystalline silicon, the surface roughness of the oxide (Ra) is less than 9.0 nm, as measured by atomic force measurement with a measurement area of ​​10 μm × 10 μm. Both micrographs are magnified 20,000 times.

[0033] refer to Figure 3 and Figure 7 A gold bonding layer 118(b) is formed on the surface 124 of the buried oxide SiO2 layer 102. Typically, the gold bonding layer has a thickness between 50 nanometers (nm) and 500 nm and is deposited via a physical vapor deposition (PVD) process, such as electron beam evaporation or sputtering. To enhance the adhesion of the gold bonding layer 118(b), a thin adhesive layer (e.g., such as titanium) with a nominal thickness in the range of 10 nm to 50 nm may be deposited on the surface 124 prior to the deposition of the gold bonding layer 118(b).

[0034] Return to reference Figure 3 An active stack 126 is formed parallel to the substrate assembly. The active stack 126 includes a sapphire wafer on which a gallium nitride layer is deposited. A piezoelectric layer (such as aluminum nitride or scandium-doped aluminum nitride) is deposited on the GaN layer. A conductive layer 136 is formed on the piezoelectric layer to provide conductivity to the piezoelectric layer and to enhance bonding to the substrate assembly.

[0035] A gold bonding layer 118(a) is formed on the surface of the conductive layer 136. Typically, the gold bonding layer has a thickness between 50 nm and 500 nm and is deposited via a PVD process, such as electron beam evaporation or sputtering. To enhance the adhesion of the gold bonding layer 118(a), a thin adhesive layer (such as titanium) with a nominal thickness in the range of 10 nm to 50 nm may be deposited on the surface of the conductive layer 136 prior to the deposition of the gold bonding layer 118(a). The gold bonding layer 118(a) on the wafer stack 126 of the sapphire support substrate 130 is then bonded to the gold bonding layer 118(b) of the carrier wafer stack 128.

[0036] Figure 8 A cross-sectional view of the active stack 126 bonded to the carrier wafer assembly 128 is shown. A sapphire support layer 130 supports a GaN layer 132, which in turn supports a piezoelectric layer 134. Typically, the piezoelectric layer is composed of single-crystal aluminum nitride or single-crystal scandium-doped aluminum nitride having an exemplary thickness of 200 nm to 1000 nm. A conductive layer 136 (typically molybdenum) is deposited on the piezoelectric layer 134. The conductive layer 136 may be formed of other metals, such as tungsten or ruthenium.

[0037] It can also utilize one or more alloys that are primarily (by weight) molybdenum, tungsten, and ruthenium.

[0038] Return to reference Figure 3 After the active stack 126 is bonded to the carrier wafer assembly 128, the sapphire support layer 130 is removed, as described in flowchart step 140. The detachment of the sapphire support layer is performed by processes such as laser lift-off or polishing, and yields a result as described in the flowchart. Figure 9 The structure shown.

[0039] refer to Figure 3 and Figure 10 Gallium nitride layer removal, such as in flowchart step 142, involves cleaning the surface residue of piezoelectric layer 134 using methods such as inductively coupled plasma (ICP). (See reference...) Figure 3 and Figure 11 The piezoelectric layer 134 is then trimmed to the desired length, width, and thickness for the desired filter performance. Generally, the tolerance for each dimension is approximately + / - 3 nm.

[0040] Figure 3 and Figures 12 to 14 The BEOL process 148 is shown. Figure 12 A BEOL process is illustrated to provide electrical interconnection for trimming the piezoelectric layer 134. A passivation layer 156 is deposited on selected portions of the top surface of the carrier wafer stack 128 and on the sides and desired portions of the top of the piezoelectric layer 134 to prepare for the deposition of the second electrode material 150. The passivation layer 156 is preferably a SiO2 layer, selectively deposited on most of the surface except for the central portion 158 of the piezoelectric layer 134. To minimize damage to the surface of the piezoelectric layer 134, the SiO2 layer 156 is obtained with an exemplary thickness of 2.5 μm + / - 0.1 μm using a low-temperature plasma deposition process. The film stress is preferably less than 50 MPa. Low-temperature plasma deposition also eliminates residual photoresist / polymer contamination on the surface.

[0041] While the second electrode material 150 is typically molybdenum, other metals such as tungsten or ruthenium may also be used. Alloys primarily (by weight) composed of one or more of molybdenum, tungsten, and ruthenium may also be used. An exemplary thickness of the second electrode material is 200 nm. The second electrode material is deposited via processes such as low-temperature (150°C) sputtering or other PVD processes to obtain a high-quality deposit characterized by high density, low stress (less than 100 MPa), and a sheet resistance of Rs = less than 0.5 + / - 0.05 ohms / square.

[0042] A portion of the passivation layer 156 is etched to expose a portion of the first electrode material 136, thereby enabling contact with the second electrode material 150 in the contact region 154. The contact region 154 is electrically isolated from the top surface 152 of the piezoelectric layer 134, thereby providing electrical interconnection to the bottom surface 160 of the piezoelectric layer. The gold bonding layer 161 will provide electrical interconnection to external devices.

[0043] Figure 13 The back-end processing of the circuitry is shown to provide an acoustic cavity 162 beneath the piezoelectric layer 134. The top surface sacrificial layer 164 is typically a standard-quality non-piezoelectric aluminum nitride and is deposited to a thickness of 100 nm ± 10 nm. A temporary silicon substrate 166 is bonded to the top surface sacrificial layer 164 and provides stiffness. This stiffness enables a depth silicon etching (DSE) of approximately 4000 angstroms through the high-resistivity silicon substrate 101 and the well-rich layer 112.

[0044] Figure 14 Another BEOL process is shown, which removes the remaining passivation layer and gold bonding layer 118(b) from cavity 162. Chemical etching (such as diluted hydrofluoric acid (HF)) removes the remaining passivation layer, while a solution (such as KI / I2) removes the gold bonding layer 118(a) from below the central portion 158.

[0045] refer to Figure 3 and Figure 15 The cap bonding process 168 seals the acoustic cavity 162. The silicon cap 170 is bonded to the silicon substrate, such as with an organic adhesive 172. The stiffness provided by the silicon cap 170 enables the top surface sacrificial layer and temporary silicon substrate ( Figure 13 The removal of the icons 164 and 166 in the image.

[0046] Acoustic resonators are typically packaged to provide electrical interconnection to external devices or circuit boards and to provide environmental protection. A suitable package is formed from a polymer resin, as described in U.S. Patent Application Publication No. US2021 / 0028766A1 entitled "Packages with Organic Back Ends for Electronic Components" by Hurwitz et al. The entire disclosure of US2021 / 0028766A1 is incorporated herein by reference.

[0047] Figure 18 An organic-based wafer-level package 80 encapsulating a piezoelectric layer 20 is shown. This organic-based wafer-level package 80 may be a component of an FBAR filter. An organic wall 82 (formed from a polymer, such as a photosensitive material used for permanent structure formation) includes vias coated with under-bump metal 84 (UBM), which is formed from a conductive material, such as nickel or copper. The UBM 84 provides electrical interconnection for the first and second electrode layers of the FBAR filter. An organic cap layer 86 has extended vias coated with continuous UBM 84. Solder bumps 88 (such as a tin / silver alloy) fill the remainder of the vias and extend beyond the surface 90 of the organic cap layer 86 for attachment and electrical interconnection to a device or circuit board.

Claims

1. An acoustic resonator, comprising: A first electrode, the first electrode having a first planar portion; The second electrode has a second planar portion that is configured to be parallel to the first planar portion; A piezoelectric layer is disposed between and in contact with the first planar portion and the second planar portion; and A support layer, which is bonded to the second electrode, has a well-rich layer that reduces the lifetime of free charges; The SiO2 layer is inserted between the well-rich layer and the first electrode and the second electrode.

2. The acoustic resonator according to claim 1, wherein the well-rich layer is selected from one or both of amorphous silicon and polycrystalline silicon.

3. The acoustic resonator according to claim 2, wherein the well-rich layer has a thickness of 500 nm to 800 nm.

4. A method for manufacturing an acoustic resonator, the method comprising the following steps: a) Deposit a well-rich layer on a first side of a first substrate; b) Oxidize the surface of the well-rich layer, which effectively reduces the lifetime of free charges; c) Deposit the first bonding layer on the oxide surface of the well-rich layer; d) Bonding the first side of the first electrode having a first planar portion to the first bonding layer; e) Make the first side of the piezoelectric layer contact the first planar portion; f) Make the second side of the piezoelectric layer contact the first planar portion of the second electrode; The SiO2 layer is inserted between the well-rich layer and the first electrode and the second electrode.

5. The method of claim 4, wherein the first substrate is selected as a silicon-based substrate wafer, and the well-rich layer is selected as amorphous silicon or polycrystalline silicon.

6. The method of claim 5, wherein the silicon substrate wafer is selected as a high-resistivity wafer having a resistivity higher than 3000 Ω*cm.

7. The method of claim 6, wherein the well-rich layer is deposited to a thickness between 500 nm and 800 nm.

8. The method of claim 7, wherein the oxidation of the well-rich layer comprises partially oxidizing the surface of the well-rich layer by one or more methods of thermal oxidation, mechanical polishing, and thermal stress relief to form a SiO2 layer.

9. The method of claim 6, wherein the oxide layer on the opposite second side of the silicon substrate wafer is removed by one or more methods such as polishing, chemical etching, and plasma dry etching.

10. The method of claim 4, wherein step (d)-bonding further comprises: The piezoelectric layer and the first electrode are deposited on a second substrate, wherein the piezoelectric layer is adjacent to the second substrate and the opposite second side of the first electrode is adjacent to the piezoelectric layer; A second bonding layer is deposited on the first side of the first electrode; and The first bonding layer is fused to the second bonding layer.

11. The method of claim 10, further comprising selecting the first bonding layer and the second bonding layer as gold or a gold-indium alloy.

12. The method of claim 11, wherein the first bonding layer and the second bonding layer are deposited by one or more techniques selected from electron beam evaporation, sputtering, and molecular beam epitaxy.

13. The method of claim 12, further comprising depositing an adhesive layer between the first bonding layer and the first electrode, and between the second bonding layer and the oxide surface of the well-rich layer.

14. The method of claim 13, further comprising selecting the adhesive layer as titanium or a titanium-tungsten alloy.

15. The method of claim 12, further comprising selecting sapphire as the second substrate.

16. An organic-based wafer-level package including an acoustic resonator, the organic-based wafer-level package comprising: The acoustic resonator has: A first electrode, the first electrode having a first planar portion; The second electrode has a second planar portion that is configured to be parallel to the first planar portion; A piezoelectric layer is disposed between and in contact with the first planar portion and the second planar portion; and A support layer, the support layer being bonded to the second electrode, the support layer having a well-rich layer, the well-rich layer reducing the lifetime of free charges; An organic wall, the organic wall contacting a first side of the piezoelectric layer, wherein a first wall through-hole extends through the organic wall and contacts the first electrode, and a second wall through-hole extends through the organic wall and contacts the second electrode; An organic top cover having first and second opposing sides, wherein the first opposing side is bonded to the organic wall, a first top cover through-hole is aligned with a first wall through-hole and a second top cover through-hole is aligned with a second wall through-hole, wherein the combination of the organic wall, the organic top cover and the first planar portion defines a first acoustic cavity; A silicon substrate substrate, wherein the silicon substrate substrate contacts a second side of the piezoelectric layer; and A silicon cap bonded to the silicon substrate, wherein the combination of the silicon substrate, the silicon cap, and the second planar portion defines a second acoustic cavity.

17. The organic-based wafer-level package of claim 16, wherein the well-rich layer is selected from one or two of the group consisting of amorphous silicon and polycrystalline silicon.

18. The organic-based wafer-level package of claim 17, wherein the well-rich layer has a thickness of 500 nm to 800 nm.

19. The organic-based wafer-level package of claim 18, wherein the SiO2 layer is interposed between the well-rich layer and both the first electrode and the second electrode.

20. A method for manufacturing organic-based wafer-level packaging, the method comprising the following steps: An acoustic resonator is provided, the acoustic resonator having a first electrode, a second electrode, a piezoelectric layer and a support layer, the first electrode having a first planar portion, the second electrode having a second planar portion disposed parallel to the first planar portion, the piezoelectric layer being disposed between and in contact with the first planar portion and the second planar portion, the support layer being bonded to the second electrode, the support layer having a well-rich layer, the well-rich layer reducing the lifetime of free charges; and Encapsulate one or more acoustic resonators in an organic wafer-level package; The SiO2 layer is inserted between the well-rich layer and the first electrode and the second electrode.

21. The method of claim 20, wherein the encapsulation step comprises: The organic wall material is bonded to the acoustic resonator; An organic top cover is bonded to the organic wall, such that the combination of the organic wall and the organic top cover defines a first acoustic cavity adjacent to the second electrode; A silicon-based substrate is bonded to the acoustic resonator; and A silicon cap is bonded to the silicon substrate such that the combination of the silicon substrate and the silicon cap defines a second acoustic cavity adjacent to the first electrode.

22. The method of claim 21, further comprising extending a first conductive material through-hole through both the organic wall and the organic top cover to electrically interconnect the second electrode to an external device and circuit, and extending a second conductive material through-hole through both the organic wall and the organic top cover to electrically interconnect the first electrode to an external device and circuit.

23. The method of claim 22, further comprising selecting the support layer as a silicon-based wafer and the well-rich layer as amorphous silicon or polycrystalline silicon.

24. The method of claim 23, wherein the silicon-based carrier wafer is selected to have a resistivity higher than 3000 Ω*cm.

25. The method of claim 24, wherein the well-rich layer is deposited to a thickness between 500 nm and 800 nm.

26. The method of claim 25, wherein the oxidation of the well-rich layer comprises partially oxidizing the surface of the well-rich layer by one or more of thermal oxidation, mechanical polishing, and thermal stress relief, thereby forming a SiO2 layer.

27. The method of claim 20, further comprising: The piezoelectric layer and the first electrode are deposited on a second substrate, wherein the piezoelectric layer is adjacent to the second substrate and the opposite second side of the first electrode is adjacent to the piezoelectric layer; A second bonding layer is deposited on the first side of the first electrode; and The first bonding layer is fused to the second bonding layer.

28. The method of claim 27, further comprising selecting the first bonding layer and the second bonding layer as gold or a gold-indium alloy.

29. The method of claim 28, wherein the first bonding layer and the second bonding layer are deposited by one or more techniques selected from electron beam evaporation, sputtering, and molecular beam epitaxy.

30. The method of claim 29, further comprising depositing an adhesive layer between the first bonding layer and the first electrode, and between the second bonding layer and the oxide surface of the well-rich layer.

31. The method of claim 30, further comprising selecting the adhesive layer as titanium or a titanium-tungsten alloy.

32. The method of claim 31, further comprising selecting sapphire as the second substrate.

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