A memristor emulator circuit

Abstract

The present invention discloses a memristor simulator circuit, including a current transmitter A, a field effect tube M, a resistor R1, a resistor Rf, a resistor RD, a capacitor C, a positive voltage source Vp, and a negative voltage source Vn. i They are respectively connected to the X end of the current conveyor A and one end of the resistor RD, the other end of the resistor RD is connected to the drain D end of the field effect tube M, the source S end of the field effect tube M is grounded, the gate G end of the field effect tube M is respectively connected to the output O end of the current conveyor A and one end of the resistor Rf, the other end of the resistor Rf is respectively connected to the Y end of the current conveyor A and one end of the resistor R1, and the other end of the resistor R1 is grounded. The Z end of the current conveyor A is connected to one end of the capacitor C, and the other end of the capacitor C is grounded.

Description

Technical Field

[0001] The invention relates to a memristor simulation model and belongs to the field of circuit design. Background Art

[0002] In 1971, Chua deduced from the symmetry theory that in addition to resistance R, inductance L and capacitance C, there is a fourth basic circuit element - memristor. Theoretical research on memristors continued until 2008, when HP Labs discovered the first nanoscale memristor with a P_t-TiO_2-P_t sandwich structure. On the one hand, memristors have the potential to realize storage and computing devices, and are one of the most powerful devices to break through the "storage wall" between CPU and memory in the existing computer architecture; on the other hand, memristors are also one of the best choices for the physical realization of neural synapses in brain-like neural networks. These two important advantages of memristors have attracted countless scientific researchers to conduct memristor research. Since there are no public memristor physical devices for sale on the market, memristor emulator circuits are one of the important means for many memristor researchers to conduct research and teaching on memristors. Existing memristor emulator circuits can be generally divided into digital and analog types. Digital memristor emulator circuits use FPGA or single-chip microcomputers to control voltage and current using discrete methods to simulate memristor characteristics. The disadvantage of digital memristor circuits is that the maximum operating frequency of the memristor is limited by the system clock and sampling frequency, and cannot be very high. Analog memristor emulator circuits can be divided into passive analog types composed of passive components and active analog memristor emulator circuits constructed by active devices. The disadvantages of passive analog memristor emulator circuits are low operating frequency and difficulty in constructing nonlinear resistors; although the operating frequency of active analog memristor emulator circuits is much higher than that of passive analog memristor emulator circuits, the topological structure of active analog memristor emulator circuits is complex and difficult to analyze and control. Summary of the invention

[0003] The technical problem to be solved by the present invention is to realize an active analog memristor emulator circuit using a simple circuit topology. The memristor emulator circuit uses a current conveyor A to construct an integrator, and then uses the output v of the current conveyor g Controlling the conductive channel resistance between the drain D and source S of the field effect transistor realizes the simulation of the memristor.

[0004] The present invention adopts the following technical solutions to solve the above technical problems:

[0005] A memristor emulator circuit is characterized by comprising a current transmitter A, a field effect transistor M, a resistor R1, a resistor Rf, a resistor RD, a capacitor C, a positive voltage source Vp, and a negative voltage source Vn.

[0006] Input v iThey are respectively connected to the X end of the current conveyor A and one end of the resistor RD, the other end of the resistor RD is connected to the drain D end of the field effect tube M, the source S end of the field effect tube M is grounded, the gate G end of the field effect tube is respectively connected to the output O end of the current conveyor A and one end of the resistor Rf, the other end of the resistor Rf is respectively connected to the Y end of the current conveyor A and one end of the resistor R1, and the other end of the resistor R1 is grounded.

[0007] The Z terminal of the current conveyor A is connected to one end of the capacitor C, and the other end of the capacitor C is grounded.

[0008] Furthermore, the current i in the resistor Rf f Compared to the current i in resistor R1 Y Can be ignored.

[0009] Furthermore, the voltage v at the X terminal of the current conveyor A is i 、X terminal current i X 、Y terminal voltage v Y 、Y terminal current i Y 、Z terminal voltage v Z 、Z terminal current i Z 、O terminal voltage v g Satisfies the formula, where β is a constant coefficient:

[0010]

[0011] Furthermore, the current conveyor A, the resistor R1, the resistor Rf, the capacitor C, the positive voltage source Vp, and the negative voltage source Vn form a pair of input v i The integrator output

[0012] Furthermore, the on-resistance of the conductive channel between the drain D and source S of the field effect transistor M is affected by v g control.

[0013] Furthermore, the drain current i of the field effect tube i It includes the current in the conductive channel between the drain D end and the source S end of the field effect transistor M and the current in the parasitic diode between the drain D end and the source S end of the field effect transistor M and the substrate. The substrate of the field effect transistor M is connected to the source S end of the field effect transistor.

[0014] Further, when inputting v i is a sinusoidal signal, the drain current i of the field effect tube M i With the input signal v i The relationship curve shows the characteristics of a hysteresis loop.

[0015] Further, when inputting v i is a sinusoidal signal, the drain current i of the field effect tube M iWith the input signal v i The relationship curve will change with the input signal v i It gradually shrinks with the increase of frequency and finally shrinks into a single-valued function curve.

[0016] Furthermore, at the sinusoidal input v i When the frequency exceeds 1MHz, the memristor emulator circuit can still maintain the memristor characteristics.

[0017] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0018] 1. The memristor emulator circuit has a simple topology and is easy to implement;

[0019] 2. The working process of the memristor emulator circuit is easy to analyze and control;

[0020] 3. The field effect transistor M in the memristor simulator circuit can be a P-channel or N-channel field effect transistor;

[0021] 4. The X-terminal current i of the memristor emulator current transmitter A X Compared with the memristor input current i i Can be ignored;

[0022] 5. Input signal v of memristor simulator i The frequency is greater than 1MHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a memristor emulator circuit;

[0024] Figure 2 Yes When i (t),i i (t), v g (t) waveform;

[0025] Figure 3 Yes When f=1MHz, 2MHz and 4MHz, i i (t)~v i (t) waveform.

[0026] Figure 4 Yes When i (t),i i (t), v g (t) waveform;

[0027] Figure 5 Yes When f=1MHz, 1.5MHz and 2MHz, i i (t)~vi (t) waveform. DETAILED DESCRIPTION

[0028] The embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0029] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless defined as herein.

[0030] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0031] Example 1

[0032] Take the current transmitter A as AD844S, R1 as 300Ω, C as 200pF, Vp=10V, Vn=-10V, field effect tube M as P-channel MOSFET 3N190, RD as 3kΩ, and Rf as 20MΩ. When i (t),i i (t), v g The waveform of (t) is as follows Figure 2 shown.

[0033] Output of current conveyor A:

[0034]

[0035] The drain current of the field effect transistor is i It is mainly composed of two parts: the first part of the current is the current i in the conductive channel when the conductive channel between the drain D and the source S of the field effect tube M is turned on. c The second part of the current is the parasitic diode current i between the drain of the field effect transistor M and the substrate (which is connected to the source S terminal of the field effect transistor M) d .

[0036] According to the IV relationship formula of the P-channel field effect tube, it can be known that when v g >V th When c =0; when vg ≤V th When the field effect tube is in the variable resistance area:

[0037] i c =k p *(v g -i c *RS-V th )[v i -i c *(RD+RD2+RS)]-0.5*kp*[v i -i c *(RD+RD2+RS)] 2 ;

[0038] When v g ≥V th When the field effect tube is in the saturation region:

[0039] i c =0.5*k p *(v g -i c *RS-V th ) 2 .

[0040] Here, V th is the threshold voltage of field effect tube M (3N190), k p is the transconductance coefficient of the field effect transistor M, RD2 is the drain body resistance of the field effect transistor M, and RS is the source body resistance of the field effect transistor M.

[0041] According to the IV relationship formula of the diode, it can be known that the current in the parasitic diode between the drain D terminal of the field effect transistor M and the substrate (which is connected to the source S terminal of the field effect transistor M) is,

[0042]

[0043] Here, I s is the diode reverse saturation leakage current, v d is the diode forward voltage drop, V T Take 26mV at room temperature.

[0044] The final FET drain current is:

[0045] i i =i c +i d .

[0046] In taking When f=1MHz, 2MHz and 4MHz, i i (t)~v i The waveform of (t) is as follows Figure 3 As shown. On the one hand, i i (t)~v i The waveform of (t) shows the characteristics of a pinch hysteresis curve; on the other hand, as the input signal v i The frequency changes from 1MHz to 2MHz and finally increases to 4MHz. i (t)~v i The waveform of (t) is finally compressed to a single-valued function curve. The above two aspects can show that the circuit is a memristor emulator circuit.

[0047] Example 2

[0048] Take the current transmitter A as AD844S, R1 as 200Ω, C as 200pF, Vp=10V, Vn=-10V, field effect tube M as N-channel MOSFET CSD15380F3, and RD as 1kΩ. When i (t),i i (t), v g The waveform of (t) is as follows Figure 4 As shown. When f=1MHz, 1.5MHz and 2MHz, i i (t)~v i The waveform of (t) is as follows Figure 5 shown.

[0049] Output of op amp A:

[0050]

[0051] The drain current of the field effect transistor is i It is mainly composed of two parts: the first part of the current is the current i in the conductive channel when the conductive channel between the drain D and the source S of the field effect tube M is turned on. c The second part of the current is the parasitic diode current i between the source of the field effect transistor M and the substrate (which is connected to the source S terminal of the field effect transistor M) d .

[0052] According to the IV relationship formula of the field N-channel effect tube, it can be known that when v g <V th When c =0; when v g ≥V th When the field effect tube is in the variable resistance area:

[0053] i c =k n *(v g -i c *RS-V th)[v i -i c *(RD+RD2+RS)]-0.5*k n *[v i -i c *(RD+RD2+RS)] 2 ;

[0054] When v g ≥V th When the field effect tube is in the saturation region:

[0055] i c =0.5*k n *(v g -i c *RS-V th ) 2 .

[0056] Here, V th is the threshold voltage of field effect tube M (CSD15380F3), k n is the transconductance coefficient of the field effect transistor M, RD2 is the drain body resistance of the field effect transistor M, and RS is the source body resistance of the field effect transistor M.

[0057] According to the IV relationship formula of the diode, it can be known that the parasitic diode current i between the source of the field effect transistor M and the substrate (which is connected to the source S terminal of the field effect transistor M) is d for,

[0058]

[0059] Here, I s is the diode reverse saturation leakage current, v d is the diode forward voltage drop, V T Take 26mV at room temperature.

[0060] The final FET drain current is:

[0061] i i =i c +i d .

[0062] In taking When f=1MHz, 1.5MHz and 2MHz, i i (t)~v i The waveform of (t) is as follows Figure 5 As shown. On the one hand, i i (t)~v i The waveform of (t) shows the characteristics of a pinch hysteresis curve; on the other hand, as the input signal v iThe frequency changes from 1MHz to 1.5MHz and finally increases to 2MHz. i (t)~v i The waveform of (t) is finally compressed to a single-valued function curve. The above two aspects can show that the circuit is a memristor emulator circuit.

[0063] The above description is only a specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any person familiar with the technology can understand and think of any changes or substitutions within the technical scope disclosed by the present invention, which should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A memristor emulator circuit, characterized in that: It includes a current transmitter A, a field effect transistor M, a resistor R1, a resistor Rf, a resistor RD, a capacitor C, a positive voltage source Vp, and a negative voltage source Vn; Input v i They are respectively connected to the X end of the current conveyor A and one end of the resistor RD, the other end of the resistor RD is connected to the drain D end of the field effect tube M, the source S end of the field effect tube M is grounded, the gate G end of the field effect tube is respectively connected to the output O end of the current conveyor A and one end of the resistor Rf, the other end of the resistor Rf is respectively connected to the Y end of the current conveyor A and one end of the resistor R1, and the other end of the resistor R1 is grounded; The Z terminal of the current conveyor A is connected to one end of the capacitor C, and the other end of the capacitor C is grounded; The voltage at the X terminal of the current conveyor A is v i 、X terminal current i X 、Y terminal voltage v Y 、Y terminal current i Y 、Z terminal voltage v Z 、Z terminal current i Z 、O terminal voltage v g Satisfies the formula, where β is a constant coefficient:

2. A memristor emulator circuit as claimed in claim 1, characterized in that: The current i in the resistor Rf f Compared to the current i in resistor R1 Y Can be ignored.

3. A memristor emulator circuit as claimed in claim 1, characterized in that: Current conveyor A, resistor R1, resistor Rf, capacitor C, positive voltage source Vp, negative voltage source Vn form a pair of input v i The integrator output 4. A memristor emulator circuit as claimed in claim 1, characterized in that: The on-resistance of the conductive channel between the drain D and source S of the field effect tube M is affected by v g control.

5. A memristor emulator circuit as claimed in claim 1, characterized in that: The drain current of the field effect transistor is i It includes the current in the conductive channel between the drain D end and the source S end of the field effect transistor M and the current in the parasitic diode between the drain D end and the source S end of the field effect transistor M and the substrate. The substrate of the field effect transistor M is connected to the source S end of the field effect transistor.

6. A memristor emulator circuit as claimed in claim 1, characterized in that: At input v i is a sinusoidal signal, the drain current i of the field effect tube M i With the input signal v i The relationship curve shows the characteristics of a hysteresis loop.

7. A memristor emulator circuit as claimed in claim 1, characterized in that: At input v i is a sinusoidal signal, the drain current i of the field effect tube M i With the input signal v i The relationship curve will change with the input signal v i It gradually shrinks with the increase of frequency and finally shrinks into a single-valued function curve.

8. A memristor emulator circuit as claimed in claim 1, characterized in that: At the sinusoidal input v i When the frequency exceeds 1MHz, the memristor emulator circuit can still maintain the memristor characteristics.

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