Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate, a method for preparing the same, and a display device, the display substrate comprising a display area and a peripheral area, the peripheral area comprising a circuit board pin area and a test pin area located on at least one side of the display area. The display substrate further comprises: a plurality of sub-pixels and a first power line electrically connected to the plurality of sub-pixels; at least one first binding power pin located in the circuit board pin area, electrically connected to the first power line, and configured to transmit a first power signal to the plurality of sub-pixels during a display phase; a second power line located in the peripheral area and surrounding the display area; at least one second binding power pin located in the circuit board pin area, electrically connected to the second power line, and configured to transmit a second power signal to the plurality of sub-pixels during a display phase; and at least one test power pin located in the test pin area, electrically connected to at least one of the first power line and the second power line, and configured to transmit at least one of the first power signal and the second power signal to the plurality of sub-pixels during a test phase.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, flexible displays using OLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become a mainstream product in the display field. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] An embodiment of the present disclosure provides a display substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a circuit board pin area and a test pin area located on at least one side of the display area; the display substrate comprises:

[0005] A plurality of sub-pixels are located in the display area;

[0006] a first power line, located in the display area and electrically connected to the plurality of sub-pixels;

[0007] at least one first binding power pin, located in the circuit board pin area, electrically connected to the first power line, and configured to transmit a first power signal to the plurality of sub-pixels in a display phase;

[0008] a second power line located in the peripheral area and surrounding the display area;

[0009] at least one second binding power pin, located in the circuit board pin area, electrically connected to the second power line, and configured to transmit a second power signal to the plurality of sub-pixels in a display phase;

[0010] At least one test power pin is located in the test pin area and is electrically connected to at least one of the first power line and the second power line. The at least one test power pin is configured to transmit at least one of the first power signal and the second power signal to the multiple sub-pixels during a test phase.

[0011] In some exemplary embodiments, the at least one test power pin includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, and the second test power pin is electrically connected to the second power line.

[0012] In some exemplary embodiments, the second test power pin is located on a side of the first test power pin close to the display area.

[0013] In some exemplary embodiments, the display substrate further includes a first binding power lead and a second binding power lead, the first binding power lead electrically connecting the first power line and the first binding power pin, and the second binding power lead electrically connecting the second power line and the second binding power pin;

[0014] The display substrate further includes a first connecting line and a second connecting line, the first test power pin is electrically connected to the first binding power lead through the first connecting line, and the second test power pin is electrically connected to the second binding power lead through the second connecting line.

[0015] In some exemplary embodiments, the display substrate further includes a first test power lead and a second test power lead, the first test power lead extends along a first direction, the second test power lead extends along the first direction, the first connecting line extends along a second direction, the second connecting line extends along a second direction, the first test power lead is electrically connected to the first connecting line and the first test power pin, and the second test power lead is electrically connected to the second connecting line and the second test power pin.

[0016] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base;

[0017] At least part of the first connecting wires is disposed in the same layer as at least one of the first gate metal layer, the second gate metal layer, or the first source / drain metal layer.

[0018] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base;

[0019] The first connection line includes a first sub-connection line and a second sub-connection line, the first sub-connection line is provided in the same layer as the first gate metal layer, the second sub-connection line is provided in the same layer as the second gate metal layer, the first sub-connection line and the second sub-connection line are connected in parallel and electrically connected, the first sub-connection line at least partially overlaps with the first binding power lead and the second binding power lead, and the second sub-connection line at least partially overlaps with the first binding power lead and the second binding power lead; or,

[0020] The first connecting line includes a first sub-connecting line and a third sub-connecting line, the first sub-connecting line and the third sub-connecting line are electrically connected, and the first sub-connecting line at least partially overlaps with the first binding power lead and the second binding power lead, the third sub-connecting line does not overlap with the first binding power lead and the second binding power lead, the first sub-connecting line is arranged on the same layer as the first gate metal layer, and the third sub-connecting line is arranged on the same layer as the first source and drain metal layer.

[0021] In some exemplary embodiments, the first test power pin includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are electrically connected.

[0022] In some exemplary embodiments, the second test power pin includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer are electrically connected.

[0023] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base;

[0024] The first sub-layer and the third sub-layer are disposed in the same layer as the first source / drain metal layer, and the second sub-layer and the fourth sub-layer are disposed in the same layer as the first gate metal layer.

[0025] In some exemplary embodiments, the first binding power pin includes a first sub-pin and a second sub-pin, the second binding power pin includes a third sub-pin and a fourth sub-pin, the third sub-pin is located on a side of the first sub-pin away from the second sub-pin, and the fourth sub-pin is located on a side of the second sub-pin away from the first sub-pin.

[0026] In some exemplary embodiments, the test power pin includes a first test power pin and a second test power pin, the first test power pin includes a fifth sub-pin and a sixth sub-pin, the second test power pin includes a seventh sub-pin and an eighth sub-pin, the seventh sub-pin is located on a side of the fifth sub-pin away from the circuit board pin area, and the eighth sub-pin is located on a side of the sixth sub-pin away from the circuit board pin area.

[0027] In some exemplary embodiments, the display substrate further includes a first power bus located on a side of the display area close to the circuit board pin area, and the first power bus electrically connects the first binding power pin and the first power line.

[0028] In some exemplary embodiments, the display substrate further includes a plurality of test units, at least one test data signal line and at least one test control signal line, at least one of the plurality of test units is electrically connected to at least one of the plurality of data lines, the at least one test data signal line and the at least one test control signal line, and is configured to pass the signal transmitted by the at least one test data signal line to the at least one data line based on the signal transmitted by the at least one test control signal line.

[0029] In some exemplary embodiments, the test pin area further includes at least one first test pin and at least one second test pin, the first test pin is located on a side of the seventh sub-pin away from the circuit board pin area, and the second test pin is located on a side of the eighth sub-pin away from the circuit board pin area.

[0030] In some exemplary embodiments, the substrate is a rigid substrate or a flexible substrate.

[0031] An embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any of the preceding items.

[0032] The present disclosure also provides a method for preparing a display substrate, wherein the display substrate includes a display area and a peripheral area surrounding the display area, the peripheral area including a circuit board pin area and a test pin area located on one side of the display area, the display area including a first power line and a plurality of sub-pixels, the peripheral area including a second power line, the circuit board pin area including at least one first binding power pin and at least one second binding power pin, and the test pin area including at least one test power pin. The preparation method includes:

[0033] forming a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer and a second gate metal layer in sequence on the substrate;

[0034] forming a fourth insulating layer on the second gate metal layer;

[0035] A first source-drain metal layer, the first power line, the second power line, the first binding power pin, the second binding power pin and at least one test power pin are formed on the fourth insulating layer; the first power line is electrically connected to the first binding power pin, the second power line is electrically connected to the second binding power pin, and at least one test power pin is electrically connected to at least one of the first power line and the second power line.

[0036] In some exemplary embodiments, at least one of the test power pins includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, and the second test power pin is electrically connected to the second power line.

[0037] In some exemplary embodiments, a first connection line is formed on the second insulating layer or the third insulating layer, and the first connection line is provided in the same layer as the first gate metal layer or the second gate metal layer;

[0038] A first test power lead and a second test power lead are formed on the fourth insulating layer. The first test power lead and the second test power lead are arranged on the same layer as the first source and drain metal layer. The first test power lead is electrically connected to the first connecting line and the first test power pin. The first test power pin is electrically connected to the first binding power lead through the first connecting line. The second test power lead is electrically connected to the second binding power lead and the second test power pin.

[0039] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0041] Figure 1 A schematic structural diagram showing a substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 2 This is one of the structural schematic diagrams showing the peripheral area in the substrate according to an exemplary embodiment of the present disclosure;

[0043] Figure 3A This is a second structural schematic diagram showing the peripheral area of ​​a substrate in an exemplary embodiment of the present disclosure;

[0044] Figure 3B This is a third structural schematic diagram showing the peripheral area of ​​a substrate in an exemplary embodiment of the present disclosure;

[0045] Figure 4 for Figure 1 A sub-pixel in the display area and Figure 3B Schematic cross-sectional view of the AA' region;

[0046] Figure 5 for Figure 1 A sub-pixel in the display area and Figure 3B Schematic cross-sectional view of the BB' region;

[0047] Figure 6 This is a fourth structural schematic diagram showing the peripheral area of ​​a substrate in an exemplary embodiment of the present disclosure;

[0048] Figure 7 This is a fifth structural schematic diagram showing a peripheral area in a substrate according to an exemplary embodiment of the present disclosure;

[0049] Figure 8 for Figure 1 A sub-pixel in the display area and Figure 7 Schematic cross-sectional view of the CC' region;

[0050] Figure 9 for Figure 1 A sub-pixel in the display area and Figure 7 Schematic cross-sectional view of the DD' region;

[0051] Figure 10 A circuit diagram of a test unit in a display substrate according to an embodiment of the present disclosure;

[0052] Figure 11 A schematic diagram of the structure of a test unit in a display substrate according to an embodiment of the present disclosure;

[0053] Figure 12 This is a sixth structural schematic diagram showing a peripheral area in a substrate according to an exemplary embodiment of the present disclosure;

[0054] Figure 13 This is the seventh structural schematic diagram showing the peripheral area of ​​the substrate according to the exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0056] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0057] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0058] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0059] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0060] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0061] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0062] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0063] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0064] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0065] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0066] like Figure 1 and Figure 2 As shown, an exemplary embodiment of the present disclosure provides a display substrate, including a display area 10 and a peripheral area 30 surrounding the display area 10 . The peripheral area 30 includes a circuit board pin area 31 and a test pin area 32 located on one side of the display area 10 .

[0067] The display substrate comprises:

[0068] A plurality of sub-pixels 1 are located in a display area 10;

[0069] A first power line 411 is located in the display area 10 and is electrically connected to the plurality of sub-pixels 1;

[0070] At least one first binding power pin 311, located in the circuit board pin area 31, electrically connected to the first power line 411, and configured to transmit a first power signal to the plurality of sub-pixels 1 during the display phase;

[0071] The second power line 412 is located in the peripheral area 30 and surrounds the display area 10;

[0072] At least one second binding power pin 312, located in the circuit board pin area 31, electrically connected to the second power line 412, and configured to transmit a second power signal to the plurality of sub-pixels 1 during the display phase;

[0073] At least one test power pin, located in the test pin area 32, is electrically connected to at least one of the first power line 411 and the second power line 412, and the at least one test power pin is configured to transmit at least one of the first power signal and the second power signal to multiple sub-pixels 1 during the test phase.

[0074] After completing the backplane circuit fabrication, luminescent material vapor deposition, and water- and oxygen-barrier encapsulation processes, OLED display devices require cell testing to filter out defective products and prevent them from entering the back-end process, which would otherwise waste materials. The display substrate of the disclosed embodiment features separate test power pins, preventing problems such as scratches or poor binding of the power pins in the common circuit board pin area during cell testing.

[0075] In an exemplary embodiment, Figure 1 and Figure 2 As shown, the at least one test power pin includes a first test power pin 321 and a second test power pin 322 . The first test power pin 321 is electrically connected to the first power line 411 , and the second test power pin 322 is electrically connected to the second power line 412 .

[0076] In an exemplary embodiment, Figure 6 As shown, the second test power pin 322 is located on a side of the first test power pin 321 close to the display area 10 .

[0077] In an exemplary embodiment, Figure 3A As shown, the display substrate further includes a first binding power lead 313 and a second binding power lead 314, the first binding power lead 313 electrically connecting the first power line 411 and the first binding power pin 311, and the second binding power lead 314 electrically connecting the second power line 412 and the second binding power pin 312;

[0078] The display substrate further includes a first connection line 303 and a second connection line 304 . The first test power pin 321 is electrically connected to the first binding power lead 313 via the first connection line 303 . The second test power pin 322 is electrically connected to the second binding power lead 314 via the second connection line 304 .

[0079] In an exemplary embodiment, Figure 2 As shown, the display substrate further includes a first power bus 411 a , which is located on a side of the display area 10 close to the circuit board pin area 31 , and electrically connects the first binding power pin 311 and the first power line 411 .

[0080] In an exemplary embodiment, Figure 2 and Figure 3B As shown, the display substrate further includes a first test power lead 323 and a second test power lead 324. The first test power lead 323 extends along a first direction 991, the second test power lead 324 extends along the first direction 991, the first connection line 303 extends along a second direction 992, and the second connection line 304 extends along the second direction 304. The first test power lead 323 is electrically connected to the first connection line 303 and the first test power pin 321, and the second test power lead 324 is electrically connected to the second connection line 304 and the second test power pin 322. The first direction and the second direction intersect, and optionally, the first direction and the second direction are perpendicular.

[0081] In an exemplary embodiment, Figure 2 and Figure 3B As shown, the circuit board pin area 31 includes a first binding power lead 313 and a second binding power lead 314. The first binding power lead 313 is electrically connected to the first power line 411 and the first binding power pin 311. The second binding power lead 314 is electrically connected to the second power line 412 and the second binding power pin 312.

[0082] The test pin area 32 includes a first test power pin 321 , a second test power pin 322 , a first test power lead 323 connected to the first test power pin 321 , and a second test power lead 324 connected to the second test power pin 322 .

[0083] The display substrate further includes a first connection line 303 and a second connection line 304 . The first connection line 303 electrically connects the first binding power lead 313 and the first test power lead 323 . The second connection line 304 electrically connects the second binding power lead 314 and the second test power lead 324 .

[0084] In an exemplary embodiment, Figure 1As shown, the display area 10 includes: a plurality of sub-pixels 1; a plurality of data lines 11 extending along a first direction 991, each data line 11 connecting a plurality of sub-pixels 1; a plurality of gate lines 12 extending along a second direction 992 intersecting the first direction 991, each gate line 12 connecting a plurality of sub-pixels 1.

[0085] The peripheral area 30 includes a plurality of driving units 21 and driving signal lines 413 connected to the driving units 21 . The driving units 21 are configured to provide driving signals to the gate lines 12 .

[0086] In an exemplary embodiment, Figure 1 and Figure 11 As shown, the peripheral area also includes multiple test units 22, at least one test data signal line 3412 and at least one test control signal line 3411. At least one of the multiple test units 22 is electrically connected to at least one of the multiple data lines 11, at least one test data signal line 3412 and at least one test control signal line 3411, and is configured to pass the signal transmitted by at least one test data signal line 3412 to at least one data line 11 according to the signal transmitted by at least one test control signal line 3411.

[0087] In an exemplary embodiment, Figures 4 and 5 、 Figures 7 and 8 As shown, in a plane perpendicular to the display substrate, the display substrate may include: a substrate 100, a first insulating layer 200 arranged on the substrate 100, an active layer 300 arranged on the first insulating layer 200, a second insulating layer 400 arranged on the active layer 300, a first gate metal layer 500 arranged on the second insulating layer 400, a third insulating layer 600 arranged on the first gate metal layer 500, a second gate metal layer 700 arranged on the third insulating layer 600, a fourth insulating layer 800 arranged on the second gate metal layer 700, and a first source-drain metal layer 900 arranged on the fourth insulating layer 800.

[0088] In an exemplary embodiment, Figure 3A and Figure 6 As shown, at least a portion of the first connection line 303 is disposed in the same layer as at least one of the first gate metal layer 500 , the second gate metal layer 700 or the first source / drain metal layer 900 .

[0089] In an exemplary embodiment, the first binding power pin 311, the second binding power pin 312, the first test power pin 321, and the second test power pin 322 are all disposed in the same layer as the first source-drain metal layer 900. The first connecting wire 303 and the first test power lead 323 are all disposed in the same layer as the second gate metal layer 700. The first binding power lead 313, the second binding power lead 314, the second connecting wire 304, and the second test power lead 324 are all disposed in the same layer as the first source-drain metal layer 900. The first connecting wire 303 is connected to the first binding power lead 313 through a via in the fourth insulating layer 800, and the first test power lead 323 is connected to the first test power pin 321 through a via in the fourth insulating layer 800.

[0090] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process.

[0091] In an exemplary embodiment, the first connection line 303 and the first test power lead 323 may be an integrated structure.

[0092] In an exemplary embodiment, the first binding power pin 311 and the first binding power lead 313 may be an integrated structure.

[0093] In an exemplary embodiment, the second binding power pin 312 and the second binding power lead 314 may be an integral structure.

[0094] In an exemplary embodiment, the second test power pin 322 , the second test power lead 324 , and the second connection line 304 may be an integrated structure.

[0095] In an exemplary embodiment, the first power line 411 is a positive voltage power line (ELVDD), and the second power line 412 is a negative voltage power line (ELVSS).

[0096] In another exemplary embodiment, as shown in FIG. 3 to FIG. Figure 5 As shown, the first binding power pin 311, the second binding power pin 312, the first test power pin 321, and the second test power pin 322 are all arranged in the same layer as the first source-drain metal layer 900. The first connecting wire 303 and the first test power lead 323 are all arranged in the same layer as the first gate metal layer 500. The first binding power lead 313, the second binding power lead 314, the second connecting wire 304, and the second test power lead 324 are all arranged in the same layer as the first source-drain metal layer 900. The first connecting wire 303 is connected to the first binding power lead 313 through a via penetrating the third insulating layer 600 and the fourth insulating layer 800. The first test power lead 323 is connected to the first test power pin 321 through a via penetrating the third insulating layer 600 and the fourth insulating layer 800.

[0097] In another exemplary embodiment, the first binding power pin 311, the second binding power pin 312, the first test power pin 321, and the second test power pin 322 are all disposed in the same layer as the first source-drain metal layer 900; the first connection line 303 is disposed in the same layer as the first gate metal layer 500; and the first binding power lead 313, the second binding power lead 314, the second connection line 304, the first test power lead 323, and the second test power lead 324 are all disposed in the same layer as the first source-drain metal layer 900. The first connection line 303 is connected to the first binding power lead 313 and the first test power lead 323, respectively, through vias penetrating the third insulating layer 600 and the fourth insulating layer 800.

[0098] In yet another exemplary embodiment, Figure 6 As shown, the circuit board pin area 31 includes a first binding power lead 313 and a second binding power lead 314. The first binding power lead 313 is electrically connected to the first power line 411 and the first binding power pin 311. The second binding power lead 314 is electrically connected to the second power line 412 and the second binding power pin 312.

[0099] The test pin area 32 includes a first test power pin 321 , a second test power pin 322 , a first test power lead 323 connected to the first test power pin 321 , and a second test power lead 324 connected to the second test power pin 322 .

[0100] The display substrate further includes a first connection line 303 , which electrically connects the first binding power lead 313 and the first test power lead 323 .

[0101] In an exemplary embodiment, the display substrate may further include a fifth insulating layer and a first planarizing layer disposed on the first source / drain metal layer 900, and a second source / drain metal layer disposed on the first planarizing layer. The first binding power pin 311, the second binding power pin 312, the first test power pin 321 and the second test power pin 322, the first binding power lead 313, the second binding power lead 314, the second connecting wire 304, the first test power lead 323 and the second test power lead 324 may also be disposed on the same layer as the second source / drain metal layer. The first connecting wire 303 may be disposed on the same layer as the first source / drain metal layer 900, the second gate metal layer 700, or the first gate metal layer 500, although this disclosure is not limited thereto.

[0102] In an exemplary embodiment, the width of the first connecting line 303 is greater than the first width. Exemplarily, the first width can be 200 microns. If the resistance at the overlapping position of the first connecting line 303 and the second binding power lead 314 is too large, it is easy to cause current concentration during the high-brightness process, thereby generating a large amount of heat, which causes the upper insulating layer or the flat layer and other organic layers to burn and carbonize, and in severe cases, to fall off, and then easily enter water vapor to cause poor reliability. The embodiment of the present disclosure designs the first connecting line 303 to be as wide as possible, utilizes as much space as possible for routing, and minimizes the metal routing resistance at the line change position, thereby avoiding burning and carbonizing of the upper insulating layer or the flat layer and other organic layers due to large routing resistance, and in severe cases, to fall off, further causing problems such as poor reliability.

[0103] In an exemplary embodiment, the width of the second connection line 304 is approximately 50 micrometers to 1000 micrometers. The width of the second connection line 304 is determined by the size of the wiring space.

[0104] In an exemplary embodiment, the distance between the orthographic projection of the edge of the first connecting line 303 on the side close to the first test power lead 323 connected thereto and the orthographic projection of the edge of the second binding power lead 314 on the side close to the first test power lead 323 on the substrate 100 is less than the first distance. The size of the first distance can be determined according to the cross-connection width between the first test power lead 323 and the first connecting line 303. The embodiment of the present disclosure can minimize the metal wiring resistance at the wiring switching position by jumping back to the first test power lead 323 with small square resistance as soon as possible after the first connecting line 303 crosses the avoided second binding power lead 314, thereby avoiding burning, carbonization, and even shedding of organic layers such as the upper insulating layer or the flat layer due to the large wiring resistance, which may further cause problems such as poor reliability.

[0105] like Figure 7 and Figure 8 As shown, the first connection line 303 includes a first sub-connection line 3031 and a second sub-connection line 3032. The first sub-connection line 3031 is provided in the same layer as the first gate metal layer 500, and the second sub-connection line 3032 is provided in the same layer as the second gate metal layer 700. The first sub-connection line 3031 and the second sub-connection line 3032 are connected in parallel and electrically connected. The first sub-connection line 3031 at least partially overlaps with the first binding power lead 313 and the second binding power lead 314, and the second sub-connection line 3032 at least partially overlaps with the first binding power lead 313 and the second binding power lead 314.

[0106] The embodiment of the present disclosure further reduces the metal wiring resistance at the line change position by utilizing the first sub-connection line 3031 on the first gate metal layer 500 and the second sub-connection line 3032 on the second gate metal layer 700 to be routed in parallel, thereby avoiding burning and carbonization of organic layers such as the upper insulating layer or the flat layer due to large wiring resistance, and even severe falling off, which further causes problems such as poor reliability.

[0107] like Figure 3A and Figure 6 As shown, the first connection line 303 includes a first sub-connection line 3031 and a third sub-connection line 3033. The first sub-connection line 3031 and the third sub-connection line 3033 are electrically connected, and the first sub-connection line 3031 at least partially overlaps with the first binding power lead 313 and the second binding power lead 314. The third sub-connection line 3033 does not overlap with the first binding power lead 313 and the second binding power lead 314. The first sub-connection line 3031 is arranged on the same layer as the first gate metal layer 500, and the third sub-connection line 3033 is arranged on the same layer as the first source and drain metal layer 900.

[0108] In an exemplary embodiment, Figure 9 As shown, the first test power pin 321 includes a first sublayer 321a and a second sublayer 321b. The first sublayer 321a can be electrically connected to the second sublayer 321b. The first sublayer 321a can be disposed on the same layer as the first gate metal layer 500, and the second sublayer 321b can be disposed on the same layer as the first source / drain metal layer 900. The display substrate of the embodiment of the present disclosure, by providing the first sublayer 321a and the second sublayer 321b, can raise the height of the first test power pin 321, thereby facilitating cell testing (Cell Test). In addition, since the signal lead of the first test power pin 321 is generally led out from the first gate metal layer 500, the provision of the first sublayer 321a also facilitates leading out the signal lead of the first test power pin 321.

[0109] In an exemplary embodiment, Figure 9 As shown, the second test power pin 322 includes a third sublayer 322a and a fourth sublayer 322b, which are electrically connected. The third sublayer 322a can be provided in the same layer as the first gate metal layer 500, and the fourth sublayer 322b can be provided in the same layer as the first source / drain metal layer 900. The display substrate of the embodiment of the present disclosure, by providing the third sublayer 322a and the fourth sublayer 322b, can raise the height of the second test power pin 322, thereby facilitating cell testing (Cell Test). In addition, since the signal lead of the second test power pin 322 is generally led out from the first gate metal layer 500, the provision of the third sublayer 322a also facilitates leading out the signal lead of the second test power pin 322.

[0110] In an exemplary embodiment, Figure 9 As shown, the second binding power pin 312 includes a fifth sublayer 312a and a sixth sublayer 312b. The fifth sublayer 312a can be electrically connected to the sixth sublayer 312b. The fifth sublayer 312a can be provided on the same layer as the first gate metal layer 500, and the sixth sublayer 312b can be provided on the same layer as the first source / drain metal layer 900. The display substrate of the present embodiment of the disclosure, by providing the fifth sublayer 312a and the sixth sublayer 312b, can raise the height of the second binding power pin 312, thereby facilitating signal binding. Furthermore, since the signal lead of the second binding power pin 312 is generally led out from the first gate metal layer 500, the provision of the fifth sublayer 312a also facilitates leading out the signal lead of the second binding power pin 312.

[0111] In an exemplary embodiment, Figure 9 As shown, the first binding power pin 311 includes a seventh sublayer 311a and an eighth sublayer 311b, which are electrically connected. The seventh sublayer 311a can be provided on the same layer as the first gate metal layer 500, and the eighth sublayer 311b can be provided on the same layer as the first source / drain metal layer 900. The display substrate of the disclosed embodiment, by providing the seventh sublayer 311a and the eighth sublayer 311b, can raise the height of the first binding power pin 311, thereby facilitating signal binding. Furthermore, since the signal lead of the first binding power pin 311 is typically led out from the first gate metal layer 500, the seventh sublayer 311a also facilitates leading out the signal lead of the first binding power pin 311.

[0112] In another exemplary embodiment, the first sublayer 321a, the third sublayer 322a, the fifth sublayer 312a, and the seventh sublayer 311a may also be provided in the same layer as the second gate metal layer 700, which is not limited in the present disclosure. Figure 7 As shown, the display substrate further includes a plurality of test signal lines 341. The test pin area 32 further includes a plurality of test pins 325 and a plurality of test connection lines 326 connected to the test pins 325 in a one-to-one correspondence.

[0113] Reference Figure 1 The display substrate of the embodiment of the present disclosure is divided into multiple areas, the middle of which is the display area 10 (or AA area) for display, and the sub-pixels 1 (or sub-pixels) for display are arranged in the display area 10. It should be understood that Figure 1The use of "rectangles" to represent the various units (including the driving unit 21, the test unit 22, etc.) and the sub-pixel 1 is only schematic, and the area they occupy is not necessarily a rectangle. For an actual display substrate, each unit (including the driving unit 21, the test unit 22, etc.) corresponds to only a very small part of the peripheral area, so in the subsequent figures, many structures in the local area of ​​each unit are approximated as straight lines. It should be understood that, based on area limitations, in many figures of the embodiments of the present disclosure, the shapes, sizes, size ratios, numbers, number ratios, positions, etc. of the various structures such as the sub-pixel 1 leads (such as signal lines), connectors, units, and areas are only exemplary, and not limitations on the embodiments of the present disclosure. For example, the actual number of test signal lines 341, drive signal lines 413, etc. should be less than Figure 1 More shown in .

[0114] In the embodiments of the present disclosure, sub-pixel 1 refers to the smallest structure that can be used to independently display the desired content, that is, the smallest independently controllable "dot" in the display device. The specific form of sub-pixel 1 is diverse, as long as it can achieve independent display.

[0115] That is to say, in each sub-pixel 1 of the display substrate of the embodiment of the present disclosure, an organic light emitting diode OLED can be used as a light emitting device, which is specifically an organic light emitting diode display substrate.

[0116] Different sub-pixels 1 may have different colors, thereby enabling color display through light mixing from different sub-pixels 1. To achieve color display, multiple sub-pixels 1 of different colors arranged together may form a "pixel (or pixel unit)," where the light emitted by these sub-pixels 1 is mixed together to form a visual "point." For example, three sub-pixels 1 of red, green, and blue may form a pixel. Alternatively, there may be no distinct pixels (or pixel units), and color display may be achieved through "sharing" between adjacent sub-pixels 1.

[0117] Reference Figure 1 In the display area 10, there are also data lines 11 extending along a first direction 991 and gate lines 12 extending along a second direction 992, wherein the first direction 991 intersects with the second direction 992 (that is, they are not parallel to each other), so that each intersection of the data line 11 and the gate line 12 can define a sub-pixel 1, and through the joint control of the gate line 12 and the data line 11, the sub-pixel 1 at the intersection of the two can be displayed.

[0118] In some embodiments, the first direction 991 is perpendicular to the second direction 992, that is, the first direction 991 may be a column direction ( Figure 1 The second direction 992 may be a row direction perpendicular to the column direction ( Figure 1 (middle is horizontal).

[0119] It should be understood that the first direction 991 and the second direction 992 are actually just two relative directions corresponding to the data line 11 and the gate line 12. The two are not necessarily the column direction and the row direction, and have no necessary relationship with the shape, position, placement, etc. of the display substrate (or display device).

[0120] In some embodiments, the sub-pixels 1 in the display area 10 may be arranged in an array, that is, the sub-pixels 1 may be arranged in multiple rows and columns, wherein each row of sub-pixels 1 is connected to a gate line 12, and each column of sub-pixels 1 is connected to a data line 11. The sub-pixels 1 do not necessarily need to be arranged in an array, and each data line 11 and gate line 12 does not necessarily need to be connected to sub-pixels 1 in the same column or row.

[0121] In the embodiments of the present disclosure, a pad or pin refers to a structure in a display substrate that can access other signals and direct them to a signal line. A pad can be used to connect to a flexible printed circuit board (FPC) or driver chip, thereby acquiring signals from the FPC or driver chip. Alternatively, a pad can be used to contact a test probe of a test device, thereby acquiring signals from the test probe.

[0122] Reference Figure 1 The peripheral area 30 can be divided into a first half area and a second half area on both sides of the display area 10 along the second direction 992. Figure 1 Since the gate lines 12 extend along the second direction 992, all gate lines 12 correspond to the first half area ( Figure 1 Therefore, the driving unit 21 in the first half area may be a gate driving unit 211 that provides gate driving signals to the plurality of gate lines 12, so that the gate driving unit 211 is connected to the corresponding gate lines 12 nearby.

[0123] In an exemplary embodiment, each gate driving unit 211 may be a gate shift register (GOA), and multiple gate shift registers are cascaded, so that the multiple gate shift registers can provide driving signals to multiple gate lines 12 respectively.

[0124] In some embodiments, the display area 10 further includes a plurality of control electrode lines 13 extending along the second direction 992 , and each control electrode line 13 is connected to a plurality of sub-pixels 1 ;

[0125] The driving unit 21 located in the second half region is a gate driving unit 212 . The gate driving unit 212 is configured to provide gate driving signals to the plurality of gate lines 13 .

[0126] Reference Figure 1The display area 10 may further be provided with control lines 13 that also extend along the second direction 992 , and each control line 13 may also be connected to one or two rows of sub-pixels 1 .

[0127] Since the control electrode lines 13 also extend along the second direction 992, all the control electrode lines 13 correspond to the second half region ( Figure 1 Therefore, the driving unit 21 in the second half area can be a gate driving unit 212 that provides gate driving signals to multiple gate lines 13, so that the gate driving unit 212 is connected to the corresponding gate line 13 nearby.

[0128] Of course, the specific form of the driving unit 21 described above is not a limitation of the embodiments of the present disclosure. For example, the driving units 21 in both half-areas may also be gate driving units 211, and respectively provide gate driving signals to different gate lines 12, or provide gate driving signals to each gate line 12 from both sides simultaneously (i.e., dual-sided driving).

[0129] In an exemplary embodiment, each gate driving unit 212 may be a gate shift register (EMGOA), and multiple gate shift registers are cascaded, so that the multiple gate shift registers can respectively provide driving signals to multiple gate lines 12 .

[0130] In some embodiments, the test signal line 341 includes a test control line 3411 and a test data line 3412; at least one test unit 22 includes multiple test transistors 220; the gate of each test transistor 220 is connected to a test control line 3411, the first electrode is connected to a data line 11, and the second electrode is connected to a test data line 3412; each test data line 3412 is connected to multiple test units 22.

[0131] Reference Figure 10 and Figure 11The display substrate of this embodiment has a total of 3 test data signal lines 3412 and 3 test control signal lines 3411. Each test unit 22 includes 6 test transistors for controlling 4 data lines 11 (corresponding to the above 4 columns of sub-pixels 1, two columns of sub-pixels 1 in each of the 4 columns of sub-pixels 1 are green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, the two sub-pixels 1 in any same row are blue and red respectively). Each test unit 22 includes a first test transistor 220a, a second test transistor 220b, a third test transistor 220c, a fourth test transistor 220d, a fifth test transistor 220e, and a sixth test transistor 220f. The drains of the first test transistor 220a and the second test transistor 220b are connected to a column of mixed red and blue sub-pixels 1, and the drains of the fourth test transistor 220d and the fifth test transistor 220e are connected to the drains of the other A column of mixed red and blue sub-pixels 1, the drain of the third test transistor 220c is connected to a column of green sub-pixels 1, the drain of the sixth test transistor 220f is connected to another column of green sub-pixels 1, the source of the first test transistor 220a and the fourth test transistor 220d is connected to the first test data signal line CTDR, the source of the second test transistor 220b and the fifth test transistor 220e is connected to the second test data signal line CTDB, the source of the third test transistor 220c and the sixth test transistor 220f is connected to the third test data signal line CTDG, the gate of the first test transistor 220a and the fifth test transistor 220e is connected to the third test control signal line SWBR, the gate of the second test transistor 220b and the fourth test transistor 220d is connected to the second test control signal line SWRB; the gate of the third test transistor 220c and the sixth test transistor 220f is connected to the first test control signal line SWG.

[0132] It can be seen from the above settings that by alternately providing turn-on signals to the second test control signal line SWRB and the third test control signal line SWBR, the first test data signal line CTDR and the second test data signal line CTDB can control the blue and red sub-pixels 1 respectively, while the first test control signal line SWG and the third test data signal line CTDG control all green sub-pixels 1, so that the sub-pixels 1 of the same color display the same brightness.

[0133] Reference Figure 10 In every 4 columns of sub-pixels 1, two columns of sub-pixels 1 can be green, and in each of the remaining two columns of sub-pixels 1, red and blue sub-pixels 1 are arranged alternately, and in the two columns of sub-pixels 1, the two sub-pixels 1 in any row are blue and red respectively.

[0134] In an exemplary embodiment, Figure 12As shown, the shape of each pin of the test pin area 32 (including the test pin 325, the first test power pin 321 and the second test power pin 322) is a square, and the spacing a between the center points of adjacent pins is greater than the preset first spacing, and the width b of each pin is greater than the preset second width.

[0135] In the embodiment of the present disclosure, the test pin area 32 can be used for unit testing by means of crimping or probing.

[0136] In an exemplary embodiment, when a pin-penetration method is used to perform unit testing, the spacing between center points of adjacent pins is between 500 and 1200 microns, and the width of each pin is between 200 and 800 microns.

[0137] In another exemplary embodiment, when the unit test is performed using a press-fit method, the spacing between center points of adjacent pins is between 150 and 300 microns, and the width of each pin is between 100 and 220 microns.

[0138] Compared with the crimping method, the needle piercing method requires a wider test pin area. If space permits, the needle piercing method can be used for unit testing.

[0139] In an exemplary embodiment, the substrate 100 is a rigid substrate or a flexible substrate.

[0140] In an exemplary embodiment, the first binding power pin 311, the second binding power pin 312, the first test power pin 321, and the second test power pin 322 are all arranged on the same layer as the first source-drain metal layer 900; the first connecting line 303 and the first test power lead 323 are arranged on the same layer as the first gate metal layer 500; the first binding power lead 313, the second binding power lead 314, the second connecting line 304, and the second test power lead 324 are all arranged on the same layer as the first source-drain metal layer 900;

[0141] The first connection line 303 is connected to the first binding power lead 313 through vias on the third insulating layer 600 and the fourth insulating layer 800 . The first test power pin 321 is connected to the first test power lead 323 through vias on the third insulating layer 600 and the fourth insulating layer 800 .

[0142] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a base 100 and a first insulating layer 200, an active layer 300, a second insulating layer 400, a first gate metal layer 500, a third insulating layer 600, a second gate metal layer 700, a fourth insulating layer 800, a first source-drain metal layer 900, a fifth insulating layer, a first planar layer and an anode layer stacked on the base 100; the test pin area 32 includes a first test power connection electrode and a second test power connection electrode, and the circuit board pin area 31 includes a first binding power connection electrode and a second binding power connection electrode, and the first test power connection electrode, the second test power connection electrode, the first binding power connection electrode, and the second binding power connection electrode are arranged on the same layer as the anode layer.

[0143] The first binding power pin 311, the second binding power pin 312, the first test power pin 321, and the second test power pin 322 are all arranged in the same layer as the first source-drain metal layer 900. The first binding power connection electrode is connected to the first binding power pin 311 via the first connection electrode, the second binding power connection electrode is connected to the second binding power pin 312 via the second connection electrode, the first test power connection electrode is connected to the first test power pin 321 via the third connection electrode, and the second test power connection electrode is connected to the second test power pin 322 via the fourth connection electrode. The first connection line 303 is arranged in the same layer as the first gate metal layer 500. The first binding power lead 313, the second binding power lead 314, the second connection line 304, the first test power lead 323, and the second test power lead 324 are all arranged in the same layer as the first source-drain metal layer 900. The first connection line 303 is connected to the first binding power lead 313 and the first test power lead 323 respectively through vias in the fourth insulating layer 800.

[0144] In an exemplary embodiment, Figure 12 As shown, the first binding power pin 311 includes a first sub-pin 3111 and a second sub-pin 3112, and the second binding power pin 312 includes a third sub-pin 3121 and a fourth sub-pin 3122, wherein the third sub-pin 3121 is located on the side of the first sub-pin 3111 away from the second sub-pin 3112, and the fourth sub-pin 3122 is located on the side of the second sub-pin 3112 away from the first sub-pin 3111.

[0145] In an exemplary embodiment, Figure 12As shown, the test power pin includes a first test power pin 321 and a second test power pin 322, the first test power pin 321 includes a fifth sub-pin 3211 and a sixth sub-pin 3212, the second test power pin 322 includes a seventh sub-pin 3221 and an eighth sub-pin 3222, the seventh sub-pin 3221 is located on the side of the fifth sub-pin 3211 away from the circuit board pin area 31, and the eighth sub-pin 3222 is located on the side of the sixth sub-pin 3212 away from the circuit board pin area 31.

[0146] In an exemplary embodiment, Figure 12 As shown, the test pin area 32 also includes at least one first test pin 3251 and at least one second test pin 3252, the first test pin 3251 is located on the side of the seventh sub-pin 3221 away from the circuit board pin area 31, and the second test pin 3252 is located on the side of the eighth sub-pin 3222 away from the circuit board pin area 31.

[0147] The display substrate of the embodiment of the present disclosure is a substrate used in a display device, for example, an array substrate having a thin film transistor (TFT) array. In an exemplary embodiment, the bonding area 30 may further include an anti-static circuit configured to eliminate static electricity, an isolation dam configured to block moisture from entering the display area 10, and other wiring areas, which are not limited in this disclosure.

[0148] In an exemplary embodiment, the circuit board pin area 31 may also be provided with other pins, which is not limited in the present disclosure.

[0149] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0150] (1) Prepare a substrate 100 on a glass carrier. In an exemplary embodiment, the substrate 100 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate 100.

[0151] In an exemplary embodiment, the substrate 100 may be a hard substrate.

[0152] (2) A first insulating film and an active layer film are sequentially deposited on the substrate 100, and the active layer film is patterned through a patterning process to form a first insulating layer 200 covering the entire substrate 100 and a pattern of the active layer 300 disposed on the first insulating layer 200. After this patterning process, the circuit board pin area 31 and the test pin area 32 include the first insulating layer 200 disposed on the substrate 100.

[0153] (3) Depositing a second insulating film and a first metal film in sequence, patterning the first metal film through a patterning process to form a second insulating layer 400 covering the active layer pattern, and a first gate metal layer 500 pattern arranged on the second insulating layer 400, wherein the first gate metal layer 500 pattern includes at least a first gate electrode, a first capacitor electrode, and a test signal line, wherein the first gate electrode and the first capacitor electrode are formed in the display area 10, and the test signal line is formed in the test pin area 32.

[0154] (4) A third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned by a patterning process to form a third insulating layer 600 covering the first gate metal layer 500, and a second gate metal layer 700 pattern disposed on the third insulating layer 600. The second gate metal layer 700 pattern includes at least a second capacitor electrode and a first connecting line 303. The third capacitor electrode is formed in the display area 10, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode. The first connecting line 303 is formed in the peripheral area 30. The first connecting line 303 is configured to connect a first binding power lead 313 and a first test power lead 323 formed subsequently, so that the first binding power lead 313 and the first test power lead 323 are simultaneously connected through the first connecting line 303 to ensure signal transmission.

[0155] (5) Depositing a fourth insulating film and patterning the fourth insulating film through a patterning process to form a fourth insulating layer 800 pattern covering the second gate metal layer 700, wherein a plurality of via holes are opened on the fourth insulating layer 800, and the plurality of via holes include at least two first active via holes and two first via holes.

[0156] In an exemplary embodiment, two first active via holes are formed in the display area 10 , and the fourth insulating layer 800 , the third insulating layer 600 , and the second insulating layer 400 within the two first active via holes are etched away to expose the surface of the first active layer.

[0157] In an exemplary embodiment, two first via holes are formed in the peripheral region 30 , and the fourth insulating layer 800 in the first via holes is etched away to expose the surface of the first connection line 303 .

[0158] In an exemplary embodiment, the two first active vias are configured to connect the subsequently formed first source electrode and first drain electrode to the first active layer, respectively. The two first vias are configured to connect the subsequently formed first binding power lead 313 and the first test power line to the first connection line 303, respectively, thereby achieving a connection between the first test power pin 321 and the first power line.

[0159] (6) depositing a third metal film, patterning the third metal film through a patterning process, and forming a first source-drain metal layer 900 pattern on the fourth insulating layer 800, wherein the first source-drain metal layer 900 at least includes a first source electrode, a first drain electrode, a first binding power pin 311, a second binding power pin 312, a first binding power lead 313, a second binding power lead 314, a first power line 411, a second power line 412, a first test power pin 321, a second test power pin 322, a first test power lead 323, a second test power lead 324, and a second connecting line 304, as shown in FIG. Figure 3B 、 Figure 4 and Figure 5 shown.

[0160] A first source electrode and a first drain electrode are formed in the display area 10 and are connected to the first active layer through first active vias. A first power line 411 is formed in the display area 10, and a second power line 412 is formed in the peripheral area 30. The first power line 411 extends from the display area 10 to the peripheral area 30 and is connected to the first binding power lead 313. The second power line 412 is connected to the second binding power lead 314.

[0161] A first binding power pin 311, a second binding power pin 312, a first binding power lead 313, and a second binding power lead 314 are formed in the circuit board pin area 31. The first binding power pin 311 and the first binding power lead 313 can be integrally formed, and the second binding power pin 312 and the second binding power lead 314 can be integrally formed. The first binding power lead 313 is connected to the first test power lead 323 through a first via.

[0162] A first test power pin 321, a second test power pin 322, a first test power lead 323, and a second test power lead 324 are formed in the test pin area 32. The first test power pin 321 and the first test power lead 323 can be an integral structure. The second binding power lead 314 is connected to the second test power lead 324 via a second connecting wire 304. The second test power pin 322, the second test power lead 324, and the second connecting wire 304 can also be an integral structure.

[0163] (7) On the substrate 100 formed with the aforementioned pattern, a fifth insulating film is first deposited, and then a first planar thin film of an organic material is coated, forming a fifth insulating layer covering the entire substrate 100 and a first planar (PLN) layer disposed on the fifth insulating layer. An anode via hole is formed on the first planar layer through a patterning process including masking, exposure, and development. The anode via hole is formed in the display area 10. The first planar layer and the fifth insulating layer within the anode via hole are removed, exposing the surface of the first drain electrode of the first transistor. In an exemplary embodiment, the fifth insulating layer and the first planar layer are referred to as a composite insulating layer.

[0164] In an exemplary embodiment, the composite insulating layer may include only the fifth insulating layer, or only the first planar layer. In the case where the composite insulating layer includes only the first planar layer, the first planar layer may be formed directly on the substrate 100 having the aforementioned pattern formed thereon, and the first planar layer may be formed in the circuit board pin region 31 and the test pin region 32.

[0165] At this point, the driving structure layer pattern is completed on the substrate 100. In the display area 10, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the driving transistor in the pixel driving circuit, and the first capacitor electrode and the second capacitor electrode constitute the storage capacitor in the pixel driving circuit.

[0166] In an exemplary embodiment, the display substrate further includes an anode, a pixel definition (PDL) layer, a spacer column (PS), an organic light-emitting layer, a cathode, and an encapsulation layer formed in the display area 10. The encapsulation layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer are made of inorganic materials, and the second encapsulation layer is made of organic materials.

[0167] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate. The second insulating layer and the third insulating layer are called gate insulating (GI) layers. The fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first metal film, the second metal film, the third metal film and the fourth metal film can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Ti / Al / Ti. The active layer film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology and organic technology.

[0168] It can be seen from the structure of the display substrate and its preparation process of the exemplary embodiment of the present disclosure that the exemplary embodiment of the present disclosure sets the first test power pin and the second test power pin in the test pin area, so that the first binding power pin and the second binding power pin in the circuit board pin area will not be damaged during the lighting test of the display substrate, thereby improving the reliability of signal input.

[0169] The structure of the substrate and its preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary. In the exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0170] Figure 13 FIG. 1 is a plan view of the pin area and the test pin area of ​​the circuit board according to an exemplary embodiment of the present disclosure. Figure 13 As shown, the circuit board pin area 31 includes a first binding power pin 311, a second binding power pin 312, a first binding power lead 313 connected to the first binding power pin 311, and a second binding power lead 314 connected to the second binding power pin 312. A first power lead 411 is connected to the first binding power lead 313, and a second power lead 412 is connected to the second binding power lead 314. The test pin area 32 includes a first test power pin 321, a second test power pin 322, a first test power lead 323 connected to the first test power pin 321, and a second test power lead 324 connected to the second test power pin 322. The test pin area 32 also includes a plurality of test pins 325 and a plurality of test connection lines 326 connected one-to-one with the test pins 325. The test pins 325 and the test connection lines 326 are arranged on the same layer as the first source and drain metal layer 900. The first connection line 303 electrically connects the first binding power lead 313 and the first test power lead 323.

[0171] The present disclosure also provides a method for manufacturing a display substrate, the display substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a circuit board pin area and a test pin area located on one side of the display area, the display area including a first power line and a plurality of sub-pixels, the peripheral area including a second power line, the circuit board pin area including at least one first binding power pin and at least one second binding power pin, and the test pin area including at least one test power pin. In an exemplary embodiment, the manufacturing method includes:

[0172] forming a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer and a second gate metal layer in sequence on the substrate;

[0173] forming a fourth insulating layer on the second gate metal layer;

[0174] A first source-drain metal layer, a first power line, a second power line, a first binding power pin, a second binding power pin and a test power pin are formed on the fourth insulating layer; the first power line is electrically connected to the first binding power pin, the second power line is electrically connected to the second binding power pin, and the test power pin is electrically connected to at least one of the first power line and the second power line.

[0175] In an exemplary embodiment, the test power pins include a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, and the second test power pin is electrically connected to the second power line.

[0176] In an exemplary embodiment, the preparation method further comprises:

[0177] forming a first connecting line on the second insulating layer or the third insulating layer, wherein the first connecting line is disposed in the same layer as the first gate metal layer or the second gate metal layer;

[0178] A first test power lead and a second test power lead are formed on the fourth insulating layer. The first test power lead and the second test power lead are arranged on the same layer as the first source and drain metal layer. The first test power lead is electrically connected to the first connecting line and the first test power pin. The first test power pin is electrically connected to the first binding power lead through the first connecting line. The second test power lead is electrically connected to the second binding power lead and the second test power pin.

[0179] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0180] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to general designs. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, may be combined with each other to obtain new embodiments.

[0181] It should be understood by those skilled in the art that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure.

Claims

1. A display substrate comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a circuit board pin area and a test pin area located on at least one side of the display area; the display substrate comprising: A plurality of sub-pixels are located in the display area; a first power line, located in the display area and electrically connected to the plurality of sub-pixels; at least one first binding power pin, located in the circuit board pin area, electrically connected to the first power line, and configured to transmit a first power signal to the plurality of sub-pixels in a display phase; a second power line located in the peripheral area and surrounding the display area; at least one second binding power pin, located in the circuit board pin area, electrically connected to the second power line, and configured to transmit a second power signal to the plurality of sub-pixels in a display phase; a first test power pin and a second test power pin, located in the test pin area, the first test power pin being electrically connected to the first power line, and the second test power pin being electrically connected to the second power line; the first test power pin being configured to transmit the first power signal to the plurality of sub-pixels during a test phase, and the second test power pin being configured to transmit the second power signal to the plurality of sub-pixels during a test phase; The first power line, the second power line, the first binding power pin, the second binding power pin, the first test power pin and the second test power pin are arranged on the same layer.

2. The display substrate according to claim 1, wherein The second test power pin is located on a side of the first test power pin close to the display area.

3. The display substrate according to claim 1, wherein The display substrate further includes a first binding power lead and a second binding power lead, wherein the first binding power lead is electrically connected to the first power line and the first binding power pin, and the second binding power lead is electrically connected to the second power line and the second binding power pin; The display substrate further includes a first connecting line and a second connecting line, the first test power pin is electrically connected to the first binding power lead through the first connecting line, and the second test power pin is electrically connected to the second binding power lead through the second connecting line.

4. The display substrate according to claim 3, wherein: The display substrate further includes a first test power lead and a second test power lead, wherein the first test power lead extends along a first direction, the second test power lead extends along the first direction, the first connection line extends along a second direction, the second connection line extends along a second direction, and the first direction and the second direction intersect; The first test power lead is electrically connected to the first connection line and the first test power pin, and the second test power lead is electrically connected to the second connection line and the second test power pin.

5. The display substrate according to claim 3, wherein: In a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base; At least part of the first connecting wires is disposed in the same layer as at least one of the first gate metal layer, the second gate metal layer, or the first source / drain metal layer. The display substrate according to claim 5 , wherein: In a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base; The first connection line includes a first sub-connection line and a second sub-connection line, the first sub-connection line is provided in the same layer as the first gate metal layer, the second sub-connection line is provided in the same layer as the second gate metal layer, the first sub-connection line and the second sub-connection line are connected in parallel and electrically connected, the first sub-connection line at least partially overlaps with the first binding power lead and the second binding power lead, and the second sub-connection line at least partially overlaps with the first binding power lead and the second binding power lead; or, The first connecting line includes a first sub-connecting line and a third sub-connecting line, the first sub-connecting line and the third sub-connecting line are electrically connected, and the first sub-connecting line at least partially overlaps with the first binding power lead and the second binding power lead, the third sub-connecting line does not overlap with the first binding power lead and the second binding power lead, the first sub-connecting line is arranged on the same layer as the first gate metal layer, and the third sub-connecting line is arranged on the same layer as the first source and drain metal layer.

7. The display substrate according to claim 5, wherein: The substrate is a rigid substrate or a flexible substrate.

8. The display substrate according to claim 1, wherein: The first test power pin includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are electrically connected.

9. The display substrate according to claim 8, wherein: The second test power pin includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer are electrically connected.

10. The display substrate according to claim 9, wherein: In a plane perpendicular to the display substrate, the display substrate includes a base and a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer, a second gate metal layer, a fourth insulating layer and a first source-drain metal layer stacked on the base; The first sub-layer and the third sub-layer are disposed in the same layer as the first source / drain metal layer, and the second sub-layer and the fourth sub-layer are disposed in the same layer as the first gate metal layer.

11. The display substrate according to claim 1, wherein: The first binding power pin includes a first sub-pin and a second sub-pin, and the second binding power pin includes a third sub-pin and a fourth sub-pin, the third sub-pin is located on a side of the first sub-pin away from the second sub-pin, and the fourth sub-pin is located on a side of the second sub-pin away from the first sub-pin.

12. The display substrate according to claim 1, wherein The first test power pin includes a fifth sub-pin and a sixth sub-pin, and the second test power pin includes a seventh sub-pin and an eighth sub-pin. The seventh sub-pin is located on a side of the fifth sub-pin away from the circuit board pin area, and the eighth sub-pin is located on a side of the sixth sub-pin away from the circuit board pin area.

13. The display substrate according to claim 12, wherein: The test pin area also includes at least one first test pin and at least one second test pin, the first test pin is located on the side of the seventh sub-pin away from the circuit board pin area, and the second test pin is located on the side of the eighth sub-pin away from the circuit board pin area.

14. The display substrate according to claim 1, wherein The display substrate further includes a first power bus located on a side of the display area close to the circuit board pin area, and the first power bus electrically connects the first binding power pin and the first power line.

15. The display substrate according to claim 1, wherein The display substrate also includes a plurality of test units, at least one test data signal line and at least one test control signal line. At least one of the plurality of test units is electrically connected to at least one of the plurality of data lines, the at least one test data signal line and the at least one test control signal line, and is configured to transmit a signal transmitted by the at least one test data signal line to the at least one data line based on a signal transmitted by the at least one test control signal line.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

17. A method for preparing a display substrate, the display substrate comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a circuit board pin area and a test pin area located on one side of the display area, the display area comprising a first power line and a plurality of sub-pixels, the peripheral area comprising a second power line, the circuit board pin area comprising at least one first binding power pin and at least one second binding power pin, and the test pin area comprising at least one test power pin, the preparation method comprising: forming a first insulating layer, an active layer, a second insulating layer, a first gate metal layer, a third insulating layer and a second gate metal layer in sequence on the substrate; forming a fourth insulating layer on the second gate metal layer; A first source-drain metal layer, the first power line, the second power line, the first binding power pin, the second binding power pin and at least one test power pin are formed on the fourth insulating layer; the first power line is electrically connected to the first binding power pin, the second power line is electrically connected to the second binding power pin, and at least one test power pin is electrically connected to at least one of the first power line and the second power line.

18. The preparation method according to claim 17, wherein At least one of the test power pins includes a first test power pin and a second test power pin, the first test power pin is electrically connected to the first power line, and the second test power pin is electrically connected to the second power line.

19. The preparation method according to claim 17, wherein The method further comprises: forming a first connecting line on the second insulating layer or the third insulating layer, wherein the first connecting line is provided on the same layer as the first gate metal layer or the second gate metal layer; A first test power lead and a second test power lead are formed on the fourth insulating layer. The first test power lead and the second test power lead are arranged on the same layer as the first source and drain metal layer. The first test power lead is electrically connected to the first connecting line and the first test power pin. The first test power pin is electrically connected to the first binding power lead through the first connecting line. The second test power lead is electrically connected to the second binding power lead and the second test power pin.

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