A preparation method of a silicon-based III-V semiconductor material

Abstract

The present invention provides a method for preparing a silicon-based III-V semiconductor material. The method includes growing at least twice on a silicon substrate a basic epitaxial structural unit of a III-V semiconductor characterized by weakly associated crystallization. Each basic epitaxial structural unit includes three layers, namely a low-temperature layer, a medium-temperature layer, and a high-temperature layer from bottom to top, and a thermal cycle annealing must be inserted during the growth of the high-temperature layer. This method enables the top and bottom regions of the low-temperature layer to achieve weakly associated crystallization with each other, and at the same time enables the high-temperature layer together with the top region of the medium-temperature layer and the bottom region of the medium-temperature layer to achieve weakly associated crystalline purification with each other, thereby optimizing the crystal quality of the high-temperature layer. Based on a similar mechanism, the repeated growth of the basic epitaxial structural unit can further improve the crystal quality of the target epitaxial layer (i.e., the top epitaxial layer of the complete structure). By using this method, a silicon-based III-V semiconductor material with an extremely low threading dislocation density can be prepared.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for preparing a silicon-based III-V semiconductor material. Background Art

[0002] With the rapid development of information technology, the information transmission network based on microelectronics is becoming increasingly strained in the face of the growing demands for data transmission rate, information processing speed, etc. For such a predicament, using light as the carrier of information transmission and combining the existing mature microelectronics and optoelectronics technologies is a good solution. While giving full play to the mature process technology of silicon-based microelectronics, it can also take advantage of the extremely high transmission rate, high anti-interference ability, and low power consumption of optoelectronics. Silicon-based optoelectronic integration has become one of the important directions for the future development of large-scale integrated circuits. However, since silicon is an indirect bandgap material with extremely low luminescence efficiency and is difficult to be used as a gain medium, the silicon-based light source has become the biggest obstacle restricting the development of silicon-based optoelectronic integration. Among the implementation schemes of silicon-based light sources, the monolithic integration of III-V semiconductor light sources on silicon has good application prospects. However, there is usually a large lattice mismatch between silicon and direct bandgap III-V semiconductors, and the lattice mismatch will lead to mismatch stress and is mainly effectively released through threading dislocations. Therefore, a large number of threading dislocations will be generated when directly epitaxially growing III-V semiconductor materials on silicon, seriously affecting the performance of silicon-based light sources, especially greatly reducing the device lifetime.

[0003] When heteroepitaxially growing GaAs-based III-V semiconductor materials on silicon, although the lattice mismatch degree between GaAs and silicon is 4.1%, it will also generate threading dislocations with a surface density as high as 10 8 cm -2 or more. At this time, how to effectively block the upward propagation of threading dislocations to the laser active region becomes crucial.

[0004] Currently, the commonly used method for blocking threading dislocations is to introduce a strain structure containing lattice mismatch, such as a strained quantum well structure, a strained quantum dot structure, and a mixed structure of strained quantum wells and quantum dots. The mismatch stress generated in the strain structure is used to change the propagation direction of the threading dislocations to avoid the propagation of threading dislocations to the active region. Thus, the propagation of threading dislocations to the active region is reduced. However, the effect of the strain structure in blocking threading dislocations is also very limited, and the mismatch stress in the strain structure may also generate additional threading dislocations. Therefore, even with the introduction of the strain structure, the threading dislocation density of the silicon-based III-V semiconductor is still as high as 10 6 cm -2As described above, this severely restricts the continuous lasing of silicon-based quantum well lasers that can cover all wavelength windows of optical communication at room temperature for a long time. Affected by this, the lifespan of GaAs-based quantum well lasers on silicon is currently only a few hundred hours. Therefore, how to effectively block the propagation of threading dislocations has always been a difficult problem in silicon-based III-V semiconductor light sources. Summary of the Invention

[0005] The present invention provides a method for preparing a silicon-based III-V semiconductor material to solve the problem that the threading dislocation density is still relatively high in the epitaxial growth of existing silicon-based III-V semiconductor materials. Compared with the prior art, the present invention can significantly reduce the threading dislocation density of silicon-based III-V semiconductor materials, which helps to achieve continuous lasing of silicon-based III-V quantum well lasers at room temperature and improve their lifespan.

[0006] The present invention provides a method for preparing a silicon-based III-V semiconductor material, which includes:

[0007] Repeatedly grow the basic epitaxial structure unit of III-V semiconductor on the silicon substrate at least twice to form a repeatedly grown epitaxial structure;

[0008] Continuously grow III-V semiconductor material and / or III-V semiconductor device structure on the repeatedly grown epitaxial structure;

[0009] Among them, the repeatedly grown epitaxial structure includes two or more basic epitaxial structure units of III-V semiconductor; the growth process of the basic epitaxial structure unit includes:

[0010] (1) Grow a low-temperature layer under a first temperature condition;

[0011] (2) Grow a middle-temperature layer on the low-temperature layer under a second temperature condition, and the second temperature condition is higher than the first temperature condition;

[0012] (3) Epitaxially grow a high-temperature layer on the middle-temperature layer under a third temperature condition, and the third temperature condition is higher than the second temperature condition;

[0013] (4) Pause the epitaxial growth of the high-temperature layer during the epitaxial growth of the high-temperature layer, perform thermal cycle annealing, and then continue the epitaxial growth of the high-temperature layer.

[0014] According to a method for preparing a silicon-based III-V semiconductor material provided by an embodiment of the present invention, the repeatedly grown epitaxial structure refers to two basic epitaxial structure units or N basic epitaxial structure units, where N is an integer greater than 2; the basic epitaxial structure units in the repeatedly grown epitaxial structure are sequentially marked as the first unit, the second unit, up to the Nth unit from bottom to top;

[0015] The thermal cycle annealing causes weak-correlated crystallization to occur between the top region and the bottom region of the low-temperature layer of the III-V semiconductor basic epitaxial structure unit, and at the same time causes the high-temperature layer of the III-V semiconductor basic epitaxial structure unit together with the top region of the middle-temperature layer and the bottom region of the middle-temperature layer to achieve weakly correlated crystalline purification; the top region refers to the region where the thickness of the low-temperature layer, or the middle-temperature layer, or the high-temperature layer is more than 2 / 3; the bottom region refers to the region where the thickness of the low-temperature layer, or the middle-temperature layer, or the high-temperature layer is less than 1 / 3;

[0016] Among them, the crystallization refers to the transformation of the low-temperature layer from an amorphous state to a crystalline state, that is, the low-temperature layer is reshaped from a disordered lattice arrangement into a more regular lattice arrangement; the weakly correlated crystallization means that in the thermal cycle annealing, the crystallization processes in the top region and the bottom region of the low-temperature layer proceed simultaneously without a sequence, and the correlation between the two regions is reduced, thereby interrupting part of the path for the penetration dislocation to propagate upward in the low-temperature layer;

[0017] The crystalline purification refers to the further crystallization of the middle-temperature layer and the high-temperature layer, that is, the middle-temperature layer and the high-temperature layer are reshaped from a relatively regular lattice arrangement into an extremely regular lattice arrangement; the weakly correlated crystalline purification means that in the thermal cycle annealing, the crystalline purification at the interface between the top region of the high-temperature layer together with the middle-temperature layer and the bottom region of the interface between the middle-temperature layer and the low-temperature layer also proceeds simultaneously without a sequence, and the correlation between them is reduced, thereby improving the crystal quality of the high-temperature layer.

[0018] According to a method for preparing a silicon-based III-V semiconductor material provided by an embodiment of the present invention, the silicon substrate is:

[0019] A silicon substrate without a tilt angle, with a crystal plane direction of 100; or,

[0020] A silicon substrate with a tilt angle, with a crystal plane direction of 100.

[0021] According to a method for preparing a silicon-based III-V semiconductor material provided by an embodiment of the present invention, the pattern of the silicon substrate is "V"-shaped, hole-shaped, square-shaped or strip-shaped.

[0022] According to a method for preparing a silicon-based III-V semiconductor material provided by an embodiment of the present invention, the conditions for growing the low-temperature layer under the first temperature condition are: the temperature range is 350-550 °C, the flow ratio or beam ratio of the group V source to the group III source ranges from 20 to 1000, and the growth thickness range is 5-50 nm;

[0023] The conditions for growing the middle-temperature layer under the second temperature condition are: the temperature range is 550-650 °C, the flow ratio or beam ratio of the group V source to the group III source ranges from 50 to 1000, and the growth thickness range is 50-500 nm;

[0024] The conditions for epitaxially growing the high-temperature layer under the third temperature condition are as follows: the temperature range is 650 - 750 °C, the flow ratio or beam flux ratio of group V to group III is in the range of 50 - 1000, and the growth thickness range is 100 - 2500 nm.

[0025] According to a method for preparing a silicon-based group III-V semiconductor material provided by an embodiment of the present invention, the thermal cycle annealing is in-situ annealing, the annealing temperature range is 300 - 800 °C, and the number of times of the thermal cycle annealing is one or more;

[0026] The growth process of the basic epitaxial structure unit further includes:

[0027] (5) After the epitaxial growth of the high-temperature layer is completed, thermal cycle annealing is performed.

[0028] According to a method for preparing a silicon-based group III-V semiconductor material provided by an embodiment of the present invention, the low-temperature layer, the medium-temperature layer, and the high-temperature layer all use the same material.

[0029] According to a method for preparing a silicon-based group III-V semiconductor material provided by an embodiment of the present invention, the epitaxial growth uses metalorganic chemical vapor deposition (MOCVD) and / or molecular beam epitaxy (MBE).

[0030] According to a method for preparing a silicon-based group III-V semiconductor material provided by an embodiment of the present invention, the group III-V semiconductor material is one or more of group III-V semiconductor materials such as GaP-based, GaAs-based, InP-based, and GaSb-based semiconductor materials.

[0031] According to a method for preparing a silicon-based group III-V semiconductor material provided by an embodiment of the present invention, the group III-V semiconductor device structure includes but is not limited to group III-V semiconductor lasers, group III-V superluminescent light-emitting diodes, group III-V light-emitting diodes, group III-V optical amplifiers, group III-V photodetectors, and group III-V passive devices.

[0032] The present invention provides a method for preparing a silicon-based group III-V semiconductor material. By growing a low-temperature layer on a silicon substrate under a first temperature condition, growing a medium-temperature layer on the low-temperature layer under a second temperature condition, where the second temperature condition is higher than the first temperature condition, epitaxially growing a high-temperature layer on the medium-temperature layer under a third temperature condition, where the third temperature condition is higher than the second temperature condition, performing thermal cycle annealing, and forming a group III-V semiconductor device structure on the high-temperature epitaxial structure of the epitaxial growth.

[0033] By using the technical solution of the embodiment of the present invention, the thermal cycle annealing causes weakly correlated crystallization to occur in the top area of ​​the low-temperature layer grown for the first time and one side of the low-temperature layer near the interface between the silicon substrate and the low-temperature layer, causes weakly correlated crystallization to occur in the top area of ​​the low-temperature layer grown for the second time and one side of the low-temperature layer near the interface between the high-temperature layer grown for the first time epitaxially and the low-temperature layer grown for the second time, and also causes the high-temperature layer together with the top area of ​​the medium-temperature layer and the bottom area of ​​the medium-temperature layer to achieve weakly correlated crystalline purification with each other.

[0034] The weakly correlated crystallization refers to the crystallization of the low-temperature layer near the interface between the silicon substrate and the low-temperature layer and near the interface between the high-temperature layer of the first epitaxial growth and the low-temperature layer of the second growth, which is carried out simultaneously on one side of the low-temperature layer in the thermal cycle annealing without any order of precedence, and the correlation between each other is reduced, thereby interrupting the upward propagation path of the threading dislocation formed at the interface between the silicon substrate and the low-temperature layer, thereby shortening the upward penetration time of the misfit dislocation formed at the interface between the silicon substrate and the low-temperature layer.

[0035] The weakly correlated crystalline purification refers to the weakly correlated crystalline purification of the high temperature layer together with the top area of ​​the medium temperature layer and the bottom area of ​​the medium temperature layer, which are also carried out simultaneously and without sequence, and the correlation between them is reduced, thereby shortening the imperfection of the crystal structure at the interface, especially the time for the threading dislocation to continue to extend upward. This process method fully exerts the potential of the multi-step epitaxial growth process, reduces the threading dislocation density of silicon-based III-V semiconductor materials, and thus significantly improves the performance of silicon-based III-V semiconductor devices, especially light-emitting devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1 This is one of the schematic flow diagrams of the method for preparing silicon-based III-V semiconductor materials provided by an embodiment of the present invention;

[0038] Figure 2 This is the second flow chart of the method for preparing silicon-based III-V semiconductor materials provided by an embodiment of the present invention;

[0039] Figure 3 It is a cross-sectional view of a silicon-based III-V semiconductor material provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without any creative effort belong to the scope of protection of the present invention.

[0041] The inventors of the present invention have studied the prior art and found that when directly heteroepitaxially growing III-V semiconductor materials on a silicon substrate, although the number of nucleation points of the III-V semiconductor materials grown at low temperature is one order of magnitude or more more than that of the III-V semiconductor materials grown at high temperature on the silicon substrate. In theory, the growth mode with more nucleation points will cause more defects, especially threading dislocations. However, after characterizing the crystal quality of the III-V semiconductor materials obtained by two different growth methods (i.e., purely growing III-V semiconductor materials at high temperature on the silicon substrate, and growing III-V semiconductor materials at low temperature first and then at high temperature on the silicon substrate), it is found that the quality of the silicon-based III-V semiconductor materials with a low-temperature layer is much higher than that of the III-V semiconductor materials grown purely at high temperature. Therefore, the "low temperature - high temperature" two-step method has become the most commonly used and basic silicon-based III-V semiconductor heteroepitaxial method. However, there is no unified explanation for this unconventional phenomenon. The currently widely adopted explanation is that since the low-temperature layer formed by low-temperature growth is an amorphous state with a disordered arrangement of group III and group V elements (which has been confirmed by experiments), there are no threading dislocations in the low-temperature layer (there are no threading dislocations in the amorphous state of the crystal, but there are a large number of crystal defects). This makes the generation of threading dislocations in the III-V semiconductor materials in the "low temperature - high temperature" two-step method closely related to the subsequent high-temperature growth process, rather than occurring near the nucleation points at the beginning. Therefore, the crystal quality of the finally obtained silicon-based III-V semiconductor materials containing a low-temperature layer will be greatly improved.

[0042] As described above, since the III-V low-temperature layer is an amorphous material (amorphous state, materials in nature can be divided into single crystal, polycrystal and amorphous according to the crystal structure), and there are a large number of defects inside. Therefore, when researchers in the field grow a III-V high-temperature layer on the III-V low-temperature layer or continue to grow a III-V high-temperature layer on the low-temperature layer, they usually do not simply repeat the two-step method in the heteroepitaxy of silicon-based III-V semiconductors (in fact, they do not repeat the low-temperature growth of III-V semiconductor materials many times). For example, they do not simply use the "low temperature - high temperature - low temperature - high temperature..." method for the heteroepitaxy of silicon-based III-V semiconductors.

[0043] Furthermore, there is a large lattice mismatch between silicon and III-V direct bandgap semiconductor materials (for example, the lattice mismatch between silicon and GaAs is as high as 4.1%). This will generate a large number of threading dislocations during the heteroepitaxial growth of III-V semiconductors on silicon substrates, which will penetrate through to the surface of the III-V high-temperature layer. To effectively reduce the surface threading dislocation density of III-V semiconductors on silicon substrates, almost all reports on the heteroepitaxy of III-V semiconductors on silicon introduce thermal cycle annealing during the two-step growth process (specifically, thermal cycle annealing is introduced during or after the high-temperature growth of III-V semiconductor materials). This is also recognized by researchers as the most effective method. Here, thermal cycle annealing means heating the III-V semiconductor material on silicon substrate to a certain temperature and holding for a period of time, then cooling down to a certain temperature and holding for the same period of time, and repeating such operations multiple times.

[0044] The mechanism by which thermal cycle annealing reduces the threading dislocation density recognized by researchers currently is: sufficient thermal stress is generated through thermal cycle annealing to make the threading dislocations slip, and then the threading dislocations collide with each other during the slipping process and partially annihilate. Since the threading dislocation density cannot be reduced to an extremely low level through a single thermal cycle annealing, researchers often repeatedly insert thermal cycle annealing at different positions of the III-V layer grown at high temperature to minimize the threading dislocation density. This operation of reducing threading dislocations can be equivalently regarded as: first growing the III-V low-temperature layer on the silicon substrate under low-temperature conditions, and then growing the required III-V semiconductor epitaxial structure two or more times under high-temperature conditions, and performing thermal cycle annealing after the growth of each III-V semiconductor epitaxial structure, that is, the "low temperature - high temperature - thermal cycle annealing - high temperature - thermal cycle annealing..." mode. The thermal stress generated by thermal cycle annealing utilizes the difference in the thermal expansion coefficient α s of the silicon substrate and the thermal expansion coefficient α f of the III-V semiconductor material grown epitaxially. min It is achieved through the temperature difference between the lowest annealing temperature T max and the highest annealing temperature T. The specific magnitude of the thermal stress can be calculated by (Considering the process cost of introducing thermal cycle annealing in the heteroepitaxy of III-V semiconductors on silicon substrates, T min is often not lower than 350 °C).

[0045] Based on the two-step method, during the experiment, the researchers also found that inserting other temperature layers between the low-temperature layer and the high-temperature layer (there is no perfect theoretical basis for this growth method, only experimental results), collectively referred to as multi-step growth (three-step method, four-step method, etc.), can further improve the crystal quality. Although the combination of various growth methods and the introduction of thermal stress can reduce the threading dislocation density, it is still impossible to reduce the large number of threading dislocations between silicon and III-V direct-bandgap semiconductor materials to the ideal range.

[0046] However, the inventor found during the research process that the effect of reducing threading dislocations brought about by the "rapid cooling" process in thermal cycle annealing not only includes the slip and mutual collision annihilation of threading dislocations, but also should include the crystalline state transformation (amorphous - single crystal) process of the low-temperature layer. The rapid crystalline state transformation process of the low-temperature layer plays a crucial role in reducing threading dislocations. That is to say, the amorphous characteristics of the low-temperature layer, especially the characteristics of defects existing in the amorphous state, make there be no threading dislocations in the pure low-temperature layer. However, the propagation of threading dislocations must rely on the characteristics of the crystal medium. Therefore, it is not difficult to think that the propagation of threading dislocations can be eliminated by borrowing the process of amorphous to single-crystal state transformation, and thus the effect of reducing the threading dislocation density can be achieved. At the same time, it is worth noting that the mutual correlation between non-adjacent regions in the amorphous state is weak. Therefore, during the crystallization process, especially the bottom and top regions of the amorphous layer are weakly correlated with each other. That is to say, the dislocations propagating upward generated in the bottom region during the crystallization process will not affect the crystallization process of the bottom region. The top region completes crystallization before the dislocations propagate to the top region, which can force the dislocations originally propagating upward to change their propagation directions to form other forms of defects, such as interface-resident dislocations, dislocation loops, etc. Moreover, the slip of the common threading dislocations in the high-temperature layer eliminates the threading dislocations originally existing in the high-temperature layer, which not only directly reduces the surface threading dislocation density but also blocks the upward propagation of dislocations from below. Under the action of the above-mentioned various factors, the threading dislocations that could originally propagate upward are forced to be converted into other forms of defects, greatly reducing the propagation of threading dislocations inside the crystal, and thus extremely effectively reducing the threading dislocation density.

[0047] This discovery of the present invention expands the researchers' understanding of the role of growth layers under non-high-temperature (low-temperature and medium-temperature) conditions, especially the traditional understanding of the role of III-V low-temperature layers. Next, the embodiments of the present invention analyze in more detail the crystallization process of the low-temperature layer in silicon-based III-V heteroepitaxy. Since the crystallization process occurs during the growth of III-V semiconductor materials, especially under the action of thermal cycle annealing, all parts of the silicon-based III-V epitaxial structure simultaneously experience the same temperature change. This makes the crystallization of the top region of the III-V low-temperature layer and the bottom region of the III-V low-temperature layer near the silicon substrate-III-V low-temperature layer interface occur simultaneously without a sequence, and their correlation is reduced but not uncorrelated, which is called "weak-correlation crystallization". It can be imagined that there will be a time difference in the crystallization process of the high-temperature layer and the III-V low-temperature layer in the III-V epitaxial structure under the action of thermal cycle annealing. The high-temperature layer will complete crystallization first. Therefore, the threading dislocations in the low-temperature layer will not propagate upward and transform into other forms of defects such as dislocation loops and interface-resident dislocations during the continued crystallization process of the low-temperature layer. Instead, the low-temperature layer plays a crucial role in reducing threading dislocations during the thermal cycle annealing process, rather than simply dislocation slip as commonly understood.

[0048] In order to further exert the effect of reducing the threading dislocation density through the crystalline state transformation, a III-V medium-temperature layer is also grown on the III-V low-temperature layer. Since the growth temperature of the III-V medium-temperature layer is low and it is a single crystal with a relatively regular lattice arrangement (not completely long-range ordered, but also including some medium-range ordered arrangements), it can still exert the ability to reduce the threading dislocation density through the crystalline state transformation. In this way, a better crystal quality of silicon-based III-V semiconductor materials can be obtained compared with the two-step method (low temperature + high temperature).

[0049] Specifically, a III-V group low-temperature layer with a moderate thickness is first grown on a silicon substrate, and the low-temperature layer remains in an amorphous state until the III-V group medium-temperature layer is epitaxially grown. When the epitaxial growth of the III-V group medium-temperature layer begins, the crystallization process of the low-temperature layer is also initiated. Since the temperature step from low to medium temperature is relatively low, the transformation process from amorphous to single crystal is weak but still exists. After the growth of the medium-temperature layer is completed, the epitaxial growth of the III-V group high-temperature layer is continued. At this time, not only is there the crystallization effect of the low-temperature layer, but also the purification effect of the medium-temperature layer and the high-temperature layer (the purification process is very similar to the crystallization process. When growing the III-V group high-temperature layer continuously on a III-V group medium-temperature layer with better quality, under the action of thermal stress, the III-V group low-temperature layer will start to fully crystallize, and at the same time, the III-V group medium-temperature layer and the high-temperature layer will also reshape from a relatively regular lattice arrangement to an extremely regular lattice arrangement. We call this process "crystalline purification"), that is, the transformation from amorphous to single crystal, and the transformation from a crystal with a relatively regular arrangement to a crystal with an extremely regular arrangement. However, due to the low temperature gradient, the thermal stress generated is small and the duration is long, and there is not enough time difference between the high-temperature layer and the low-temperature layer. At this time, the crystal quality obtained is still poor. Finally, a thermal cycle annealing step is added to the high-temperature layer. Since the temperature gradient generated by thermal cycle annealing is generated quickly, while the high-temperature layer completes the integration of threading dislocations, there will be enough time difference with the low-temperature layer and the medium-temperature layer to reduce the upward propagation of threading dislocations, and fully utilize the crystallization of the low-temperature layer, the purification of the medium-temperature layer and the high-temperature layer to reduce the threading dislocation density.

[0050] Although the crystal quality of the high-temperature layer is greatly improved through this process, due to a large number of threading dislocations generated at the interface between silicon and the III-V group low-temperature layer, it is still not enough to reduce the surface threading dislocation density to a very low level. It is precisely because the inventors of this case discovered the growth laws of low temperature and medium temperature during the growth process that they are confident that "crystallization" and "purification" can effectively reduce the threading dislocations and will not bring any adverse factors. Therefore, the crystallization and purification effects can be used again with confidence to further reduce, that is, repeat "low temperature - medium temperature - high temperature - thermal cycle annealing" twice or more times on the III-V group high-temperature layer to reduce the threading dislocation density to the ideal range. The entire growth process is "low temperature - medium temperature - high temperature - thermal cycle annealing - low temperature - medium temperature - high temperature - thermal cycle annealing".

[0051] The following combines Figure 1 , and specifically elaborates on the preparation method of the silicon-based III-V group semiconductor material provided by the embodiments of the present invention. Referring to Figure 1 , this method specifically includes the following steps:

[0052] Step 110: Repeatedly grow the III-V group semiconductor epitaxial structure unit on the silicon substrate at least twice to form a repeatedly grown epitaxial structure;

[0053] Step 120: Continuously epitaxially grow III-V semiconductor materials and / or III-V semiconductor device structures on the repeating growth epitaxial structure.

[0054] Reference Figure 2 , to grow III-V semiconductor epitaxial structure units, including the following steps:

[0055] Step 210: Grow a low-temperature layer under a first temperature condition;

[0056] Step 220: Under a second temperature condition higher than the first temperature condition, grow a medium-temperature layer on the low-temperature layer;

[0057] Step 230: Under a third temperature condition higher than the second temperature condition, epitaxially grow a high-temperature layer on the medium-temperature layer, and a thermal cycle annealing must be inserted during the growth of the high-temperature layer;

[0058] Step 240: After the epitaxial growth of the high-temperature layer is completed, perform thermal cycle annealing.

[0059] Using the technical solution of this embodiment, a III-V semiconductor basic structure (i.e., a basic epitaxial structure unit) composed of a low-temperature layer, a medium-temperature layer, and a high-temperature layer stacked is obtained.

[0060] Please refer to Figure 3 As shown, the embodiment of the present invention adopts the above three-step method to generate silicon-based III-V semiconductor materials, specifically including:

[0061] A first low-temperature layer 311 located on a silicon substrate 310;

[0062] A first medium-temperature layer 312 located on the first low-temperature layer 311;

[0063] A first high-temperature layer 313 located on the first medium-temperature layer 312;

[0064] A second low-temperature layer 321 located on the first high-temperature layer 313;

[0065] A second medium-temperature layer 322 located on the second low-temperature layer 321;

[0066] A second high-temperature layer 323 located on the second medium-temperature layer 322.

[0067] In a specific embodiment of the present invention, the preparation method of the silicon-based III-V semiconductor material can form one or more groups of low-temperature layers, medium-temperature layers, and high-temperature layers, which is not limited by Figure 3 the embodiment shown, and can be selected according to needs.

[0068] Using the technical solution of the embodiment of the present invention, in the two or more unit repeated growth epitaxial structure (i.e., the repeated growth epitaxial structure), the III-V semiconductor epitaxial structure units from bottom to top at least include a first III-V semiconductor epitaxial structure unit (i.e., the first unit) and a second III-V semiconductor epitaxial structure unit (i.e., the second unit).

[0069] Thermal cycle annealing causes weak-correlated crystallization to occur on the low-temperature layer side near the interface between the top region of the low-temperature layer of the first III-V semiconductor epitaxial structure unit and the silicon substrate and the low-temperature layer, and also causes weak-correlated crystallization to occur on the low-temperature layer side near the interface between the top region of the low-temperature layer of the second III-V semiconductor epitaxial structure unit and the high-temperature layer of the first III-V semiconductor epitaxial structure unit and the low-temperature layer of the second III-V semiconductor epitaxial structure unit. It also causes the top region of the high-temperature layer together with the middle-temperature layer to achieve weakly correlated crystalline purification with the bottom region of the middle-temperature layer.

[0070] The weak-correlated crystallization refers to the crystallization occurring simultaneously and without a sequence on the low-temperature layer side near the interface between the silicon substrate and the low-temperature layer and on the low-temperature layer side near the interface between the high-temperature layer of the first III-V semiconductor epitaxial structure unit and the low-temperature layer of the second III-V semiconductor epitaxial structure unit during the thermal cycle annealing, and the correlation between them is reduced, thus interrupting the upward propagation path of the threading dislocations formed at the interface between the silicon substrate and the low-temperature layer.

[0071] The weakly correlated crystalline purification refers to the top region of the high-temperature layer together with the middle-temperature layer achieving weakly correlated crystalline purification with the bottom region of the middle-temperature layer, which also occurs simultaneously and without a sequence, and the correlation between them is reduced, thereby optimizing the crystal quality of the high-temperature layer.

[0072] Optionally, the weak-correlated crystallization occurring on the low-temperature layer side near the interface between the top region of the low-temperature layer of the first III-V semiconductor epitaxial structure unit and the silicon substrate and the low-temperature layer means that the low-temperature layer changes from an amorphous state to a crystalline state, that is, the low-temperature layer is reshaped from a disordered lattice arrangement into a more regular lattice arrangement.

[0073] The top region of the high-temperature layer together with the middle-temperature layer achieving weakly correlated crystalline purification with the bottom region of the middle-temperature layer means that the middle-temperature layer and the high-temperature layer are further crystallized, that is, the middle-temperature layer is reshaped from a more regular lattice arrangement into an extremely regular lattice arrangement.

[0074] Optionally, when using two or more sets of three-step processes to generate III-V semiconductor materials, since the first set of low-temperature layer - medium-temperature layer - high-temperature layer mainly addresses the lattice mismatch problem of silicon-based substrates, a certain amount of threading dislocations will be generated. The second set of low-temperature layer - medium-temperature layer - high-temperature layer starts to address the threading dislocations remaining in the first set of epitaxial structures. Through epitaxial growth of at least two sets of epitaxial structures, since each set has an amorphous structure and an annealing step, the upward-propagating threading dislocations can be effectively blocked.

[0075] In the embodiments of the present invention, at least two sets of low-temperature, medium-temperature, and high-temperature growth steps can be used to generate III-V semiconductor materials. Through a large number of experiments, it has been proven that this can not only reduce the threading dislocation density but also ensure that the finally formed III-V epitaxial structure has an appropriate thickness.

[0076] In the embodiments of the present invention, the silicon substrate is an unbiased (100) crystal plane silicon substrate, or a biased (100) crystal plane silicon substrate, or a silicon substrate of all crystal planes other than the (100) crystal plane. Preferably, it is an unbiased (100) crystal plane silicon substrate. The silicon substrate can be a patterned silicon substrate, and the patterns include but are not limited to "V"-shaped, hole-shaped, square-shaped, and strip-shaped. The pattern size is at the micron, sub-micron, or nano scale.

[0077] The silicon-based III-V semiconductor material can be in an amorphous structure. Through the low-temperature growth conditions provided by the first temperature condition, an amorphous layer grown at low temperature on the silicon substrate serves as a bridge connecting the diamond crystal structure silicon substrate and the zinc blende structure III-V semiconductor material. Through thermal cycle annealing, the amorphous low-temperature layer undergoes weak-correlation crystallization, reducing the number of threading dislocations formed due to lattice mismatch between the silicon substrate and the III-V semiconductor material.

[0078] The amorphous structure grown at low temperature in the second set is used on the surface of the III-V semiconductor material structure that has been epitaxially grown. At this time, the role of the amorphous structure is different from that in the first set of epitaxial growth. First, both the upper and lower connections of this amorphous structure are III-V semiconductor materials with a zinc blende structure. Second, this amorphous layer, as a disordered amorphous structure, changes or even blocks the propagation process of threading dislocations in the underlying long-range ordered single-crystal structure. In addition, since the lattice constant of this amorphous layer at this time matches the lattice constant of the III-V semiconductor material to be grown, no new threading dislocations will be further generated.

[0079] The embodiments of the present invention give full play to the characteristics of low-temperature amorphous growth. The method is simple but extremely effective in reducing defects and improving crystal quality. Compared with the commonly used high-mismatch dislocation blocking layer, the structure of the present invention does not require re-introducing additional lattice mismatch, greatly reducing the structural stress, and this method is generally applicable, effective, simple, and easy to implement.

[0080] In an embodiment of the present invention, the silicon substrate is a patterned silicon substrate, and the pattern of the patterned silicon substrate is "V"-shaped, hole-shaped, square-shaped or strip-shaped.

[0081] In an embodiment of the present invention, a strain layer can also be formed on the high-temperature layer or the medium-temperature layer, and the strain layer can block the upward propagation of threading dislocations.

[0082] In an embodiment of the present invention, the conditions for growing the low-temperature layer under the first temperature condition are: the temperature range is 350 - 550 °C, the flow ratio or beam ratio of group V source to group III source ranges from 20 to 1000, and the growth thickness range is 5 - 50 nm;

[0083] The conditions for growing the medium-temperature layer under the second temperature condition are: the temperature range is 550 - 650 °C, the flow ratio or beam ratio of group V source to group III source ranges from 50 to 1000, and the growth thickness range is 50 - 500 nm;

[0084] The conditions for epitaxially growing the high-temperature layer under the third temperature condition are: the temperature range is 650 - 750 °C, the flow ratio or beam ratio of group V to group III ranges from 50 to 1000, and the growth thickness range is 100 - 2500 nm.

[0085] The process parameters proposed in the embodiments of the present invention are not isolated from each other, and the parameters are interrelated. Therefore, it is necessary to fully refer to the correlation relationship between the parameters of each step and conduct a large number of experiments to obtain them.

[0086] In an embodiment of the present invention, the annealing temperature range of the thermal cycle annealing is: 300 - 800 °C. Using thermal cycle annealing can promote the recrystallization of the high-temperature layer and the underlying low-temperature layer, reduce the formation of threading dislocations in the low-temperature layer, so as to achieve the ability to reduce the threading dislocation density.

[0087] In an embodiment of the present invention, thermal cycle annealing is performed after at least one of the low-temperature layer, the medium-temperature layer, and the high-temperature layer. In this way, thermal cycle annealing can be performed after any layer or separately after the formation of the high-temperature layer.

[0088] In an embodiment of the present invention, the low-temperature layer, the medium-temperature layer, and the high-temperature layer all use the same material.

[0089] In a specific embodiment of the present invention, the epitaxial growth of any of the above layers adopts metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) or a combination of MOCVD and MBE, so as to achieve epitaxial growth of silicon-based III-V semiconductor materials on a bias-free silicon substrate after cleaning, and to suppress the generation of antiphase domains and threading dislocations.

[0090] The following describes the preparation method of the silicon-based III-V semiconductor material according to the embodiment of the present invention with specific examples.

[0091] In one embodiment of the present invention, a method for epitaxially growing a silicon-based group III-V semiconductor material on a cleaned non-offset-angle silicon substrate by using MOCVD to suppress the generation of antiphase domains and threading dislocations is provided, but it is not limited to MOCVD.

[0092] In this embodiment, the silicon substrate is a non-offset-angle (100) silicon substrate, the group III-V arsenide is made of GaAs material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethylgallium, the group V source is high-purity arsine, and the reaction chamber pressure is 100 Torr. The specific steps of the method for preparing the silicon-based group III-V semiconductor material provided in this embodiment are as follows:

[0093] Step 301: Clean the silicon substrate to remove impurities such as organic substances, metal particles, and oxide layers on the silicon substrate;

[0094] Step 302: Spin-dry the cleaned silicon substrate and place the spin-dried silicon substrate into the epitaxial growth chamber;

[0095] Step 303: Raise the chamber temperature to 850 °C and hold for 10 min, lower the growth chamber temperature to 420 °C to grow a 10-nm GaAs low-temperature layer with a V / III flow ratio of 200;

[0096] Step 304: Raise the temperature to 650 °C to grow a 200-nm GaAs medium-temperature layer with a group V / III flow ratio of 100;

[0097] Step 305: Raise the temperature to 680 °C to grow a 500-nm GaAs high-temperature layer with a group V / III flow ratio of 100;

[0098] Step 306: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0099] Step 307: At 680 °C, grow a 100-nm GaAs high-temperature layer with a group V / III flow ratio of 100;

[0100] Step 308: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0101] Step 309: At 680 °C, grow a 100-nm GaAs high-temperature layer with a group V / III flow ratio of 100;

[0102] Step 310: Lower the temperature to 420 °C to grow a 10-nm GaAs low-temperature layer with a group V / III flow ratio of 200;

[0103] Step 311: Raise the temperature to 650 °C and grow a 200-nm-thick GaAs mid-temperature layer with a V / III group flow ratio of 100.

[0104] Step 312: Raise the temperature to 680 °C and grow a 500-nm-thick GaAs high-temperature layer with a V / III group flow ratio of 100.

[0105] Step 313: Raise the temperature to 750 °C and hold for 5 min, then slowly lower the temperature to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing.

[0106] Step 314: At 680 °C, grow a 100-nm-thick GaAs high-temperature layer with a V / III group flow ratio of 100.

[0107] Step 315: Raise the temperature to 750 °C and hold for 5 min, then slowly lower the temperature to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing.

[0108] Step 316: At 680 °C, grow a 100-nm-thick GaAs high-temperature layer with a V / III flow ratio of 100.

[0109] Step 317: Based on the GaAs epitaxial layer, perform epitaxial growth of the quantum well structure. A semiconductor quantum well structure (Semiconductor quantum wells) refers to a structure grown in a sandwich style from two semiconductor materials.

[0110] In another embodiment of the present invention, the silicon substrate is a biased (100) silicon substrate, the III-V group arsenide is made of InP material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethylgallium, the group V source is high-purity phosphine, and the reaction chamber pressure is 100 Torr. The specific steps of the method for preparing the silicon-based III-V group semiconductor material provided in this embodiment are as follows:

[0111] Step 401: Clean the silicon substrate to remove organic substances, metal particles, and oxide layers on the silicon substrate.

[0112] Step 402: Spin-dry the cleaned silicon substrate and place the spin-dried silicon substrate into the epitaxial growth chamber.

[0113] Step 403: Raise the chamber temperature to 750 °C and hold for 10 min, lower the growth chamber temperature to 420 °C and grow a 10-nm-thick InP low-temperature layer with a V / III group flow ratio of 990.

[0114] Step 404: Raise the temperature to 650 °C and grow a 200-nm-thick InP mid-temperature layer with a V / III group flow ratio of 400.

[0115] Step 405: Raise the temperature to 680 °C and grow a 300-nm InP high-temperature layer with a V / III group flow ratio of 400;

[0116] Step 406: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0117] Step 407: At 680 °C, grow a 100-nm InP high-temperature layer with a V / III group flow ratio of 400;

[0118] Step 408: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0119] Step 409: At 680 °C, grow a 100-nm InP high-temperature layer with a V / III group flow ratio of 400;

[0120] Step 410: Lower the temperature to 420 °C and grow a 10-nm InP low-temperature layer with a V / III group flow ratio of 990;

[0121] Step 411: Raise the temperature to 650 °C and grow a 200-nm InP medium-temperature layer with a V / III group flow ratio of 400;

[0122] Step 412: Raise the temperature to 680 °C and grow a 300-nm InP high-temperature layer with a V / III group flow ratio of 400;

[0123] Step 413: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0124] Step 414: At 680 °C, grow a 100-nm InP high-temperature layer with a V / III group flow ratio of 400;

[0125] Step 415: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, and then raise the temperature to 680 °C to complete annealing;

[0126] Step 416: At 680 °C, grow a 100-nm InP high-temperature layer with a V / III group flow ratio of 400.

[0127] Step 417: On the basis of the InP epitaxial layer, perform epitaxial growth of a superluminescent diode structure. A semiconductor superluminescent diode is an optoelectronic semiconductor device that emits broadband light based on the superluminescence phenomenon.

[0128] In another embodiment of the present invention, the silicon substrate is a (100) SOI substrate, the III-V arsenide is made of GaSb material, the MOCVD carrier gas is high-purity hydrogen, the group III organic source is high-purity trimethylgallium, the group V source is high-purity stibine, and the reaction chamber pressure is 100 Torr. The specific steps of the method for preparing the silicon-based III-V semiconductor material provided in this embodiment are as follows:

[0129] Step 501: Clean the silicon substrate to remove impurities such as organic substances, metal particles, and oxide layers on the silicon substrate;

[0130] Step 502: Spin-dry the cleaned silicon substrate and place the spin-dried silicon substrate into the epitaxial growth chamber;

[0131] Step 503: Raise the chamber temperature to 750 °C and maintain it for 10 min, lower the growth chamber temperature to 420 °C to grow a 10-nm GaSb low-temperature layer, and the V / III group flow ratio is 250;

[0132] Step 504: Raise the temperature to 650 °C and grow a 200-nm GaSb medium-temperature layer, and the V / III group flow ratio is 100;

[0133] Step 505: Raise the temperature to 680 °C and grow a 300-nm GaSb high-temperature layer, and the V / III group flow ratio is 100;

[0134] Step 506: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, then raise the temperature to 680 °C to complete annealing;

[0135] Step 507: At 680 °C, grow a 100-nm GaSb high-temperature layer, and the V / III flow ratio is 100;

[0136] Step 508: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, then raise the temperature to 680 °C to complete annealing;

[0137] Step 509: At 680 °C, grow a 100-nm GaSb high-temperature layer, and the V / III flow ratio is 100;

[0138] Step 510: Lower the temperature to 420 °C to grow a 10-nm GaSb low-temperature layer, and the V / III flow ratio is 250;

[0139] Step 511: Raise the temperature to 650 °C and grow a 200-nm GaSb medium-temperature layer, and the V / III group flow ratio is 100;

[0140] Step 512: Raise the temperature to 680 °C and grow a 300-nm-thick high-temperature GaSb layer with a V / III group flow ratio of 100;

[0141] Step 513: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, then raise the temperature to 680 °C to complete annealing;

[0142] Step 514: At 680 °C, grow a 100-nm-thick high-temperature GaSb layer with a V / III group flow ratio of 100;

[0143] Step 515: Raise the temperature to 750 °C and hold for 5 min, slowly lower it to 350 °C and hold for 400 s, then raise the temperature to 680 °C to complete annealing;

[0144] Step 516: At 680 °C, grow a 100-nm-thick high-temperature GaSb layer with a V / III group flow ratio of 100.

[0145] Step 517: On the basis of the GaSb epitaxial layer, perform epitaxial growth of a quantum dot structure. A quantum dot (English: Quantum Dot) is a semiconductor nanostructure that confines excitons in three spatial directions. The epitaxial growth method refers to growing a new crystal on a substrate material. If the crystal is small enough, quantum dots will be formed. According to different growth mechanisms, this method can be further divided into chemical vapor deposition and molecular beam epitaxy.

[0146] As can be seen from the above embodiments, the III-V semiconductor materials include one or more of GaP-based, GaAs-based, InP-based, and GaSb-based semiconductor materials, preferably GaAs-based and InP-based materials. The materials include, but are not limited to, binary materials such as AlP, GaP, InP, AlAs, GaAs, AlSb, GaSb, InSb, etc., ternary materials such as BGaP, BAlP, AlGaP, InGaP, AlGaAs, InGaAs, AlGaSb, InGaSb, GaAsSb, etc., and quaternary materials such as BGaAsP, AlGaAsP, InGaAsP, AlGaInAs, InGaAsSb, etc. No specific limitation is made here.

[0147] In addition, in the embodiments of the present invention, the III-V semiconductor device structures include, but are not limited to, III-V semiconductor lasers, III-V superluminescent light-emitting diodes, III-V light-emitting diodes, III-V optical amplifiers, III-V photodetectors, and III-V passive devices.

[0148] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing a silicon-based III-V semiconductor material, characterized in that, comprising: repeatedly growing a III-V semiconductor basic epitaxial structure unit on a silicon substrate at least twice to form a repeatedly grown epitaxial structure; continuing to epitaxially grow a III-V semiconductor material and / or a III-V semiconductor device structure on the repeatedly grown epitaxial structure; wherein, the repeatedly grown epitaxial structure includes two or more III-V semiconductor basic epitaxial structure units; the growth process of the basic epitaxial structure unit includes: (1) growing a low-temperature layer under a first temperature condition; (2) growing a middle-temperature layer on the low-temperature layer under a second temperature condition, the second temperature condition being higher than the first temperature condition; (3) epitaxially growing a high-temperature layer on the middle-temperature layer under a third temperature condition, the third temperature condition being higher than the second temperature condition; (4) pausing the epitaxial growth of the high-temperature layer during the epitaxial growth of the high-temperature layer, performing thermal cycle annealing, and then continuing the epitaxial growth of the high-temperature layer; the thermal cycle annealing causes weak-correlated crystallization of the top region and the bottom region of the low-temperature layer of the III-V semiconductor basic epitaxial structure unit to interrupt part of the upward propagation path of threading dislocations in the low-temperature layer; the thermal cycle annealing simultaneously causes the high-temperature layer of the III-V semiconductor basic epitaxial structure unit together with the top region and the bottom region of the middle-temperature layer to achieve weakly correlated crystalline purification with each other to improve the crystal quality of the high-temperature layer.

2. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that, the repeatedly grown epitaxial structure refers to two basic epitaxial structure units or N basic epitaxial structure units, where N is an integer greater than 2; the basic epitaxial structure units in the repeatedly grown epitaxial structure are sequentially labeled as the first unit, the second unit, up to the Nth unit from bottom to top; the thermal cycle annealing causes weak-correlated crystallization of the top region and the bottom region of the low-temperature layer of the III-V semiconductor basic epitaxial structure unit, and simultaneously causes the high-temperature layer of the III-V semiconductor basic epitaxial structure unit together with the top region and the bottom region of the middle-temperature layer to achieve weakly correlated crystalline purification with each other; the top region refers to a region with a thickness of more than 2 / 3 of the low-temperature layer, or the middle-temperature layer, or the high-temperature layer; the bottom region refers to a region with a thickness of less than 1 / 3 of the low-temperature layer, or the middle-temperature layer, or the high-temperature layer; wherein, the crystallization refers to the transformation of the low-temperature layer from an amorphous state to a crystalline state, that is, the low-temperature layer is reshaped from a disordered lattice arrangement into a more regular lattice arrangement; the weak-correlated crystallization refers to the simultaneous crystallization process in the top region and the bottom region of the low-temperature layer during the thermal cycle annealing without a sequential order, and the correlation between the two regions is reduced, thereby interrupting part of the upward propagation path of threading dislocations in the low-temperature layer. The crystalline purification means that the intermediate-temperature layer and the high-temperature layer are further crystallized, that is, the intermediate-temperature layer and the high-temperature layer are reshaped from a relatively regular lattice arrangement into an extremely regular lattice arrangement; the weakly associated crystalline purification means that during thermal cycle annealing, the crystalline purification at the interface bottom region between the high-temperature layer together with the top region of the intermediate-temperature layer and the intermediate-temperature layer and the low-temperature layer is also carried out simultaneously without a sequence, and the association between them is reduced, thereby improving the crystal quality of the high-temperature layer.

3. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the silicon substrate is: a silicon substrate without a tilt angle, with a crystal plane direction of 100; or, a silicon substrate with a tilt angle, with a crystal plane direction of 100.

4. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the pattern of the silicon substrate is "V"-shaped, hole-shaped, square-shaped or strip-shaped.

5. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the conditions for growing the low-temperature layer under the first temperature condition are: the temperature range is 350 - 550 °C, the flow ratio or beam ratio of the group-V source to the group-III source is in the range of 20 - 1000, and the growth thickness range is 5 - 50 nm; the conditions for growing the intermediate-temperature layer under the second temperature condition are: the temperature range is 550 - 650 °C, the flow ratio or beam ratio of the group-V source to the group-III source is in the range of 50 - 1000, and the growth thickness range is 50 - 500 nm; the conditions for epitaxially growing the high-temperature layer under the third temperature condition are: the temperature range is 650 - 750 °C, the flow ratio or beam ratio of group-V to group-III is in the range of 50 - 1000, and the growth thickness range is 100 - 2500 nm.

6. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the thermal cycle annealing is in-situ annealing, the annealing temperature range is 300 - 800 °C, and the number of times of the thermal cycle annealing is one or more; the growth process of the basic epitaxial structure unit further includes: (5) After the epitaxial growth of the high-temperature layer is completed, thermal cycle annealing is carried out.

7. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the low-temperature layer, the intermediate-temperature layer and the high-temperature layer all use the same material.

8. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the epitaxial growth adopts metalorganic chemical vapor deposition MOCVD and / or molecular beam epitaxy MBE.

9. The method for preparing a silicon-based III-V semiconductor material according to claim 1, characterized in that the III-V semiconductor material is one or more of GaP-based, GaAs-based, InP-based and GaSb-based semiconductor materials.

10. The method for preparing a silicon-based III-V semiconductor material according to any one of claims 1 - 9, characterized in that The III-V semiconductor device structures include, but are not limited to, III-V semiconductor lasers, III-V superluminescent light-emitting diodes, III-V light-emitting diodes, III-V optical amplifiers, III-V photodetectors, and III-V passive devices.

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