Gate and method of manufacturing a mosfet

Abstract

The application relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a gate and a semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; sequentially forming an undoped first polysilicon layer and a carbon-doped second polysilicon layer on the semiconductor substrate; performing plasma treatment on the surface of the second polysilicon layer by using nitride; performing P-type ion implantation on the second polysilicon layer; and etching the second polysilicon layer, the first polysilicon layer and the gate dielectric layer to form a gate stack. In the embodiment, NH3 gas is used to in-situ dope the surface of the carbon-doped gate polysilicon layer to form a nitride protective layer, so that the recess of the gate polysilicon layer caused by F in BF3 is avoided, and the yield of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a manufacturing method of a gate and a MOSFET. BACKGROUND

[0002] The existing step of forming a gate is to grow a polysilicon gate in two stages, as shown in the following figure. First, undoped polysilicon 10' is grown to a certain thickness, and carbon-doped polysilicon 11' is grown in situ to prevent boron penetration. Then, boron is implanted by plasma doping with BF3 gas to form P-type dopants. Then, active processing is performed to form a P-MOS gate. However, during ion implantation of BF3 plasma, due to the etching characteristics of F, polysilicon gate recess occurs. Compared with the wafer center, the plasma density at the wafer edge is dense, and the amount of recess is relatively large, causing loss of polysilicon gate (GATE POLY). Figure 1 SUMMARY

[0003] The present application at least partially solves the above technical problems in the related art. To this end, the present application provides a manufacturing method of a gate and a MOSFET to solve at least one of the above technical problems.

[0004] To achieve the above-mentioned purpose, the first aspect of the present application provides a manufacturing method of a gate, comprising:

[0005] providing a semiconductor substrate;

[0006] forming a gate dielectric layer on the semiconductor substrate;

[0007] forming an undoped first polysilicon layer and a carbon-doped second polysilicon layer on the semiconductor substrate in sequence;

[0008] performing plasma treatment on the surface of the second polysilicon layer using nitride;

[0009] performing P-type ion implantation on the second polysilicon layer;

[0010] etching the second polysilicon layer, the first polysilicon layer, and the gate dielectric layer to form a gate stack.

[0011] The second aspect of the present application provides a manufacturing method of a MOSFET, comprising the manufacturing method of a gate as described above and forming source / drain regions on both sides of the gate. BRIEF DESCRIPTION OF DRAWINGS

[0012] ​Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments with reference made to the accompanying drawings. The drawings are for purposes of illustration only and are not intended to be limiting in

[0013] Figure 1 A structure diagram of a gate in the prior art is shown;

[0014] Figure 2 A structure diagram of a gate in the embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0016] In the drawings, various structure diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale in that certain details are exaggerated for the purpose of clarity and can omit certain details. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary and can deviate in actuality due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0017] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element therebetween. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0018] The semiconductor substrate includes a memory device region for fabricating a flash memory device and a logic device region for forming a logic device, and the memory device region is formed with a gate structure of the flash memory device.

[0019] The logic device can be divided into an N-type logic device and a P-type logic device, and the N-type logic device or the P-type logic device or both the N-type logic device and the P-type logic device is fabricated in the logic device region. Among them, before the P-type polysilicon gate of the P-type logic device is formed, B ion implantation is needed to the polysilicon corresponding to the P-type logic device using BF3 plasma, but due to the etching characteristics of F, it will cause the polysilicon gate to be recessed, in order to solve the above problem, the following solutions are proposed in the embodiment.

[0020] The application will be described in detail below with reference to the accompanying drawings, taking the forming method of a MOSFET as an example.

[0021] Referring to Figure 2 First, a semiconductor substrate 10 is provided; specifically, the semiconductor substrate 10 can include any known silicon-based semiconductor material, including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrate. Alternatively, the semiconductor substrate 10 can include a silicon layer formed on a non-silicon-based semiconductor material, such as gallium arsenide, germanium, gallium nitride, or aluminum-phosphorus. In some embodiments, the semiconductor substrate 10 is a doped or undoped silicon substrate.

[0022] Next, a gate dielectric layer (not shown in the figure), an undoped first polysilicon layer 11, and a carbon-doped second polysilicon layer 12 are sequentially formed on the semiconductor substrate 10;

[0023] Specifically, the undoped first polysilicon layer 11 is formed on the semiconductor substrate 10 by, for example, a chemical vapor deposition fabrication process or a thermal oxidation fabrication process. In this embodiment, the first polysilicon layer 11 covers the semiconductor substrate 10. Then, the carbon-doped second polysilicon layer 12 is formed on the undoped first polysilicon layer 11 by, for example, a chemical vapor deposition fabrication process.

[0024] Generally, the deposition process includes exposing the semiconductor substrate 10 to a silicon source (such as silane, chlorosilane, or dichlorosilane) in a deposition chamber at a pressure of from about 50 mT to about 1000 mT for a period of from about 10 minutes to about 120 minutes, while maintaining the semiconductor substrate 10 at a temperature of from about 650°C to about 850°C.

[0025] An ion implantation fabrication process is performed on the carbon-doped first polysilicon layer 11 using NH3 gas to perform in-situ N ion implantation on the surface of the carbon-doped first polysilicon layer 11 to form a nitride protective layer 13 on the carbon-doped first polysilicon layer 11, using an electrostatic chuck capable of reaching a temperature of 500°C on a plasma doping device.

[0026] In-situ B ion implantation is performed on the carbon-doped second polysilicon layer 12 using BF3 or B2H6 gas to form a P-type polysilicon gate. The boron-doped ion implantation energy is 0.5 KeV to 10 KeV.

[0027] Next, a cap layer is formed on the second polysilicon layer 12, and then a gate mask pattern is formed on the cap layer, and the second polysilicon layer 12, the first polysilicon layer 11 and the gate dielectric layer are etched in a patterned manner to form a gate stack, with the gate mask pattern as a mask. Specifically, photoresist is applied on the cap layer, a gate mask pattern is formed on the cap layer according to the pattern of the gate stack to be formed, and then the gate stack is etched to form the gate stack with the gate mask pattern as a mask.

[0028] Next, source / drain implantation is performed on the semiconductor substrate 10 on both sides of the gate stack. Those skilled in the art can select the type of ions to be implanted according to the needs. For example, if an nMOS FFT is to be formed, As or P ions can be implanted, and if a pMOS FFT is to be formed, B or Ga ions can be implanted.

[0029] Compared with the prior art, the embodiment uses NH3 gas to perform in-situ plasma implantation on the surface of the carbon-doped first polysilicon layer 11 to form a nitride protective layer, thereby avoiding the recess of the second polysilicon layer 12 caused by BF3 or B2H6 gas during ion implantation, and improving the yield of the device.

[0030] The gate electrode in the embodiment can be applied to a volatile memory device such as a DRAM device, an SRAM device, or a non-volatile memory device such as a Flash device, a PRAM device, an MRAM device, and an RRAM device.

[0031] Further, a chip having the semiconductor device described above can be used in various electronic devices. Specifically, the electronic device can be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, a mobile power supply, etc.

[0032] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0033] The embodiments of the disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the disclosure, and all such substitutions and modifications shall fall within the scope of the disclosure.

Claims

1. A method of manufacturing a gate, characterized by, Comprising: providing a semiconductor substrate; forming a gate dielectric layer on the semiconductor substrate; forming an undoped first polysilicon layer, a carbon-doped second polysilicon layer on the semiconductor substrate in sequence; plasma treating the surface of the second polysilicon layer with nitride to form a nitride protective layer; wherein the nitride is selected from NH3; the temperature of in-situ plasma treating the surface of the second polysilicon layer with nitride is greater than 500℃; performing P-type ion implantation on the second polysilicon layer; wherein the P-type ion implantation is boron ion implantation; the boron ion implantation is performed on the second polysilicon layer with BF3 or B2H6; the boron ion implantation energy is 0.5KeV-10KeV; etching the second polysilicon layer, the first polysilicon layer and the gate dielectric layer to form a gate stack. The step of etching the second polysilicon layer, the first polysilicon layer and the gate dielectric layer to form a gate stack comprises:

2. The method for manufacturing a gate according to claim 1, characterized in that, forming a cap layer on the second polysilicon layer; forming a gate mask pattern on the cap layer; etching the cap layer, the second polysilicon layer, the first polysilicon layer and the gate dielectric layer with the gate mask pattern as a mask. A manufacturing method of the gate electrode as claimed in claim 1 or 2; 3. A method of manufacturing a MOSFET, characterized by, and forming source / drain regions on the substrate on both sides of the gate electrode. ​

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