Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region having a plurality of mutually separated first fins on the first region; forming a first gate structure on the first region; forming a dielectric layer on the substrate; removing the first gate structure and the portion of the first fins covered by the first gate structure by using an anisotropic etching process to form an isolation opening in the dielectric layer and in the first fins; and performing a cleaning process on the isolation opening to remove residues in the isolation opening. Since the anisotropic etching process is used, the problem of over-etching the dielectric layer and damaging other device structures during the removal of the first gate structure is reduced. In addition, after the isolation opening is formed, the cleaning process is performed on the isolation opening to remove residues in the isolation opening, so that the isolation structure subsequently formed in the isolation opening has a good filling effect, thereby improving the performance of the semiconductor structure finally formed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a forming method of a semiconductor structure. BACKGROUND

[0002] With the improvement of the integration of semiconductor devices, the critical dimension of the transistor is continuously reduced. However, with the sharp reduction of the transistor size, the difficulty of inhibiting the short channel effect is increased due to the unchangeable thickness of the gate dielectric layer and the working voltage, and the channel leakage current of the transistor is increased.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a fish fin. The channel of the FinFET protrudes from the substrate surface to form a fin, and the gate covers the top surface and the sidewall of the fin, so that the inversion layer is formed on each side of the channel, and the on and off of the circuit can be controlled on both sides of the fin. This design can increase the control of the gate on the channel region, thereby effectively inhibiting the short channel effect of the transistor. However, the Fin Field-Effect Transistor still has the short channel effect.

[0004] In addition, in order to further reduce the influence of the short channel effect on the semiconductor device and reduce the channel leakage current, the strained silicon technology is introduced in the technical field of semiconductor. The method of the strained silicon technology includes: forming a groove in the fin on both sides of the gate structure; and forming a source-drain doped layer in the groove by an epitaxial growth process.

[0005] In order to prevent the source-drain doped layers of different transistors from being connected to each other, it is necessary to form an isolation layer in the fin, and at the same time, in order to reduce the area of the isolation layer and improve the integration of the formed semiconductor structure, the SDB (Single Diffusion Break) technology is introduced in the prior art.

[0006] However, the semiconductor structure formed by the SDB technology introduced in the prior art has poor performance. SUMMARY

[0007] The technical problem solved by the present application is to provide a forming method of a semiconductor structure, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region, the first region having a plurality of mutually separated first fins; forming a first gate structure on the first region, the first gate structure crossing the first fins; forming a dielectric layer on the substrate, the dielectric layer covering the sidewall of the first gate structure; removing the first gate structure and the part of the first fins covered by the first gate structure by using an anisotropic etching process, forming an isolation opening in the dielectric layer and the first fins; performing a cleaning process on the isolation opening to remove residues in the isolation opening; and forming an isolation structure in the isolation opening after the cleaning process.

[0009] Optionally, the first gate structure comprises a gate dielectric layer, a work function layer metal layer on the gate dielectric layer, and a protective layer on the work function metal layer.

[0010] Optionally, the material of the gate dielectric layer comprises a high-K dielectric material.

[0011] Optionally, the material of the work function metal layer comprises tantalum nitride and titanium nitride.

[0012] Optionally, the material of the protective layer comprises silicon nitride.

[0013] Optionally, the method for removing the first gate structure and the part of the first fins covered by the first gate structure by using an anisotropic etching process comprises: removing the protective layer by using a first dry etching process; removing the work function metal layer and the gate dielectric layer by using a second dry etching process; and removing the part of the first fins covered by the first gate structure by using a third dry etching process.

[0014] Optionally, the parameters of the first dry etching process comprise: the etching gas comprises CF4, CHF3 and CH3F, wherein the gas flow rate of CF4 is 10-100 standard milliliter / minute, the gas flow rate of CHF3 is 50-120 standard milliliter / minute, and the gas flow rate of CH3F is 100-200 standard milliliter / minute; the pressure is 5-100 millitorr; and the bias voltage is 200-800 volts.

[0015] Optionally, the parameters of the second dry etching process include: the etching gas includes Cl2, BCl3, CF4, wherein the gas flow of Cl2 is 5-50 standard milliliter / minute, the gas flow of BCl3 is 100-500 standard milliliter / minute, the gas flow of CF4 is 10-100 standard milliliter / minute; the pressure is 5-200 millitorr; the bias voltage is 500-1000 volts.

[0016] Optionally, the parameters of the third dry etching process include: the etching gas includes HBr, wherein the gas flow of HBr is 10-200 standard milliliter / minute; the pressure is 5-200 millitorr; the bias voltage is 200-1000 volts.

[0017] Optionally, the material of the residue includes: tantalum nitride and titanium nitride.

[0018] Optionally, the cleaning process includes: a first cleaning process, and a second cleaning process after the first cleaning process.

[0019] Optionally, the process parameters of the first cleaning process include: the cleaning gas includes WCl5, Ar, H2, wherein Ar and H2 are carrier gases, the gas flow of WCl5 is 300-1000 standard milliliter / minute, the gas flow of Ar is 300-1000 standard milliliter / minute, the gas flow of H2 is 3-7 standard liter / minute; the cleaning temperature is 400-500 degrees Celsius; the pressure is 10-50 torr.

[0020] Optionally, the process parameters of the second cleaning process include: 20-30 degrees Celsius of HF, wherein the solution volume ratio of HF is 1:100-1:1000; 20-30 degrees Celsius of NH4OH, wherein the solution volume ratio of NH4OH is 1:1-1:100; the aqueous solution of HCl is sprayed in mist form under the action of N2.

[0021] Optionally, the forming method of the first gate structure includes: forming a first dummy gate structure on the first region, the first dummy gate structure straddling the first fin, and the dielectric layer covering the sidewall of the first dummy gate structure; removing the first dummy gate structure to form a first gate opening in the dielectric layer; and forming the first gate structure in the first gate opening.

[0022] Optionally, the substrate further includes a second region adjacent to the first region, and a plurality of mutually separate second fins are formed on the second region, and the second fins and the first fins are arranged in parallel.

[0023] Optionally, in the process of forming the first gate structure, further comprising: forming a second gate structure on the second region, the second gate structure crossing over the second fin.

[0024] Optionally, in the process of forming the first gate structure, further comprising: forming a plurality of third gate structures on the first region, the third gate structures crossing over the first fin, and the first gate structure being located between adjacent third gate structures.

[0025] Optionally, the forming method of the isolation structure comprises: forming an initial isolation structure in the isolation opening and on the dielectric layer; and performing a planarization treatment on the initial isolation structure until the top surface of the dielectric layer is exposed, to form the isolation structure.

[0026] Optionally, the forming process of the initial isolation structure comprises a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0027] Optionally, the planarization treatment process on the initial isolation structure comprises a chemical mechanical polishing process.

[0028] Optionally, the material of the isolation structure comprises silicon nitride.

[0029] Optionally, further comprising: forming an isolation layer on the substrate, the isolation layer covering part of the sidewall of the first fin, and the top surface of the isolation layer being lower than the top surface of the first fin.

[0030] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0031] In the forming method of the technical scheme of the present application, the anisotropic etching process is used to remove the first gate structure and part of the first fin covered by the first gate structure, to form an isolation opening in the dielectric layer. Since the anisotropic etching process is used, the problem of over-etching the dielectric layer and damaging other device structures during the removal of the first gate structure can be reduced. In addition, after the isolation opening is formed, a cleaning treatment is performed on the isolation opening to remove the residues in the isolation opening, so that the isolation structure formed in the isolation opening subsequently has a good filling effect, thereby improving the performance of the finally formed semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figures 1 to 3 is a schematic diagram of each step of a forming process of a semiconductor structure;

[0033] Figures 4 to 17is a structural schematic diagram of each step of a semiconductor structure forming method embodiment in the present application. DETAILED DESCRIPTION

[0034] As described in the background, the semiconductor structure formed by the SDB technology introduced by the prior art has poor performance. The following will be specifically described with reference to the drawings.

[0035] Figures 1 to 3 is a structural schematic diagram of each step of a semiconductor structure forming process.

[0036] Please refer to Figure 1 and Figure 2 , Figure 2 is Figure 1 The cross-sectional view along the A-A direction provides a substrate 100, which includes a first region I and a second region II arranged along a first direction X, the first region I has a plurality of first fins 101 arranged in parallel along the first direction X, and the second region II has a plurality of second fins 102 arranged in parallel along the first direction X; a first gate structure 103 is formed on the first region I, which spans the first fins 101 along the first direction X; a second gate structure 104 is formed on the second region II, which spans the second fins 102 along the first direction X; a dielectric layer 105 is formed on the substrate 100, which covers the sidewalls of the first gate structure 103 and the second gate structure 104.

[0037] Please refer to Figure 3 , Figure 3 and Figure 2 The view direction is consistent with that of the first gate structure 103 and the first fin 101 covered by the first gate structure 103, and a wet etching process is used to remove the first gate structure 103 and the first fin 101 covered by the first gate structure 103, forming an isolation opening in the dielectric layer 105; an isolation structure 106 is formed in the isolation opening.

[0038] In the present embodiment, the isolation structure 106 is an SDB structure, which is used to prevent the connection of source / drain doped layers of different types of transistor structures, and has an isolation effect. Moreover, the isolation structure 106 is formed by removing the first gate structure 103, so as to effectively reduce the area of isolation and improve the integration of the formed semiconductor structure.

[0039] However, the wet etching process is used to remove the first gate structure 103, and since the wet etching process has the characteristic of isotropy, the etching solution is prone to over-etching in the process of removing the first gate structure 103, thereby causing damage to the second gate structure 104 (such asFigure 3 The performance of the finally formed semiconductor structure is reduced.

[0040] On this basis, the application provides a semiconductor structure forming method. Anisotropic etching is used to remove the first gate structure and part of the first fin covered by the first gate structure, so as to form an isolation opening in the dielectric layer. Since the anisotropic etching is used, the problem of over-etching the dielectric layer and damaging other device structures during the removal of the first gate structure is reduced. In addition, after the isolation opening is formed, the isolation opening is cleaned to remove residues in the isolation opening, so that the isolation structure formed in the isolation opening has a good filling effect, thereby improving the performance of the finally formed semiconductor structure.

[0041] In order to make the above objectives, characteristics and advantages of the application more obvious and easy to understand, specific embodiments of the application will be described in detail below with reference to the drawings.

[0042] Figures 4 to 17 is a structural schematic diagram of a semiconductor structure forming process according to an embodiment of the application.

[0043] Please refer to Figure 4 and Figure 5 , Figure 5 is Figure 4 is a schematic diagram of a cross section along direction B-B in

[0044] In the embodiment, the substrate 200 further includes a second region II adjacent to the first region I, and the second region II has a plurality of mutually separated second fins 202, and the second fins 202 and the first fins 201 are arranged in parallel.

[0045] In the embodiment, a forming method of the substrate 200, the first fins 201 and the second fins 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, and the patterned layer exposes part of the top surface of the initial substrate; and etching the initial substrate with the patterned layer as a mask to form the substrate 200, the first fins 201 and the second fins 202.

[0046] In the embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0047] In this embodiment, the material of the first fin 201 is silicon; in other embodiments, the material of the first fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0048] In this embodiment, the material of the second fin 202 is silicon; in other embodiments, the material of the second fin can also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0049] Please refer to Figure 6 , Figure 6 and Figure 5 , the isolation layer 203 is formed on the substrate 200, the isolation layer 203 covers part of the sidewall of the first fin 201, and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201.

[0050] In this embodiment, the isolation layer 203 also covers part of the sidewall of the second fin 202, and the top surface of the isolation layer 203 is lower than the top surface of the second fin 202.

[0051] In this embodiment, the forming method of the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching to remove part of the initial isolation layer to form the isolation layer 203, and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201.

[0052] The material of the isolation layer 203 is an insulating material, which includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 203 is silicon oxide.

[0053] In this embodiment, after the isolation layer 203 is formed, it further includes: forming a first gate structure on the first region I, the first gate structure is across the first fin 201; forming a second gate structure on the second region II, the second gate structure is across the second fin 202; forming a plurality of third gate structures on the first region I, the third gate structure is across the first fin 201, and the first gate structure is located between adjacent third gate structures; forming a dielectric layer on the substrate 200, the dielectric layer covers the sidewall of the first gate structure. For specific forming process, please refer to Figures 7 to 12 .

[0054] Please refer to Figure 7 and Figure 8 , Figure 8 is Figure 7 , a first dummy gate structure 204 is formed on the first region I, and the first dummy gate structure 204 is across the first fin 201.

[0055] In the embodiment, in the process of forming the first dummy gate structure 204, further comprising: forming a second dummy gate structure 205 on the second region II, the second dummy gate structure 205 spanning over the second fin 202; forming a plurality of third dummy gate structures 206 on the first region I, the third dummy gate structures 206 spanning over the first fin 201, and the first dummy gate structure 204 being located between adjacent third dummy gate structures 206.

[0056] In the embodiment, the first dummy gate structure 204 comprises: a dummy gate dielectric layer, and a dummy gate layer (not shown) on the dummy gate dielectric layer.

[0057] In the embodiment, the material of the dummy gate dielectric layer comprises a high-K dielectric material.

[0058] The material of the dummy gate layer comprises polysilicon or amorphous silicon. In the embodiment, the material of the dummy gate layer is polysilicon.

[0059] Please continue to refer to Figure 7 and Figure 8 , after forming the first dummy gate structure 204, forming a sidewall 207 on the substrate 200, the sidewall 207 being located on the sidewall of the first dummy gate structure 204.

[0060] In the embodiment, the sidewall of the second dummy gate structure 205 and the second dummy gate structure 206 is also formed with the sidewall 207.

[0061] The material of the sidewall 207 comprises one or more combinations of silicon nitride, silicon oxide and silicon oxynitride. In the embodiment, the material of the sidewall 207 is silicon nitride.

[0062] Please refer to Figure 9 , Figure 9 and Figure 7 , the view direction is consistent, forming a first source-drain doped layer 208 in the first fin 201.

[0063] In the embodiment, in the process of forming the first source-drain doped layer 208, further comprising: forming a second source-drain doped layer 209 in the second fin 202.

[0064] In the embodiment, the forming method of the first source-drain doped layer 208 includes: etching the first fin 201 as a mask with the first dummy gate structure 204, the third dummy gate structure 206 and the sidewall 207, forming a first source-drain opening (not shown) in the first fin 201; forming a first epitaxial layer (not shown) in the first source-drain opening by an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth, incorporating source-drain ions in the epitaxial layer to form the first source-drain doped layer 208.

[0065] In the embodiment, the forming method of the second source-drain doped layer 209 includes: etching the second fin 202 as a mask with the second dummy gate structure 205 and the sidewall 207, forming a second source-drain opening (not shown) in the second fin 202; forming a second epitaxial layer (not shown) in the second source-drain opening by an epitaxial growth process; in-situ doping the second epitaxial layer during the epitaxial growth, incorporating source-drain ions in the epitaxial layer to form the second source-drain doped layer 209.

[0066] Please refer to the same view direction of Figure 10 , Figure 10 and Figure 8 , a dielectric layer 210 is formed on the substrate 200, and the dielectric layer 210 covers the sidewall of the first dummy gate structure 204.

[0067] In the embodiment, the dielectric layer 210 also covers the sidewall of the second dummy gate structure 205 and the third dummy gate structure 206.

[0068] In the embodiment, the material of the dielectric layer 210 is silicon oxide; in other embodiments, the material of the dielectric layer can also be low-K dielectric material (low-K dielectric material refers to dielectric material with relative dielectric constant lower than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with relative dielectric constant lower than 2.5).

[0069] Please refer to the same view direction of Figure 11 and Figure 12 , Figure 12 is Figure 11 , after forming the dielectric layer 210, the first dummy gate structure 204 is removed, forming a first gate opening (not shown) in the dielectric layer 210; the first gate structure 211 is formed in the first gate opening.

[0070] In the embodiment, in the process of forming the first gate structure 211, further comprising: removing the second dummy gate structure 205, forming a second gate opening (not shown) in the dielectric layer 210; removing the third dummy gate structure 206, forming a third gate opening (not shown) in the dielectric layer 210; forming the second gate structure 212 in the second gate opening; forming the third gate structure 213 in the third gate opening.

[0071] In the embodiment, the first gate structure 211 comprises: a gate dielectric layer, a work function metal layer on the gate dielectric layer, and a protective layer (not shown) on the work function metal layer.

[0072] In the embodiment, the material of the gate dielectric layer comprises high-K dielectric material.

[0073] In the embodiment, the material of the work function metal layer comprises tantalum nitride and titanium nitride.

[0074] In the embodiment, the material of the protective layer comprises silicon nitride.

[0075] Please refer to Figures 13 to 15 , Figure 14 is Figure 13 is a schematic view of the cross section along the direction E in the embodiment, and the anisotropic etching process is used to remove the first gate structure 211 and the part of the first fin 201 covered by the first gate structure 211, forming an isolation opening 214 in the dielectric layer 210 and the first fin 201. Figure 15 Figure 13 is a schematic view of the cross section along the direction F in the embodiment, and the anisotropic etching process is used to remove the first gate structure 211 and the part of the first fin 201 covered by the first gate structure 211, forming an isolation opening 214 in the dielectric layer 210.

[0076] The anisotropic etching process is used to remove the first gate structure 211 and the part of the first fin 201 covered by the first gate structure 211, forming an isolation opening 214 in the dielectric layer 210. Since the anisotropic etching process is used, the problem of over-etching the dielectric layer 210 and damaging other device structures can be reduced in the process of removing the first gate structure 211.

[0077] In the embodiment, the method of removing the first gate structure 211 and the part of the first fin 201 covered by the first gate structure 211 by using the anisotropic etching process comprises: removing the protective layer by using a first dry etching process; removing the work function metal layer and the gate dielectric layer by using a second dry etching process; removing the part of the first fin 201 covered by the first gate structure 211 by using a third dry etching process.

[0078] ​In the embodiment, the parameters of the first dry etching process include: the etching gas includes CF4, CHF3 and CH3F, the gas flow of CF4 is 10-100 standard milliliter per minute, the gas flow of CHF3 is 50-120 standard milliliter per minute, the gas flow of CH3F is 100-200 standard milliliter per minute; the pressure is 5-100 millitorr; the bias voltage is 200-800 volts.

[0079] In the embodiment, the parameters of the second dry etching process include: the etching gas includes Cl2, BCl3 and CF4, the gas flow of Cl2 is 5-50 standard milliliter per minute, the gas flow of BCl3 is 100-500 standard milliliter per minute, the gas flow of CF4 is 10-100 standard milliliter per minute; the pressure is 5-200 millitorr; the bias voltage is 500-1000 volts.

[0080] In the embodiment, the parameters of the third dry etching process include: the etching gas includes HBr, the gas flow of HBr is 10-200 standard milliliter per minute; the pressure is 5-200 millitorr; the bias voltage is 200-1000 volts.

[0081] Please refer to the same view direction of Figure 16 , Figure 16 and Figure 15 , the isolation port 214 is cleaned to remove the residues in the isolation port 214.

[0082] In the embodiment, since the sidewall of the first gate structure 211 is not absolutely vertical, in the process of removing the first gate structure 211, the recessed sidewall of the first gate structure 211 is not easy to be removed, thereby forming the residues.

[0083] In the embodiment, the material of the residues includes: tantalum nitride and titanium nitride.

[0084] In the embodiment, the cleaning process includes: a first cleaning process, and a second cleaning process after the first cleaning process.

[0085] The process parameters for the first cleaning treatment include: the cleaning gas consists of WCl5, Ar, and H2, with Ar and H2 serving as carrier gases; the gas flow rate of WCl5 is 300 standard milliliters / minute to 1000 standard milliliters / minute; the gas flow rate of Ar is 300 standard milliliters / minute to 1000 standard milliliters / minute; and the gas flow rate of H2 is 3 standard liters / minute to 7 standard liters / minute; the cleaning temperature is 400 degrees Celsius to 500 degrees Celsius; and the pressure is 10 Torr to 50 Torr.

[0086] Since the residues are mainly concentrated at the corners, the first cleaning process is isotropic and can remove most of the tantalum nitride and titanium nitride residues.

[0087] The process parameters for the second cleaning treatment include: HF at 20°C to 30°C, wherein the volume ratio of HF solution is 1:100 to 1:1000; NH4OH at 20°C to 30°C, wherein the volume ratio of NH4OH solution is 1:1 to 1:1:00; and an aqueous solution mixed with HCl, which is sprayed out in a mist form under the action of N2.

[0088] Since the first cleaning process includes WCl5 cleaning gas, a small amount of metallic tungsten (W) remains after the first cleaning process. Therefore, the metallic tungsten is removed by the aqueous solution containing HCl in the second cleaning process. The aqueous solution containing HCl is sprayed out in a mist under the action of N2, which has a certain impact force and can make the cleaning more thorough.

[0089] By removing the residue inside the isolation opening 214, the isolation structure subsequently formed inside the isolation opening 214 has a better filling effect, thereby improving the performance of the final semiconductor structure.

[0090] Please refer to Figure 17 After the cleaning process, an isolation structure 215 is formed within the isolation opening 214.

[0091] In this embodiment, the isolation structure 215 is an SDB structure. This isolation structure 215 is used to prevent the source and drain doped layers of different types of transistor structures from interconnecting, thus achieving an isolation effect. Furthermore, the isolation structure 215 is formed by removing the first gate structure 211. This effectively reduces the isolation area and improves the integration density of the formed semiconductor structure.

[0092] In the embodiment, the forming method of the isolation structure 215 includes: forming an initial isolation structure (not shown) in the isolation opening 214 and on the dielectric layer 210; and performing a planarization process on the initial isolation structure until the top surface of the dielectric layer 210 is exposed, thereby forming the isolation structure 215.

[0093] The forming process of the initial isolation structure includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. In the embodiment, the forming process of the initial isolation structure adopts an atomic layer deposition process.

[0094] In the embodiment, the planarization process on the initial isolation structure adopts a chemical mechanical polishing process.

[0095] In the embodiment, the material of the isolation structure 215 adopts silicon oxide.

[0096] Although the present application has been disclosed with reference to the above embodiments, it is not intended to limit the present application to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region adjacent to the first region, the first region having a plurality of mutually discrete first fins, the second region having a plurality of mutually discrete second fins, the second fins and the first fins being arranged in parallel. A first gate structure is formed on the first region and a second gate structure is formed on the second region, the first gate structure spanning the first fin and the second gate structure spanning the second fin; A dielectric layer is formed on the substrate, the dielectric layer covering the sidewalls of the first gate structure; An anisotropic etching process is used to remove the first gate structure and the portion of the first fin covered by the first gate structure, forming an isolation opening in the dielectric layer and in the first fin; The isolation opening is cleaned to remove any residue inside. After the cleaning process, an isolation structure is formed within the isolation opening; the isolation structure is an SDB structure. The cleaning process includes: a first cleaning process, and a second cleaning process following the first cleaning process; The first cleaning process is isotropic to remove residues at corners; The aqueous solution of the second cleaning treatment is mixed with HCl, and the aqueous solution mixed with HCl is sprayed out in a mist with impact force under the action of N2.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first gate structure includes: a gate dielectric layer, a work function metal layer located on the gate dielectric layer, and a protective layer located on the work function metal layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the gate dielectric layer includes a high-K dielectric material.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The materials of the work function metal layer include tantalum nitride and titanium nitride.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the protective layer includes silicon nitride.

6. The method for forming a semiconductor structure as described in claim 2, characterized in that, A method for removing the first gate structure and the portion of the first fin covered by the first gate structure using an anisotropic etching process includes: removing the protective layer using a first dry etching process; removing the work function metal layer and the gate dielectric layer using a second dry etching process; and removing the portion of the first fin covered by the first gate structure using a third dry etching process.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The parameters of the first dry etching process include: etching gases including CF4, CHF3, and CH3F, wherein the gas flow rate of CF4 is 10 standard ml / min to 100 standard ml / min, the gas flow rate of CHF3 is 50 standard ml / min to 120 standard ml / min, and the gas flow rate of CH3F is 100 standard ml / min to 200 standard ml / min; the pressure is 5 mTorr to 100 mTorr; and the bias voltage is 200 volts to 800 volt-amperes.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The parameters of the second dry etching process include: etching gases including Cl2, BCl3, and CF4, wherein the gas flow rate of Cl2 is 5 standard ml / min to 50 standard ml / min, the gas flow rate of BCl3 is 100 standard ml / min to 500 standard ml / min, and the gas flow rate of CF4 is 10 standard ml / min to 100 standard ml / min; the pressure is 5 mTorr to 200 mTorr; and the bias voltage is 500 volts to 1000 volts.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The parameters of the third dry etching process include: the etching gas includes HBr, wherein the gas flow rate of HBr is 10 standard ml / min to 200 standard ml / min; the pressure is 5 mTorr to 200 mTorr; and the bias voltage is 200 volts to 1000 volts.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the residue include tantalum nitride and titanium nitride.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters for the first cleaning treatment include: the cleaning gas consists of WCl5, Ar, and H2, with Ar and H2 serving as carrier gases; the gas flow rate of WCl5 is 300 standard milliliters / minute to 1000 standard milliliters / minute; the gas flow rate of Ar is 300 standard milliliters / minute to 1000 standard milliliters / minute; and the gas flow rate of H2 is 3 standard liters / minute to 7 standard liters / minute; the cleaning temperature is 400 degrees Celsius to 500 degrees Celsius; and the pressure is 10 Torr to 50 Torr.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters for the second cleaning treatment include: HF at 20°C to 30°C, wherein the volume ratio of HF solution is 1:100 to 1:1000; NH4OH at 20°C to 30°C, wherein the volume ratio of NH4OH solution is 1:1 to 1:100; and an aqueous solution mixed with HCl, which is sprayed out in a mist form under the action of N2.

13. The method for forming a semiconductor structure as described in claim 2, characterized in that, The method of forming the first gate structure includes: forming a first dummy gate structure on the first region, the first dummy gate structure spanning the first fin, the dielectric layer covering the sidewall of the first dummy gate structure; removing the first dummy gate structure and forming a first gate opening in the dielectric layer; and forming the first gate structure in the first gate opening.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of forming the first gate structure further includes: forming a plurality of third gate structures on the first region, the third gate structures spanning across the first fin, and the first gate structure being located between adjacent third gate structures.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the isolation structure includes: forming an initial isolation structure inside the isolation opening and on the dielectric layer; and planarizing the initial isolation structure until the top surface of the dielectric layer is exposed, thereby forming the isolation structure.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The formation process of the initial isolation structure includes: chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process for planarizing the initial isolation structure includes chemical mechanical polishing.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the isolation structure includes silicon nitride.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: An isolation layer is formed on the substrate, the isolation layer covering a portion of the sidewall of the first fin, and the top surface of the isolation layer being lower than the top surface of the first fin.

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