Semiconductor structure and its formation method

Abstract

This application provides a semiconductor structure and a method for forming the same. The method includes: providing a substrate and a dielectric layer on the substrate, the dielectric layer including a first portion and a second portion with coplanar top surfaces; forming a first sacrificial layer on the surface of the first portion of the dielectric layer; forming a second sacrificial layer on the surface and sidewalls of the first sacrificial layer and on the surface of the second portion of the dielectric layer; forming a resistive layer on the surface of the second sacrificial layer; and etching the resistive layer, the second sacrificial layer, and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the surface of the second portion of the dielectric layer. The semiconductor structure formation method of this application can effectively reduce the stripping phenomenon of the resistive layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Compared to traditional photonics technology, silicon photonic devices have advantages such as lower cost, higher integration, more embedded co-energy, higher interconnect density and lower power consumption. For example, silicon photonic titanium nitride heaters have been widely studied due to their excellent performance.

[0003] However, during the fabrication of silicon phototitanium nitride heaters, titanium nitride (TIN) peeling often occurs, resulting in defective devices and affecting device yield. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a semiconductor structure and a method for forming the same, so as to effectively reduce the stripping of the resistive layer.

[0005] To address the aforementioned technical problems, this application provides a method for forming a semiconductor structure, comprising: providing a substrate and a dielectric layer on the substrate, the dielectric layer including a first portion and a second portion with coplanar top surfaces; forming a first sacrificial layer on the surface of the first portion of the dielectric layer; forming a second sacrificial layer on the surface and sidewalls of the first sacrificial layer and on the surface of the second portion of the dielectric layer; forming a resistive layer on the surface of the second sacrificial layer; and etching the resistive layer, the second sacrificial layer, and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the surface of the second portion of the dielectric layer.

[0006] In this embodiment of the application, a conductive layer is formed between the first portion of the dielectric layer and the substrate.

[0007] In this embodiment, the first sacrificial layer sequentially includes an isolation layer and an auxiliary isolation layer located on a first portion of the surface of the dielectric layer.

[0008] In this embodiment, the material of the isolation layer includes amorphous carbon, and the material of the auxiliary isolation layer includes silicon oxide.

[0009] In this embodiment, the process of forming the first sacrificial layer includes: sequentially forming an isolation material layer and an auxiliary isolation material layer on the surface of the dielectric layer; forming a first photoresist layer, wherein the first photoresist layer covers the surface of the auxiliary isolation material layer above a first portion of the dielectric layer; and using the first photoresist layer as a mask, etching the auxiliary isolation material layer and the isolation material layer to form the first sacrificial layer.

[0010] In this embodiment, the first photoresist layer includes a first antireflective layer and a first photoresist layer located on the surface of the first antireflective layer.

[0011] In this embodiment of the application, the process of forming the first sacrificial layer further includes: removing the first photoresist layer; removing the first antireflective layer and a portion of the second portion of the dielectric layer, such that the top surface of the second portion of the dielectric layer is lower than the surface of the first portion of the dielectric layer.

[0012] In this embodiment, the top surface of the second sacrificial layer located on the second portion of the dielectric layer is coplanar with the surface of the first portion of the dielectric layer.

[0013] In this embodiment, the material of the second sacrificial layer includes silicon oxide.

[0014] In this embodiment, the material of the resistive layer includes at least one of elemental metals and metal nitrides.

[0015] In this embodiment, the process of etching the resistive layer, the second sacrificial layer, and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the second portion surface of the dielectric layer, includes: forming a second photoresist layer, the second photoresist layer covering the surface of the resistive layer above the second portion of the dielectric layer; and using the second photoresist layer as a mask to etch the resistive layer, the second sacrificial layer, and the first sacrificial layer.

[0016] In this embodiment, the second photoresist layer sequentially includes a photoresist isolation layer, a second anti-reflection layer, and a second photoresist layer located on the surface of the resistive layer above the second portion of the dielectric layer.

[0017] In this embodiment, the material of the photoresist isolation layer includes silicon oxide.

[0018] In this embodiment, the process of forming the second photoresist layer includes: forming a photoresist isolation material layer on the surface of the resistive layer; forming a second antireflective material layer on the surface of the photoresist isolation material layer, wherein the top surfaces of the second antireflective material layer above the first portion of the dielectric layer and above the second portion of the dielectric layer are coplanar; forming a second photoresist material layer on the surface of the second antireflective material layer; and etching the second photoresist material layer, the second antireflective material layer, and the photoresist isolation material layer above the first portion of the dielectric layer.

[0019] In this embodiment of the application, the process of etching the resistive layer, the second sacrificial layer and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the second part of the surface of the dielectric layer, further includes: removing the second photoresist layer and the second anti-reflective layer.

[0020] To address the aforementioned technical problems, this application also provides a semiconductor structure, comprising: a substrate; a dielectric layer located on the substrate, comprising a first portion and a second portion that are coplanar; a first sacrificial layer located on the surface of the first portion of the dielectric layer; a second sacrificial layer located on the surface and sidewalls of the first sacrificial layer and on the surface of the second portion of the dielectric layer; and a resistive layer located on the surface of the second sacrificial layer.

[0021] In this embodiment, the top surface of the second sacrificial layer located on the second portion of the dielectric layer is coplanar with the surface of the first portion of the dielectric layer.

[0022] In this embodiment, the first sacrificial layer sequentially includes an isolation layer and an auxiliary isolation layer located on a first portion of the surface of the dielectric layer.

[0023] In this embodiment, the material of the isolation layer includes amorphous carbon, and the material of the auxiliary isolation layer includes silicon oxide.

[0024] In this embodiment, the materials of the dielectric layer and the second sacrificial layer include silicon oxide.

[0025] In this embodiment, the material of the resistive layer includes at least one of elemental metals and metal compounds.

[0026] The semiconductor structure and its formation method of this application form a first sacrificial layer on a portion of the surface of the dielectric layer before forming the resistive layer. Then, a second sacrificial layer is formed on the surface and sidewalls of the first sacrificial layer and the remaining surface of the dielectric layer. Finally, a resistive layer is formed on the surface of the second sacrificial layer. This effectively isolates most of the resistive layer from the dielectric layer, thus solving the problem of resistive layer peeling and significantly improving product yield. Attached Figure Description

[0027] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0028] Figures 1 to 3 This is a schematic diagram of the formation process of a silicon phototitanium nitride heater;

[0029] Figures 4 to 11 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application;

[0030] Figure 12Test diagram of the radius of curvature of the semiconductor structure surface fabricated by the formation method of this application embodiment and conventional formation method. Detailed Implementation

[0031] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0032] Traditional processes for manufacturing silicon phototitanium nitride heaters are prone to titanium nitride peeling, resulting in defective devices and low yield.

[0033] Specifically, Figures 1 to 3 The formation process of a silicon phototitanium nitride heater is shown.

[0034] Reference Figure 1 First, a semiconductor substrate 10 is provided, in which various devices can be formed. A dielectric layer 20 is deposited on the surface of the semiconductor substrate 10. The dielectric layer 20 is made of silicon oxide. Then, a titanium nitride layer 30 is deposited on the surface of the dielectric layer 20. The titanium nitride layer 30 provides the required resistance for the heater. Then, a bottom anti-reflective layer 40 and a photoresist 50 are sequentially formed on the surface of the titanium nitride layer 30.

[0035] During the deposition of the titanium nitride layer 30, the large difference in the coefficient of thermal expansion between the titanium nitride material in the titanium nitride layer 30 and the silicon oxide material in the dielectric layer 20 causes a stress mismatch between the two, resulting in the titanium nitride layer 30 not adhering well to the surface of the dielectric layer 20 and being prone to peeling. Therefore, the formed titanium nitride layer 30 often has significant defects.

[0036] Combination Figure 2 and Figure 3 The photoresist layer 50 is patterned with a titanium nitride heater using an exposure and development technique. Then, using the photoresist 50 as a mask, the bottom anti-reflective layer 40 and the titanium nitride layer 30 are etched. Finally, the photoresist 50 is removed to form a silicon photoresist titanium nitride heater. However, significant defects in the titanium nitride layer 30 greatly affect the performance of the formed silicon photoresist titanium nitride heater, potentially leading to device failure in severe cases.

[0037] Based on the above-mentioned technical problems, the present application provides a semiconductor structure and its formation method. Before forming the resistive layer, a first sacrificial layer is first formed on a portion of the surface of the dielectric layer. Then, a second sacrificial layer is formed on the surface and sidewalls of the first sacrificial layer and the remaining surface of the dielectric layer. Finally, a resistive layer is formed on the surface of the second sacrificial layer. Since there are first and second sacrificial layers between most of the resistive layer and the dielectric layer, the peeling phenomenon of the resistive layer can be effectively alleviated, and the yield of the device can be greatly improved.

[0038] The technical solution of this application will be described in detail below with reference to the accompanying drawings, taking the formation method of the silicon phototitanium nitride heater as an example.

[0039] Figures 4 to 11 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure formation method in the embodiments of this application.

[0040] Please refer to Figure 4 A substrate 100 is provided, and the material of the substrate 100 may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. It may also include a multilayer structure composed of the aforementioned materials, or be silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), etc. In the embodiments of this application, the substrate 100 is composed of single-crystal silicon or silicon-on-insulator.

[0041] A dielectric layer 200 is formed on the substrate 100, and the dielectric layer 200 includes a first portion and a second portion with coplanar top surfaces. It should be understood that in actual processes, the first portion and the second portion of the dielectric layer 200 can be formed as a single unit in the same deposition process. In this embodiment, the dielectric layer 200 is artificially divided into two portions for ease of description in order to clearly illustrate the positional relationships between the structures. Of course, in other embodiments, the first portion and the second portion of the dielectric layer 200 can also be formed in different processes.

[0042] The formation process of the dielectric layer 200 may include: depositing a dielectric material on the surfaces of the conductive layer 110 and the remaining substrate 100 using a chemical vapor deposition process; and grinding the dielectric material to a certain height using chemical mechanical polishing or physical mechanical polishing, so that the dielectric material on the surfaces of the conductive layer 110 and the remaining substrate 100 is at the same horizontal plane or substantially at the same horizontal plane, thereby forming the dielectric layer 200. The thickness of the dielectric layer 200 is determined according to the actual situation, and the material of the dielectric layer 200 includes silicon oxide.

[0043] In some embodiments, a conductive layer 110 is formed between a first portion of the dielectric layer 200 and the substrate 100. That is, the conductive layer 110 is located on a portion of the surface of the substrate 100, and the dielectric layer 200 is located on the conductive layer 110 and the remaining surfaces of the substrate 100. The size of the conductive layer 110 is designed according to actual conditions. In this embodiment, the width of the conductive layer 110 is smaller than the width of the first portion of the dielectric layer 200. The material of the conductive layer 110 may include metals, such as aluminum, copper, tungsten, etc., or other conductive materials.

[0044] Continue to refer to Figure 4 A first sacrificial layer 300 is formed on the surface of a first portion of the dielectric layer 200. The first sacrificial layer 300 can be a single-layer structure or a multilayer structure. For example, the first sacrificial layer 300 includes an isolation layer 310, which can isolate most of the resistive layer formed in subsequent processes from the first portion of the dielectric layer 200 formed above, thereby maximally mitigating the problem of resistive layer peeling caused by stress mismatch between the resistive layer and the dielectric layer 200. In this embodiment, the first sacrificial layer 300 is a stacked structure, including an isolation layer 310 and an auxiliary isolation layer 320. The isolation layer 310 is located on the surface of the first portion of the dielectric layer 200, and the auxiliary isolation layer 320 is located on the surface of the isolation layer 310. Since the isolation layer 310 and the auxiliary isolation layer 320 will be removed in subsequent processes, they are collectively referred to as the first sacrificial layer 300. However, in actual semiconductor structures, the isolation layer 310 and the auxiliary isolation layer 320 play different roles. The isolation layer 310 mainly isolates most of the resistive layer from the first portion of the dielectric layer, thereby maximally mitigating or even completely eliminating the stripping phenomenon of the resistive layer. The auxiliary isolation layer 320 can not only play the same role as the isolation layer 310, but also isolate the anti-reflective layer (DARC) formed in subsequent processes from the isolation layer 310. For details, please refer to the description of subsequent processes.

[0045] The formation process of the first sacrificial layer 300 may include: sequentially forming an isolation material layer and an auxiliary isolation material layer on the surface of the dielectric layer 200, wherein the formation process of the isolation material layer and the auxiliary isolation material layer may be a common deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition; forming a first photoresist layer on the surface of the auxiliary isolation material layer above the first portion of the dielectric layer 200, wherein the first photoresist layer may be a single-layer structure, for example, it may include a first photoresist layer, or, as in the embodiments of this application, the first photoresist layer includes a first anti-reflection layer 410 and a first photoresist layer (not shown) located on the surface of the first anti-reflection layer 410. The first anti-reflection layer 410 can reduce or eliminate the reflection of incident light and improve the exposure and development effect. It should be noted that the aforementioned auxiliary isolation layer 320 can prevent the first anti-reflection layer 410 and the isolation layer 310 from directly contacting each other, buffer the stress between the first anti-reflection layer 410 and the isolation layer 310, make the formed first anti-reflection layer 410 more uniform, and achieve the best effect in eliminating the reflection of incident light. Next, using the first photoresist layer as a mask, the auxiliary isolation material layer and the isolation material layer are etched to form the first sacrificial layer 300. In this embodiment, the auxiliary isolation material layer and the isolation material layer can be etched using a dry etching process.

[0046] The first sacrificial layer 300 needs to function as both an isolation layer and a dielectric layer, and also needs to be easily removed in subsequent processes. This places stringent requirements on the material selection for the first sacrificial layer 300. In this embodiment, amorphous carbon (APF) is used as the material for the isolation layer 310, and silicon oxide is used as the material for the auxiliary isolation layer 320, which fully meets the performance requirements for the first sacrificial layer 300. The material of the first antireflective layer 410 needs to have good reflective properties; in this embodiment, silicon oxynitride is used as the first antireflective layer 410.

[0047] In some embodiments, the thickness of the isolation layer 310 is 500 angstroms to 2000 angstroms, the thickness of the auxiliary isolation layer 320 is 20 angstroms to 100 angstroms, and the thickness of the first antireflective layer 410 is 200 angstroms to 600 angstroms. The sum of the widths of the first sacrificial layer 300 and the subsequently formed resistive layer is substantially equal to the width of the dielectric layer 200. "Substantially equal to" means that a very thin film layer (i.e., the subsequently formed "second sacrificial layer 500") exists between the first sacrificial layer 300 and the resistive layer. Therefore, the width of the first sacrificial layer 300 is closely related to the width of the resistive layer to be formed. The larger the width of the resistive layer, the smaller the width of the first sacrificial layer 300 needs to be designed; conversely, the smaller the width of the resistive layer, the larger the width of the first sacrificial layer 300. The specific design depends on the actual situation.

[0048] The process of forming the first sacrificial layer 300 further includes: removing the first photoresist layer, which can be done by a conventional ozone oxidation process.

[0049] refer to Figure 5 Next, the first anti-reflective layer 410 is removed. In this embodiment, a blank etching method is used to remove the first anti-reflective layer 410, meaning the first anti-reflective layer 410 is etched without any mask obstruction, thus eliminating the need for mask formation and removal steps. Since the second portion of the dielectric layer 200 has no obstructing structures, a portion of the second portion of the dielectric layer 200 is also etched simultaneously with the first anti-reflective layer 410, resulting in the top surface of the second portion of the dielectric layer 200 being lower than the surface of the first portion. The etching process for the first anti-reflective layer 410 and a portion of the second portion of the dielectric layer 200 can be a dry etching process.

[0050] refer to Figure 6 In other embodiments, a sacrificial layer, such as a mask layer, can be formed on the surface of the second portion of the dielectric layer 200 before removing the first antireflective layer 410. In this case, the sacrificial layer on the surface of the second portion of the dielectric layer 200 can be etched away at the same time as the first antireflective layer 410, thereby protecting the second portion of the dielectric layer 200 from loss. That is, after removing the first antireflective layer 410, the top surface of the second portion of the dielectric layer 200 is still coplanar with the surface of the first portion of the dielectric layer 200.

[0051] The following description uses the example of the top surface of the second part of the dielectric layer 200 being lower than the surface of the first part of the dielectric layer 200.

[0052] refer to Figure 7A second sacrificial layer 500 is formed on the surface and sidewalls of the first sacrificial layer 300 and on the second portion of the dielectric layer 200. The process for forming the second sacrificial layer 500 can be chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other conventional deposition methods. The second sacrificial layer 500 can, on the one hand, fill the position of the second portion of the dielectric layer 200 lost in the aforementioned process, making the top surface of the second sacrificial layer 500 on the surface of the second portion of the dielectric layer 200 coplanar with the surface of the first portion of the dielectric layer 200; on the other hand, since there is also a stress mismatch between the isolation layer 310 and the resistive layer formed in subsequent processes, the second sacrificial layer 500 can prevent the sidewalls of the isolation layer 310 from directly contacting the resistive layer, which is beneficial for the formation of the resistive layer; furthermore, the second sacrificial layer 500 and the auxiliary isolation layer 320 together serve to prevent direct contact between the surfaces of the resistive layer and the isolation layer 310. The thickness of the second sacrificial layer 500 is preferably such that it precisely fills the position of the second portion of the dielectric layer 200 lost in the aforementioned process. In this embodiment, the thickness of the second sacrificial layer 500 is 20 angstroms to 100 angstroms. The material of the second sacrificial layer 500 can be the same as the material of the auxiliary isolation layer 320 and the dielectric layer 200. In some embodiments, the material of the second sacrificial layer 500 includes silicon oxide.

[0053] refer to Figure 8 A resistive layer 600 is formed on the surface of the second sacrificial layer 500. The resistive layer 600 provides resistance for the silicon photoelectric titanium nitride heater; therefore, the material of the resistive layer 600 needs to meet the resistance value requirements of the silicon photoelectric titanium nitride heater. In this embodiment, the resistive layer 600 comprises titanium nitride. In other embodiments, the semiconductor structure can be other types of silicon photoelectric heaters; therefore, the material of the resistive layer 600 can be other materials that can provide resistance, such as copper, aluminum, tungsten, and at least one of some metal nitride compounds. The thickness of the resistive layer 600 is closely related to the required resistance value. For the same material, the greater the thickness of the resistive layer 600, the smaller the resistance value provided by the resistive layer 600. In this embodiment, the thickness of the resistive layer 600 is 1000 angstroms to 1500 angstroms. The process for forming the resistive layer 600 can be a physical vapor deposition process.

[0054] After the resistive layer 600 is formed, the resistive layer 600, the second sacrificial layer 500 and the first sacrificial layer 300 need to be etched, leaving only the second sacrificial layer 500 and the resistive layer 600 on the second part of the surface of the dielectric layer 200, in order to form a silicon phototitanium nitride heater.

[0055] For details, please refer to Figure 9A photoresist isolation material layer 700 is formed on the surface of the resistive layer 600. A height difference exists between the top surfaces of the photoresist isolation material layer 700 above the first and second portions of the dielectric layer 200, resulting in a stepped distribution. The material of the photoresist isolation material layer 700 can be the same as that of the second sacrificial layer 500 and the dielectric layer 200, for example, including silicon oxide. The photoresist isolation material layer 700 can isolate the resistive layer 600 from the subsequently formed second antireflective material layer 420, thereby improving the uniformity of the second antireflective material layer 420 and consequently enhancing its antireflective capability. The process for forming the photoresist isolation material layer 700 can be a conventional deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and the thickness of the photoresist isolation material layer 700 can be between 20 angstroms and 100 angstroms.

[0056] A second antireflective material layer 420 is formed on the surface of the photoresist isolation material layer 700. This second antireflective material layer 420 serves two purposes: firstly, it provides antireflection; secondly, it fills the height difference between the photoresist isolation material layers 700 above the first and second portions of the dielectric layer 200. Specifically, the top surfaces of the second antireflective material layers 420 above the first and second portions of the dielectric layer 200 are coplanar, which facilitates the subsequent formation of the second photoresist material layer. The material of the second antireflective material layer 420 may include silicon oxynitride.

[0057] Continue to refer to Figure 9 A second photoresist material layer 800 is formed on the surface of the second antireflective material layer 420. In this embodiment, a spin coating process can be used.

[0058] refer to Figure 10 The second photoresist material layer 800, the second anti-reflective material layer 420, and the photoresist isolation material layer 700 above the first portion of the dielectric layer 200 are etched to form the second photoresist layer 810, the second anti-reflective layer 421, and the photoresist isolation layer 710, respectively. The second photoresist layer 810, the second anti-reflective layer 421, and the photoresist isolation layer 710 constitute the second photoresist layer, which covers the surface of the resistive layer 600 above the second portion of the dielectric layer 200.

[0059] Combination Figure 9 and Figure 10Using the second photoresist layer as a mask, the resistive layer 600, the second sacrificial layer 500, and the first sacrificial layer 300 are etched, leaving only the second sacrificial layer 500 and the resistive layer 600 on the second portion of the surface of the dielectric layer 200. The etching process used is dry etching. If the transmittance of the entire resistive layer 600 is calculated as 100%, the transmittance of the remaining resistive layer 600 is no more than 20%. That is to say, when the resistive layer 600 is formed, less than 20% of the resistive layer 600 is in contact with the second sacrificial layer 500. Through the isolation effect of the first sacrificial layer 300, more than 80% of the resistive layer 600 will not contact the dielectric layer 200. Therefore, when the resistive layer 600 is formed, there will be no serious stress mismatch between it and the underlying material, effectively solving the problem of easy peeling of the resistive layer.

[0060] refer to Figure 11 The second photoresist layer 810 and the second anti-reflective layer 421 are removed. The removal of the second photoresist layer 810 can be achieved using an ozone oxidation process, while the removal of the second anti-reflective layer 421 can be achieved using a dry etching process.

[0061] refer to Figure 8 This application also provides a semiconductor structure, including: a substrate 100; a dielectric layer 200 located on the substrate 100, including a first portion and a second portion that are coplanar; a first sacrificial layer 300 located on the surface of the first portion of the dielectric layer 200; a second sacrificial layer 500 located on the surface and sidewalls of the first sacrificial layer 300 and the surface of the second portion of the dielectric layer 200; and a resistive layer 600 located on the surface of the second sacrificial layer 500.

[0062] In this embodiment of the application, the top surface of the second portion of the dielectric layer 200 is lower than the surface of the first portion of the dielectric layer 200, and the top surface of the second sacrificial layer 500 located on the surface of the second portion of the dielectric layer 200 is coplanar with the surface of the first portion of the dielectric layer 200.

[0063] In other embodiments, the top surface of the second portion of the dielectric layer 200 is coplanar with the surface of the first portion of the dielectric layer 200, while the top surface of the second sacrificial layer 500 located on the surface of the second portion of the dielectric layer 200 is higher than the surface of the first portion of the dielectric layer 200.

[0064] In this embodiment of the application, the first sacrificial layer 300 sequentially includes an isolation layer 310 and an auxiliary isolation layer 320 located on a first portion of the surface of the dielectric layer 200, wherein the material of the isolation layer 310 includes amorphous carbon, and the material of the auxiliary isolation layer 320 may include silicon oxide.

[0065] The dielectric layer 200 and the second sacrificial layer 500 are made of silicon oxide, and the resistive layer 600 is made of at least one of elemental metal and metal compound.

[0066] The following sections describe the surface curvature radius tests of semiconductor structures fabricated using the formation method of this application and conventional formation methods, and the test results have been normalized. Figure 12 The results are the normalized radius of curvature test results.

[0067] refer to Figure 12 Wherein, numbers 1 and 2 represent the radii of curvature of a normal wafer surface, numbers 3, 4, and 5 represent the radii of curvature of a semiconductor structure surface fabricated using conventional methods, and numbers 6 and 7 represent the radii of curvature of a semiconductor structure surface fabricated using the method described in this application. For this application, a larger radius of curvature indicates a smaller degree of surface curvature, representing lower stress levels; conversely, a smaller radius of curvature indicates a greater degree of surface curvature, representing higher stress levels. Figure 12 It is known that the radius of curvature of the semiconductor structure surface fabricated using the formation method of this application is closest to the radius of curvature of the normal wafer surface, and is much larger than the radius of curvature of the semiconductor structure surface fabricated using the conventional formation method.

[0068] Therefore, by forming a first sacrificial layer and a second sacrificial layer to avoid direct contact between the resistive layer and the dielectric layer, the problem of resistive layer peeling caused by stress mismatch between the resistive layer and the dielectric layer can be effectively solved, and the device yield can be significantly improved.

[0069] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0070] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0071] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," when used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0072] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0073] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method of forming a semiconductor structure, characterized by, include: A substrate and a dielectric layer located on the substrate are provided, the dielectric layer comprising a first portion and a second portion having coplanar top surfaces; A first sacrificial layer is formed on the surface of a first portion of the dielectric layer; A second sacrificial layer is formed on the surface and sidewalls of the first sacrificial layer and on the second portion of the surface of the dielectric layer; A resistive layer is formed over the entire surface of the second sacrificial layer; The resistive layer, the second sacrificial layer, and the first sacrificial layer are etched, leaving only the second sacrificial layer and the resistive layer on the second portion of the surface of the dielectric layer.

2. The method of forming a semiconductor structure of claim 1, wherein, A conductive layer is formed between the first portion of the dielectric layer and the substrate.

3. The method of forming a semiconductor structure of claim 1, wherein, The first sacrificial layer comprises, in sequence, an isolation layer and an auxiliary isolation layer located on the surface of a first portion of the dielectric layer.

4. The method of forming a semiconductor structure of claim 3, wherein, The material of the isolation layer includes amorphous carbon, and the material of the auxiliary isolation layer includes silicon oxide.

5. The method of forming a semiconductor structure of claim 3, wherein, The process for forming the first sacrificial layer includes: An isolation material layer and an auxiliary isolation material layer are sequentially formed on the surface of the dielectric layer; A first photoresist layer is formed, which covers the surface of an auxiliary isolation material layer above a first portion of the dielectric layer; Using the first photoresist layer as a mask, the auxiliary isolation material layer and the isolation material layer are etched to form the first sacrificial layer.

6. The method of forming a semiconductor structure of claim 5, wherein, The first photoresist layer includes a first anti-reflective layer and a first photoresist layer located on the surface of the first anti-reflective layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The process for forming the first sacrificial layer further includes: Remove the first photoresist layer; Remove the first antireflective layer and a portion of the second portion of the dielectric layer, such that the top surface of the second portion of the dielectric layer is lower than the surface of the first portion of the dielectric layer.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The top surface of the second sacrificial layer located on the second portion of the surface of the dielectric layer is coplanar with the surface of the first portion of the dielectric layer.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the second sacrificial layer includes silicon oxide.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The resistive layer is made of at least one of elemental metals and metal nitrides.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of etching the resistive layer, the second sacrificial layer, and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the second portion surface of the dielectric layer, includes: A second photoresist layer is formed, which covers the surface of the resistive layer above the second portion of the dielectric layer; Using the second photoresist layer as a mask, the resistive layer, the second sacrificial layer, and the first sacrificial layer are etched.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The second photoresist layer sequentially includes a photoresist isolation layer, a second anti-reflection layer, and a second photoresist layer located on the surface of the resistive layer above the second portion of the dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The material of the photoresist isolation layer includes silicon oxide.

14. The method for forming a semiconductor structure according to claim 12, characterized in that, The process for forming the second photoresist layer includes: A photoresistive insulating material layer is formed on the surface of the resistive layer; A second antireflective material layer is formed on the surface of the photoresistive isolation material layer, wherein the top surfaces of the second antireflective material layer above the first portion of the dielectric layer and above the second portion of the dielectric layer are coplanar; A second photoresist material layer is formed on the surface of the second anti-reflective material layer; The second photoresist material layer, the second anti-reflective material layer, and the photoresist isolation material layer above the first portion of the dielectric layer are etched.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The process of etching the resistive layer, the second sacrificial layer, and the first sacrificial layer, leaving only the second sacrificial layer and the resistive layer on the second portion surface of the dielectric layer, further includes: removing the second photoresist layer and the second antireflective layer.

16. A semiconductor structure, characterized in that, include: Substrate; A dielectric layer, located on the substrate, includes a first portion and a second portion that are coplanar; A first sacrificial layer is located on a first portion of the surface of the dielectric layer; The second sacrificial layer is located on the surface and sidewalls of the first sacrificial layer and on a second portion of the surface of the dielectric layer; A resistive layer is located on the entire surface of the second sacrificial layer.

17. The semiconductor structure according to claim 16, characterized in that, The top surface of the second sacrificial layer located on the second portion of the surface of the dielectric layer is coplanar with the surface of the first portion of the dielectric layer.

18. The semiconductor structure according to claim 16, characterized in that, The first sacrificial layer comprises, in sequence, an isolation layer and an auxiliary isolation layer located on the surface of a first portion of the dielectric layer.

19. The semiconductor structure according to claim 18, characterized in that, The material of the isolation layer includes amorphous carbon, and the material of the auxiliary isolation layer includes silicon oxide.

20. The semiconductor structure according to claim 16, characterized in that, The materials of the dielectric layer and the second sacrificial layer include silicon oxide.

21. The semiconductor structure according to claim 16, characterized in that, The resistive layer is made of at least one of elemental metals and metal compounds.

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