Control method and control circuit for a four-switch buck-boost converter

Abstract

This invention discloses a control method and circuit for a four-switch buck-boost converter. The method includes: acquiring the DS voltage v of the fourth switch. dsS4 Compare voltages v dsS4 and threshold v th Output periodic modulation signal Pd md It is used to control the switching frequency of the switching transistors cycle by cycle; based on the periodic set signal P Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm Based on Pd md and Pd Lm Generate periodic set signal P Rst Based on P Rst The invention utilizes the timing of four operating modes in a Clk and four-switch buck-boost converter to generate drive signals for the four switches, thereby achieving main-cycle control of the converter's switching frequency. This invention allows for flexible implementation of strategies for fixing the switching frequency in steady state and varying the switching frequency during large dynamic processes. The invention is simple, convenient, and highly reliable, which is beneficial for achieving high power density and high conversion efficiency in the converter.

Description

Technical Field

[0001] This invention belongs to the field of converter technology, specifically a control method and control circuit for a four-switch Buck-Boost converter. Background Technology

[0002] The four-switch buck-boost converter is a DC / DC circuit topology widely used in power supply fields such as aerospace, communications, and military weaponry due to its high efficiency, reliability, flexibility, and wide input / output range. Figure 1 The four-switch Buck-Boost converter shown includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and an inductor L. One end of the inductor L is connected between the first switch S1 and the second switch S2, and the other end is connected between the third switch S3 and the fourth switch S4. Figure 1 It also includes a converter controller for controlling the switching on and off of the first switch S1 through the fourth switch S4. The input source is a voltage V. in Power is input to the converter, and after passing through the converter, the power is converted into an output voltage V. o Transmitted to the output load.

[0003] Generally, a four-switch Buck-Boost converter consists of four phases within a switching cycle: the input phase, the input-output phase, the freewheeling phase, and the clamping phase, such as... Figure 2 As shown. From Figure 2As can be seen from the converter modal diagram, the four-switch buck-boost converter has a high degree of control freedom. Real-time control of the converter's output voltage can be achieved by adjusting the duration of time intervals T1, T2, and T4. This means that the four-switch buck-boost converter has a very flexible and complex control strategy. Generally speaking, the control strategies of the four-switch buck-boost converter fall into two categories: fixed switching frequency and variable switching frequency. Patent CN106849659 employs a fixed switching frequency algorithm, setting different circuit control parameters in three different operating modes: buck, boost, and buck-boost. This results in a complex and cumbersome control architecture. Furthermore, this patent requires resistor current sampling, which places high demands on the hardware circuitry, and the losses caused by resistor sampling further affect the converter efficiency. In addition, the fixed switching frequency control architecture cannot reliably guarantee cycle-by-cycle magnetic reset of the inductor under conditions such as large jumps in converter load or input voltage, nor can it achieve cycle-by-cycle soft switching. In the paper "Research on Control Strategy of High-Frequency and High-Efficiency Four-Switch Buck-Boost Converter", the authors proposed variable frequency and segmented variable frequency control strategies for digital control. The variable frequency control strategy operates the converter in variable frequency mode across the entire operating range. This strategy typically has a wide operating frequency range, but the switching frequency is high and efficiency is low under light load conditions. The wide operating frequency range also poses significant challenges to the converter's core design and drive design. The segmented variable frequency strategy, implemented through software algorithms, also suffers from the problem of failing to achieve cycle-by-cycle magnetic reset and cycle-by-cycle soft switching of the inductor during large dynamic processes. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a flexible cycle-by-cycle frequency control method and control circuit. This method allows for flexible setting of the converter's maximum frequency and flexible implementation of strategies for fixing the switching frequency in steady state and varying the switching frequency during large dynamic processes. It also effectively achieves cycle-by-cycle magnetic reset and cycle-by-cycle soft switching of the converter inductor. Furthermore, it provides a simple and effective implementation scheme for the parameters of a four-switch buck-boost converter at various time intervals.

[0005] The technical solution to achieve the objective of this invention is: a control method for a four-switch buck-boost converter, the method comprising the following steps:

[0006] Step 1: Collect the drain-source voltage v of the fourth switch in the four-switch buck-boost converter. dsS4 ;

[0007] Step 2, compare the DS voltage v dsS4 And comparison threshold v th Output periodic modulation signal Pd mdIt is used to control the switching frequency of a four-switch buck-boost converter on a cycle-by-cycle basis.

[0008] Step 3, based on the periodic set signal P Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm ;

[0009] Step 4, based on the periodic modulation signal Pd md and minimum period limit signal Pd Lm Generate periodic set signal P Rst ;

[0010] Step 5, based on the periodic set signal P Rst The clock signal Clk and the times T1 to T4 of the four working modes in the four-switch buck-boost converter generate the drive signals QS1 to QS4 of the four switches, realizing the main cycle control of the frequency of the converter switches; the four working modes include the input stage, the input-output stage, the freewheeling stage, and the clamping stage.

[0011] Furthermore, step 3, based on the periodic set signal P Rst The minimum period limit signal P is generated by the clock signal Clk. dLm Specifically, it includes:

[0012] Step 3-1, based on the periodic set signal P Rst A ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value T... rm Accumulate by 1 when the periodic set signal P Rst When it arrives, T rm The value is immediately cleared to zero and the count starts from the beginning;

[0013] Step 3-2, compare the ramp signal count value T rm And the set threshold value, output the minimum cycle limit signal Pd Lm If T rm The minimum cycle limit signal Pd is greater than the set threshold value. Lm A high level indicates a high level, and vice versa.

[0014] Further, step 5, based on the periodic set signal P Rst The clock signal Clk and the turn-on times of the four switches in the four-switch buck-boost converter are used to generate drive signals QS1 to QS4 for the four switches, thereby achieving main cycle control of the converter's switching frequency. Specifically, this includes:

[0015] Step 5-1, based on the periodic set signal P RstA ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value Trip is incremented by 1. When the period is set by the signal P... Rst When it arrives, the Trip value is immediately reset to zero and the count starts from the beginning;

[0016] Step 5-2: Compare the ramp signal count value Trip with the set first threshold value, and generate the drive signals QS1 / QS2 for the first and second switching transistors based on the comparison result.

[0017] Step 5-3: Compare the ramp signal count value Trip with the set second threshold value, and compare the ramp signal count value Trip with the set third threshold value. Based on the two comparison results, generate drive signals QS3 / QS4 for the third and fourth switches. QS3 / QS4 and QS1 / QS2 are a pair of complementary signals with fixed dead time.

[0018] A control circuit for a four-switch buck-boost converter, the circuit comprising: a main power circuit for the four-switch buck-boost converter and a control device;

[0019] The main power circuit of the four-switch buck-boost converter includes a first switch, a second switch, a third switch, a fourth switch, and an inductor. One end of the inductor is connected between the first and second switches, and the other end is connected between the third and fourth switches. The input source is a voltage V. in Power is input to the converter, and after passing through the converter, the power is converted into an output voltage V. o The signal is transmitted to the output load; the on / off control of the first to fourth switching transistors is controlled by the control device.

[0020] The information exchanged between the control device and the main power circuit includes the converter input voltage sample value V. in Output voltage sampling value V o The sampled value V of the drain-source voltage of the fourth switching transistor. dsS4 and the drive signals QS1 to QS4 of the first to fourth switching transistors; the control device samples the input voltage V of the main power circuit. in and output voltage V o To perform output voltage regulation control of the converter; the control device further samples the drain-source voltage V across the fourth switch of the main power circuit. dsS4 To achieve main cycle control of the converter's switching frequency; the control device outputs the first to fourth switch drive signals QS1 to QS4 of the main power circuit to achieve control of the converter's switching frequency and output voltage.

[0021] Furthermore, the control device includes a subtractor, an output voltage closed-loop regulation module, a T1-T4 time period parameter calculation module, a PWM generation module, an analog comparator, a minimum cycle limit module, a two-input AND gate, a data storage module, and a crystal oscillator module;

[0022] The subtractor is used to sample the output voltage value V. o and output voltage reference value V oref Perform subtraction;

[0023] The output voltage closed-loop regulation module is used to perform proportional-integral calculations on the error value output by the subtractor.

[0024] The parameter calculation module for the time period T1 to T4 is used to calculate the input voltage sample value V. in Output voltage sampling value V o The output value V of the output voltage closed-loop regulation module er The output value M of the data storage module is used to calculate the time T1 to T4 of the four-stage buck-boost converter.

[0025] The PWM generation module is used to convert the T1-T4 time period output by the T1-T4 time period parameter calculation module into the high-frequency modulation pulse width of the first to fourth switching transistors of the four-switch buck-boost converter, and output on / off control signals QS1, QS2, QS3, and QS4 to control the converter.

[0026] The analog comparator is used to compare the DS voltage v of the fourth switch. dsS4 and threshold v th Output periodic modulation signal P dmd ;

[0027] The minimum period limit module is used to set the period based on the periodic set signal P. Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm ;

[0028] The two-input AND gate is used to process the periodically modulated signal Pd. md and the minimum period limit signal Pd Lm Perform input AND logic and output a periodic set signal P. Rst ;

[0029] The data storage module is used to store the pre-calculated M value offline;

[0030] The crystal oscillator module is used to generate the clock signal Clk.

[0031] Compared with the prior art, the significant advantages of this invention are:

[0032] 1) Provides a switching cycle frequency control method and control circuit, which can ensure a "fixed" switching frequency in steady-state operation, flexibly limit the converter's maximum frequency, and reliably guarantee the strategy of changing the switching frequency during transient processes to effectively realize the cycle-by-cycle magnetic reset of the converter inductor and the cycle-by-cycle soft switching control, thereby improving the reliability and conversion efficiency of the converter.

[0033] 2) No additional hardware measures are required. The reliable soft switching of the Q2 switch under wide input and output conditions can be achieved simply by adjusting the T2 stage (input-output stage) time of the four-switch buck-boost converter online in real time.

[0034] 3) By limiting the maximum frequency, this invention is beneficial to the design of hardware circuit drivers and also helps to improve the efficiency of the converter under light load.

[0035] 4) The control method and circuit provided by this invention are simple to implement and can be easily implemented by digital microcontrollers (MCUs). The hardware circuit only requires additional resistor voltage divider sampling and analog comparators, which is beneficial for realizing high power density power modules.

[0036] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0037] Figure 1 This is the power circuit diagram for a four-switch buck-boost converter.

[0038] Figure 2 This is a typical waveform diagram of a four-switch buck-boost converter.

[0039] Figure 3 This is a control method and control circuit diagram for a four-switch buck-boost converter in one embodiment of the present invention.

[0040] Figure 4A This is a typical waveform diagram of a four-switch buck-boost converter.

[0041] Figure 4B This is a typical waveform diagram of a four-switch buck-boost converter.

[0042] Figure 5 This is a schematic diagram of the operating modes of a four-switch buck-boost converter.

[0043] Figure 6 This is a block diagram of a PWM generation module in one embodiment of the present invention.

[0044] Figure 7 This is a block diagram of the minimum cycle limiting module in one embodiment of the present invention.

[0045] Figure 8A Typical operating waveforms in one embodiment of the present invention Figure 1 .

[0046] Figure 8B Typical operating waveforms in one embodiment of the present invention Figure 2 .

[0047] Figure 9 This is the second operating mode of the four-switch buck-boost converter.

[0048] Figure 10 The image shows the steady-state experimental waveform of the hardware platform built according to the present invention.

[0049] Figure 11 The image shows the transient experimental waveforms of the hardware platform built according to the present invention. Detailed Implementation

[0050] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0051] In one embodiment, a control method for a four-switch buck-boost converter is provided, the method comprising the following steps:

[0052] Step 1: Collect the drain-source voltage v of the fourth switch S4 in the four-switch buck-boost converter. dsS4 ;

[0053] Step 2, compare the DS voltage v dsS4 And comparison threshold v th Output periodic modulation signal Pd md It is used to control the switching frequency of a four-switch buck-boost converter on a cycle-by-cycle basis.

[0054] Step 3, based on the periodic set signal P Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm ;

[0055] Step 4, based on the periodic modulation signal Pd md and minimum period limit signal Pd Lm Generate periodic set signal P Rst ;

[0056] Step 5, based on the periodic set signal P RstThe clock signal Clk and the times T1 to T4 of the four working modes in the four-switch buck-boost converter generate the drive signals QS1 to QS4 of the four switches S1 to S4, realizing the main cycle control of the converter switching frequency; the four working modes include the input stage, the input-output stage, the freewheeling stage, and the clamping stage.

[0057] Furthermore, in one embodiment, step 3 is based on the periodic set signal P Rst The minimum period limit signal P is generated by the clock signal Clk. dLm Specifically, it includes:

[0058] Step 3-1, based on the periodic set signal P Rst A ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value T... rm Accumulate by 1 when the periodic set signal P Rst When it arrives, T rm The value is immediately reset to zero and the count starts from the beginning;

[0059] Step 3-2, compare the ramp signal count value T rm And the set threshold value, output the minimum cycle limit signal Pd Lm If T rm The minimum cycle limit signal Pd is greater than the set threshold value. Lm A high level indicates a high level, and vice versa.

[0060] Furthermore, in one embodiment, step 5 is based on the periodic set signal P Rst The clock signal Clk and the turn-on times of the four switches in the four-switch buck-boost converter generate drive signals QS1 to QS4 for the four switches S1 to S4, thereby achieving main cycle control of the converter's switching frequency. Specifically, this includes:

[0061] Step 5-1, based on the periodic set signal P Rst A ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value Trip is incremented by 1. When the period is set by the signal P... Rst When it arrives, the Trip value is immediately reset to zero and the count starts from the beginning;

[0062] Step 5-2: Compare the ramp signal count value Trip with the set first threshold value, and generate the drive signals QS1 / QS2 for the first switch S1 and the second switch S2 based on the comparison result.

[0063] Step 5-3: Compare the ramp signal count value Trip with the set second threshold value, and compare the ramp signal count value Trip with the set third threshold value. Based on the two comparison results, generate drive signals QS3 / QS4 for the third switch S3 and the fourth switch S4. QS3 / QS4 and QS1 / QS2 are a pair of complementary signals with fixed dead time.

[0064] Furthermore, in one embodiment, the first threshold value, the second threshold value, and the third threshold value are respectively taken as T1+T2, T1, and T1+T2+T3, where T1, T2, and T3 are the times of the three working modes of the four-switch buck-boost converter: the input stage, the input-output stage, and the freewheeling stage.

[0065] In one embodiment, combined Figure 3 A control circuit for a four-switch buck-boost converter is provided, the circuit comprising: a main power circuit 300 for the four-switch buck-boost converter and a control device 301;

[0066] The main power circuit 300 of the four-switch buck-boost converter includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and an inductor L. One end of the inductor L is connected between the first switch S1 and the second switch S2, and the other end is connected between the third switch S3 and the fourth switch S4. The input source is a voltage V. in Power is input to the converter, and after passing through the converter, the power is converted into an output voltage V. o The current is transmitted to the output load; the on / off control of the first switch S1 to the fourth switch S4 is controlled by the control device 301; furthermore, for ease of description, this application names the current flowing through the inductor L as i L The current i L The positive direction is defined as the flow from the connection point of the first switch S1 and the second switch S2 to the connection point of the third switch S3 and the fourth switch S4. The control device 301 controls the switching frequency and output voltage of the converter by controlling the on / off state of the first to fourth switches of the main power circuit 300. The core device of the specific physical circuit of the control device 301 can be a microcontroller (MCU) integrating analog circuits such as analog comparators and analog operational amplifiers, or a field-programmable logic device (FPGA) integrating analog circuits such as analog comparators and analog operational amplifiers, or a control system composed of a microcontroller or programmable logic device core combined with external analog circuits such as analog comparators and operational amplifiers.

[0067] The information exchanged between the control device 301 and the main power circuit 300 includes the converter input voltage sampling value V. in Output voltage sampling value V oThe sampled value V of the drain-source voltage across the fourth switch S4 dsS4 and the drive signals QS1 to QS4 of the first to fourth switching transistors S1 to S4; the control device 301 samples the input voltage V of the main power circuit 300. in and output voltage V o To perform output voltage regulation control of the converter; the control device 301 further samples the drain-source voltage V across the fourth switch S4 of the main power circuit 300. dsS4 To achieve main cycle control of the converter switching frequency; the control device 301 outputs the first to fourth switch drive signals QS1 to QS4 of the main power circuit 300 to achieve control of the converter switching frequency and output voltage.

[0068] Furthermore, the control device 301 includes a subtractor 302, an output voltage closed-loop adjustment module 303, a time period parameter calculation module 304, a PWM generation module 305, an analog comparator 306, a minimum cycle limit module 307, a two-input AND gate 308, a data storage module 309, and a crystal oscillator module 310.

[0069] (a) Subtractor 302

[0070] Subtractor 302 module samples the output voltage value V. o and output voltage reference value V oref The subtraction operation is performed, and the output signal of the subtractor is used as the input signal of the output voltage closed-loop regulation module 303.

[0071] (II) Output Voltage Closed-Loop Regulation Module 303

[0072] The output voltage closed-loop regulation module 303 regulates the output voltage V. o and output reference value V oref The error value is calculated using a proportional-integral operation, i.e., V er =k p +k i / s×V oref -V o ;where k p and k i These are the proportional and integral coefficient constants, respectively. Their specific values ​​can be optimized based on the specific operating conditions of the four-switch buck-boost converter.

[0073] (III) Module 304 for calculating parameters for time period T1 to T4

[0074] The T1-T4 time period parameter calculation module 304, where the definition of the T1-T4 time period is as follows: Figure 2 Module 304's input signal terminal includes the input voltage sampling value V of a four-switch buck-boost converter.in Output voltage sampling value V o Module 303 regulator output value V er And the output value M of data storage module 309; the output signal of module 304 is the time value T1 to T4 for the time period T1 to T4; the specific calculation formula for the parameters of the time period T1 to T4 by module 304 is as follows:

[0075]

[0076]

[0077]

[0078] T4 = T s -T1-T2-T3 (4)

[0079] In the formula, V er T is the regulator output value of the output voltage closed-loop regulation module 303; M is the output value of the data storage module 309. This variable can be a fixed value or a value that changes with the input and output voltages and the converter load operating conditions. The specific value of the data storage module 309 is calculated offline and pre-stored in the memory. When the converter is running, the specific value of M corresponding to the current converter operating state is obtained by searching the data storage module 309. In equation (4), T s It is a value taken over one switching cycle. In equation (2), ΔI m It is a pre-set fixed value, usually about 5% of the rated input current of the converter; L in the formula (2) is the nominal inductance value of the inductor of the four-switch buck-boost converter in the main power circuit.

[0080] From equations (1) to (2), we know that the time and output voltage closed-loop regulator module 303 of the four-switch buck-boost converter in the T1 and T2 segments are v er The time intervals T1 and T2 are proportional, meaning that when the converter output voltage drops, the time intervals T1 and T2 will increase to adjust the output voltage; the time interval T3 is used to achieve cycle-by-cycle reset of the converter inductor L, which will be discussed below. Figure 2 This conclusion will be further explained.

[0081] During time period T1, the first switch S1 and the fourth switch S4 are turned on, and the input voltage and ground are applied across the inductor L, respectively. During this period, the inductor current flows as follows: The slope increases, and during this stage, inductor L begins to store energy; the change in current of inductor L is:

[0082]

[0083] During time period T2, the first switch S1 and the third switch S3 are turned on, and the input voltage and output voltage are applied across the inductor L, respectively. The inductor current flows as follows: The slope of the curve changes, and during this stage, both the input terminal and the converter inductor transfer energy to the load; during this stage, the change in current of inductor L is:

[0084]

[0085] During time period T3, the second switch S2 and the third switch S3 are turned on; the output voltage and ground are applied across the inductor L, and the inductor current flows as follows: The slope decreases; during this phase, the change in current of inductor L is:

[0086]

[0087] Substituting equation (3) into equation (7) yields the following:

[0088]

[0089] During time period T4, the second switch S2 and the fourth switch S4 are turned on, the inductor current remains constant, and the converter neither absorbs energy from the input nor outputs energy to the load. The change in current of inductor L during this time period is as follows:

[0090] Δi L4 =0 (9)

[0091] By summing the changes in inductor current over each time period from equation (5) to equation (9), we can obtain the change in inductor current over one switching cycle:

[0092] Δi Lt =Δi L1 +Δi L2 +Δi L3 +Δi L4 =0 (10)

[0093] As can be seen from equation (10), the present invention achieves cycle-by-cycle reset of the inductor of the four-switch buck-boost converter by selecting an appropriate T3 time period value.

[0094] The following will further combine Figure 4A and Figure 4B Explain the physical meaning of equation (2). See also Figure 2 When the four-switch buck-boost converter operates in buck mode, the inductor current continuously increases during the T2 time period. (See also...) Figure 4A When the four-switch buck-boost converter operates in boost mode, the inductor current decreases during time period T2. Furthermore, if the time periods T1 and T2 are not allocated appropriately, it is easy for problems to occur. Figure 4B The phenomenon shown indicates that at the end of time period T2, the current in inductor L will drop to near zero, which is detrimental to the zero-voltage turn-on of the second switch S2 of the four-switch buck-boost converter. See also... Figure 5 During the dead time before the first switch S1 of the converter is turned off and the second switch S2 is turned on, the inductor current i L The inductor current i flows through the parasitic capacitance C2 of the second switch S2 and the channel of the third switch S3. L The parasitic capacitance C2 of the second switching transistor is discharged and its energy is recovered to the output. If the inductor current i at this time... L If the current is too small, the inductor current energy will be insufficient to discharge the charge of C2, and the second switch will not be able to achieve zero-voltage turn-on, thus affecting the efficiency of the converter. To address this problem, the present invention proposes the solution shown in equation (2) above.

[0095] Referring to equations (5) and (6) above, at the end of time period T2, the inductor current i L The value is,

[0096]

[0097] i T4 Let T4 be the inductor current value of the converter at the end of time period T4. Substituting equations (1) and (2) into the above equation, we get...

[0098]

[0099] As can be seen from equation (12), through reasonable ΔI m The parameter selection method of the present invention, based on the T2 time period parameter design method, ensures that even when the four-switch buck-boost converter is operating in boost mode, the inductor current i will remain constant at the end of the T2 time period. L The value can still maintain a sufficiently large amplitude to reliably achieve the soft switching of the second switching transistor S2 of the converter.

[0100] (iv) PWM Generation Module

[0101] See Figure 3 The input signal to the PWM generation module 305 is the output signal of module 304 during the time period T1 to T4, and the periodic set signal P. Rst The clock signal Clk. The function of the 305 module is to convert the time period from T1 to T4 into a specific timing sequence (see...). Figure 2 ) combined PWM signals.

[0102] Figure 6A detailed block diagram of the PWM generation module of this invention is provided, including digital comparator 1, digital comparator 2, digital comparator 3, comparator threshold 1, comparator threshold 2, comparator threshold 3, complementary and insertion dead-time module 1, complementary and insertion dead-time module 2, two-input AND gate 1, and digital counting ramp generation module 1. The output signal Trip of the ramp generation module is connected to the negative terminal of digital comparator 1, the positive terminal of digital comparator 2, and the negative terminal of digital comparator 3. Comparator threshold 1 is connected to the positive terminal of digital comparator 1; comparator threshold 2 is connected to the negative terminal of digital comparator 2; and comparator threshold 3 is connected to the positive terminal of digital comparator 3. The specific values ​​of comparator threshold 1 to comparator threshold 3 are T1+T2, T1, and T1+T2+T3, respectively; the values ​​of T1 to T4 are derived from... Figure 3 The parameter calculation module 304. The working principle of digital comparators 1 to 3 is that when the value at the positive terminal is greater than the value at the negative terminal, the digital comparator outputs a high level. This level signal, after passing through the complementary and dead-time insertion module, generates a pair of complementary signals QS1 / QS2 and QS3 / QS4 with a fixed dead time. The input signals of the digital counting ramp generation module 1 are the clock signal Clk and the periodic set signal P. Rst When the clock signal arrives, the ramp counter value Trip is incremented by 1, and when the set signal arrives, the Trip value is cleared to zero and the count starts from the beginning.

[0103] (V) Analog Comparator 306

[0104] See Figure 3 The analog comparator 306 samples the DS voltage v of the fourth switch S4. dsS4 And comparison threshold v th Comparison, when the sampled voltage v dsS4 Below the comparison threshold v th At that time, the analog comparator 306 outputs a periodic modulation signal Pd. md A high level indicates a signal high, and vice versa. The periodic modulation signal Pd... md The mechanism used to control the switching frequency of a four-switch buck-boost converter cycle by cycle will be explained in detail below.

[0105] (vi) Minimum cycle limit module 307

[0106] See Figure 3 The input signal of the minimum period limit module 307 is the period set signal P. Rst And the clock signal Clk, output the minimum period limit signal Pd Lm The Pd LmThe signal is used to limit the minimum cycle, i.e., the maximum frequency, of the four-switch buck-boost converter. By limiting the maximum frequency, this invention benefits both the design of the hardware circuit driver and the improvement of the converter's light-load efficiency.

[0107] Figure 7 A detailed block diagram of the minimum cycle limiting module of the present invention is provided, including a comparator threshold 4, a digital counting ramp generation module 2, and a digital comparator 4. The comparator threshold 4 is connected to the negative terminal of the digital comparator 4, and the output signal T of the digital counting ramp generation module 2 is... rm Connected to the positive terminal of digital comparator 4. When the ramp signal T... rm If the digital value is greater than the digital value of the comparator threshold 4, the digital comparator 4 outputs a high level; otherwise, it outputs a low level. The input signals of the digital counting ramp generation module 2 are the clock signal Clk and the periodic set signal P. Rst When the clock signal arrives, the ramp count value T rm The increment is 1, and when the set signal P... Rst When it arrives, T rm The value is immediately reset to zero and the count starts from the beginning.

[0108] (vii) Two-input AND gate module 308

[0109] See Figure 3 The two-input AND gate module 308 converts the periodic modulation signal Pd output by the analog comparator 306 into a frequency modulation signal. md and the minimum period limit signal Pd output by the minimum period limit module 307. Lm The input logic is ANDed, and the output signal is a periodic set signal P. Rst The set signal is connected as an input signal to modules 307 and 305.

[0110] (viii) Crystal oscillator module 310

[0111] See Figure 3 The crystal oscillator module 310 outputs the clock signal of the digital system, which is used to generate the clock signal for the digital counting of modules 305 and 307.

[0112] The following will combine Figure 8A and 8B This paper details the cycle-by-cycle switching frequency adjustment strategy of the present invention. See also... Figure 8A The schematic waveforms of this invention, from top to bottom, represent the digital counting ramp signal Trip (see [reference]). Figure 6 The drive signals QS1 to QS4 of the first to fourth switches of the four-switch buck-boost converter, and the inductor current waveform i of the converter. L The converter periodic modulation signal Pd mdPeriodic limiting signal Pd Lm Digital counting ramp signal Trm (see Figure 6 ) and periodic set signal P Rst .

[0113] The digital counting ramp signal Trip continuously accumulates within one switching cycle (the Trip signal is incremented by 1 each time the clock signal Clk arrives), until the cycle set signal P. Rst Upon arrival, the Trip signal is immediately cleared and the counting restarts. Within one counting cycle, which is also one switching cycle of the converter, the Trip signal can be divided into four time periods, T1 to T4, according to... Figure 6 The PWM generation module 305 shown generates drive signals QS1 to QS4 for the four-switch buck-boost converter. During time period T1, the inductor current increases; during time period T2, the inductor current continues to increase (Figure 8 corresponds to the converter operating in buck mode; if the converter is operating in boost mode, the inductor current decreases during this stage); during stage T3, the inductor current decreases; and during stage T4, the inductor current freewheeling remains constant. See also... Figure 9 At the end of stage T3, converter S3 is turned off, and the inductor current i L The inductor current has dropped to a negative value. It charges and discharges through the channel of the second switch S2 in the four-switch converter and through the junction capacitances C3 and C4 of the third and fourth switches. The drain-source voltage of the fourth switch S4 begins to decrease, and when it drops to... Figure 3 The analog comparator threshold v of module 306 shown th At that time, the periodic modulation signal Pd md The signal flips to a high level, and then the converter S4 is turned on, Pd md Maintain high level until the next switch S3 is turned on, Pd md The signal toggles to low. Referring to Figure 8, the digital counting ramp signal Trm continuously accumulates within one switching cycle (Trm is incremented by 1 each time the clock signal Clk arrives), until the cycle set signal P... Rst Upon arrival, the Trm signal is immediately reset to zero and the counting restarts. See also Figure 7 When the value of the digital counting ramp signal Trm exceeds the comparator threshold T Lm At that time, digital comparator 4 operates, Pd Lm The output signal toggles to a high level. When the set signal P... Rst When the signal arrives, the digital counting ramp signal Trm is immediately cleared to zero, and the value of Trm is less than the comparator threshold value T. Lm Period-limited signal Pd Lm The signal toggles to a low level. The digital comparator threshold value T... LmThis refers to the minimum cycle time of a four-switch buck-boost converter, which is also the upper limit of the switching frequency. This value is typically between 0.5 μs and 10 μs, and the specific value needs to be determined based on the application. See also... Figure 9 Periodic set signal P Rsts The periodic set signal P is obtained by digital AND logic processing of the periodic modulation signal and the periodic limiting signal. Rst When the signal flips to a high level, the digital counter ramp signals Trip and Trm are immediately cleared to zero, and the next switching cycle begins. Figure 8A It can be seen that the periodic modulation signal Pd md The high level arrives before the lowest cycle limit signal Pd. Lm Periodic set signal P Rst The period time is limited by the minimum period signal Pd Lm The converter operates at the minimum cycle, i.e., the highest clamping switching frequency, due to clamping.

[0114] See Figure 8B When the load on the four-switch buck-boost converter increases, the input voltage decreases, or the converter experiences a large dynamic transient process, the durations of time periods T1 and T2 become longer, corresponding to the periodic modulation signal Pd. md The arrival time of the high-level signal lags behind the period limit signal Pd. Lm The final periodic set signal P of the converter Rst That is, the switching frequency of the converter will be determined by the periodic modulation signal Pd. md It is determined that the switching period of the converter will be greater than the minimum limiting period T at this time. Lm The actual operating cycle of the converter is determined by the periodic modulation signal Pd. md Therefore, this signal is called a "periodic modulation" signal.

[0115] Combination Figure 8A and Figure 8B According to the control method proposed in this invention, the switching period of the four-switch buck-boost converter is determined by the periodic modulation signal Pd. md and period-limited signal Pd Lm The Pd was jointly decided. md and Pd Lm The signal is subjected to a logical AND operation to generate a periodic set signal P. Rst The set signal P Rst Clear all digital counter ramps and begin a new switching cycle. The cycle limit signal Pd Lm The minimum switching period of the converter is limited. Under conditions such as light load or high input voltage, the converter operates at its minimum switching period. Under heavy load, low input voltage, or large dynamic processes, the switching period of the converter is determined by the periodic modulation signal Pd. mdThe decision is made to automatically increase the switching cycle of the converter, ensuring that the inductor current naturally decreases to a negative value, achieving natural magnetic reset. This reliably guarantees that the converter can achieve soft switching in both steady-state and transient processes. See also... Figure 8A and Figure 8B The periodic set signal P Rst Each switching cycle generates a corresponding trigger signal, which means that the frequency control method of the present invention is to adjust and control the frequency cycle by switching cycle, which is beneficial to realize cycle-by-cycle magnetic reset and converter soft switching.

[0116] It should be noted that by reasonably setting the minimum cycle limit value T of the converter... Lm (see Figure 7 For example, setting the T Lm The value is greater than the periodic modulation signal Pd under the condition of minimum input / output voltage and full output load. md The period value can be determined so that the converter can operate at a fixed switching period under steady-state conditions with full input and output voltage and full load range. In this way, the converter will only automatically reduce the switching frequency under necessary conditions such as extreme transients to achieve cycle-by-cycle inductor magnetic reset and cycle-by-cycle soft switching of the converter. This will simplify the design of magnetic components and converter drive circuits.

[0117] To further illustrate the advantages of this control method, a prototype was built, and the test waveforms are shown below. Figure 10 and Figure 11 As shown. Figure 10 The key experimental waveforms under the conditions of 28V input voltage, 36V output voltage, and 120W output load are presented. It can be seen that the converter operates at a fixed switching frequency in steady state, with the periodic set signal P. Rst Cycle-by-cycle reset converter. Figure 11 The waveform of the extreme transient state when the output load is suddenly short-circuited is given. It can be seen that as the output load suddenly increases, the converter periodically modulates the signal Pd. md By automatically reducing the extended switching cycle cycle, cycle-by-cycle inductor magnetic reset and cycle-by-cycle soft switching of the converter are reliably achieved.

[0118] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principle of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A control method for a four-switch buck-boost converter, characterized in that, The method includes the following steps: Step 1: Collect the drain-source voltage v of the fourth switch (S4) in the four-switch buck-boost converter. dsS4 ; Step 2, compare the DS voltage v dsS4 And comparison threshold v th Output periodic modulation signal Pd md It is used to control the switching frequency of a four-switch buck-boost converter on a cycle-by-cycle basis. Step 3, based on the periodic set signal P Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm ; Step 4, based on the periodic modulation signal Pd md and minimum period limit signal Pd Lm Generate periodic set signal P Rst ; Step 5, based on the periodic set signal P Rst The clock signal Clk and the times T1 to T4 of the four working modes in the four-switch buck-boost converter generate the drive signals QS1 to QS4 of the four switches (S1 to S4) to realize the main cycle control of the frequency of the converter switches; the four working modes include the input stage, the input-output stage, the freewheeling stage and the clamping stage.

2. The control method for the four-switch buck-boost converter according to claim 1, characterized in that, Step 3 is based on the periodic set signal P Rst The minimum period limit signal P is generated by the clock signal Clk. dLm Specifically, it includes: Step 3-1, based on the periodic set signal P Rst A ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value T... rm Accumulate by 1 when the periodic set signal P Rst When it arrives, T rm The value is immediately cleared to zero and the count starts from the beginning; Step 3-2, compare the ramp signal count value T rm And the set threshold value, output the minimum cycle limit signal Pd Lm If T rm The minimum cycle limit signal Pd is greater than the set threshold value. Lm A high level indicates a high level, and vice versa.

3. The control method for the four-switch buck-boost converter according to claim 1, characterized in that, Step 5 is based on the periodic set signal P Rst The clock signal Clk and the turn-on times of the four switches in the four-switch buck-boost converter generate drive signals QS1 to QS4 for the four switches (S1 to S4), thereby achieving main cycle control of the converter's switching frequency. Specifically, this includes: Step 5-1, based on the periodic set signal P Rst A ramp signal count is performed using the clock signal Clk. When the clock signal Clk arrives, the ramp signal count value Trip is incremented by 1. When the period is set by the signal P... Rst When it arrives, the Trip value is immediately reset to zero and the count starts from the beginning; Step 5-2: Compare the ramp signal count value Trip with the set first threshold value, and generate drive signals QS1 / QS2 for the first switch (S1) and the second switch (S2) based on the comparison result; Step 5-3: Compare the ramp signal count value Trip with the set second threshold value, and compare the ramp signal count value Trip with the set third threshold value. Based on the two comparison results, generate drive signals QS3 / QS4 for the third switch (S3) and the fourth switch (S4). QS3 / QS4 and QS1 / QS2 are a pair of complementary signals with fixed dead time.

4. The control method for the four-switch buck-boost converter according to claim 3, characterized in that, The first threshold, the second threshold, and the third threshold are respectively set to T1+T2, T1, and T1+T2+T3, where T1, T2, and T3 are the times of the three working modes of the four-switch buck-boost converter: the input stage, the input-output stage, and the freewheeling stage.

5. A control circuit for a four-switch buck-boost converter based on the method of any one of claims 1 to 4, characterized in that, The circuit includes: a four-switch buck-boost converter main power circuit (300) and a control device (301); The main power circuit (300) of the four-switch buck-boost converter includes a first switch (S1), a second switch (S2), a third switch (S3), a fourth switch (S4), and an inductor (L). One end of the inductor (L) is connected between the first switch (S1) and the second switch (S2), and the other end is connected between the third switch (S3) and the fourth switch (S4). The input source is a voltage V. in Power is input to the converter, and after passing through the converter, the power is converted into an output voltage V. o The power is transmitted to the output load; the on / off control of the first switch (S1) to the fourth switch (S4) is controlled by the control device (301); The information exchanged between the control device (301) and the main power circuit (300) includes the converter input voltage sample value V. in Output voltage sampling value V o The sampled value V of the drain-source voltage across the fourth switch (S4) dsS4 and the drive signals QS1 to QS4 of the first to fourth switching transistors (S1 to S4); the control device (301) samples the input voltage V of the main power circuit (300). in and output voltage V o To perform output voltage regulation control of the converter; the control device (301) further samples the drain-source voltage V of the fourth switch (S4) of the main power circuit (300). dsS4 To achieve main cycle control of the converter switching frequency; the control device (301) outputs the first to fourth switch drive signals QS1 to QS4 of the main power circuit (300) to achieve control of the converter switching frequency and output voltage.

6. The control circuit of the four-switch buck-boost converter according to claim 5, characterized in that, The control device (301) includes a subtractor (302), an output voltage closed-loop regulation module (303), a time period parameter calculation module (304) for T1 to T4, a PWM generation module (305), an analog comparator (306), a minimum cycle limit module (307), a two-input AND gate (308), a data storage module (309), and a crystal oscillator module (310). The subtractor (302) is used to sample the output voltage value V. o and output voltage reference value V oref Perform subtraction; The output voltage closed-loop regulation module (303) is used to perform proportional-integral calculation on the error value output by the subtractor (302); The parameter calculation module (304) for the time period T1 to T4 is used to calculate the input voltage sampling value V. in Output voltage sampling value V o The output value V of the output voltage closed-loop regulation module (303) er The output value M of the data storage module (309) is used to calculate the time T1 to T4 of the four stages of the four-switch buck-boost converter; The PWM generation module (305) is used to convert the T1-T4 time period output by the T1-T4 time period parameter calculation module (304) into the high-frequency modulation pulse width of the first switch (S1) to the fourth switch (S4) of the four-switch buck-boost converter, and output on / off control signals QS1, QS2, QS3 and QS4 to realize the control of the converter. The analog comparator (306) is used to compare the DS voltage v of the fourth switch (S4). dsS4 and threshold v th Output periodic modulation signal P dmd ; The minimum period limit module (307) is used to limit the period based on the period set signal P. Rst The minimum period limit signal Pd is generated by the clock signal Clk. Lm ; The two-input AND gate (308) is used to process the periodic modulation signal Pd. md and the minimum period limit signal Pd Lm Perform input AND logic and output a periodic set signal P. Rst ; The data storage module (309) is used to store the pre-calculated M value offline; The crystal oscillator module (310) is used to generate the clock signal Clk.

7. The control circuit of the four-switch buck-boost converter according to claim 6, characterized in that, The formula for the proportional-integral operation of the output voltage closed-loop regulation module (303) on the error value output by the subtractor (302) is as follows: V er =(k p +k i / s)×(V oref -V o ) In the formula, k p and k i These are the proportional and integral coefficient constants, respectively.

8. The control circuit of the four-switch buck-boost converter according to claim 6, characterized in that, The specific formula for calculating time period T1 to T4 by the parameter calculation module (304) is as follows: T4=T s -T1-T2-T3 In the formula, ΔI m It is a preset fixed value, L is the nominal inductance value of the inductor of the four-switch buck-boost converter, and T is a fixed value. s This represents the period value of the converter.

9. The control circuit of the four-switch buck-boost converter according to claim 6, characterized in that, The PWM generation module (305) includes digital comparator 1, digital comparator 2, digital comparator 3, comparator threshold 1, comparator threshold 2, comparator threshold 3, complementary and insertion dead-time module 1, complementary and insertion dead-time module 2, two-input AND gate 1, and digital counting ramp generation module 1; the input of the digital counting ramp generation module 1 is the periodic set signal P. Rst The clock signal Clk and the output signal Trip are connected to the negative terminal of digital comparator 1, the positive terminal of digital comparator 2, and the negative terminal of digital comparator 3. When the clock signal Clk arrives, the value of the output signal Trip is incremented by 1, and when the period set signal arrives, the value of the output signal Trip is cleared to zero and the counting starts from the beginning. The comparator threshold 1 is connected to the positive terminal of digital comparator 1, the comparator threshold 2 is connected to the negative terminal of digital comparator 2, and the comparator threshold 3 is connected to the positive terminal of digital comparator 3. The working principle of digital comparators 1 to 3 is as follows: when the value at the positive terminal is greater than the value at the negative terminal, the digital comparator outputs a high level. The level signal output by digital comparator 1 is passed through the complementary and dead-time insertion module 1 and outputs the drive signals QS1 / QS2 for the first switch (S1) and the second switch (S2). The level signals output by digital comparators 2 and 3 are passed through the two-input AND gate 1 and input to the complementary and dead-time insertion module 2, which outputs the drive signals QS3 / QS4 for the third switch (S3) and the fourth switch (S4).

10. The control circuit of the four-switch buck-boost converter according to claim 6, characterized in that, The minimum cycle limiting module (307) includes a comparator threshold 4, a digital counting ramp generation module 2, and a digital comparator 4; the comparator threshold 4 is connected to the negative terminal of the digital comparator 4, and the output ramp signal count value T of the digital counting ramp generation module 2 is... rm Connected to the positive terminal of digital comparator 4; when the ramp signal count value T rm If the digital value is greater than the digital value of the comparator threshold 4, the digital comparator 4 outputs a high level; otherwise, it outputs a low level. The input signals of the digital counting ramp generation module 2 are the clock signal Clk and the periodic set signal P. Rst When the clock signal Clk arrives, the ramp signal count value T rm The value is incremented by 1, while the periodic set signal P... Rst When it arrives, the ramp signal count value T rm The value is immediately reset to zero and the count starts from the beginning.

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