Semiconductor device structure and manufacturing method thereof

Abstract

The present invention discloses a semiconductor element structure and a method for manufacturing the same, wherein the semiconductor element structure includes a circuit substrate. A first metal block layer is arranged on the circuit substrate. A buffer layer is arranged on the first metal block layer. An absorption layer is arranged on the buffer layer. A first electrode layer is arranged on the absorption layer. A plurality of piezoelectric material units are arranged on the first electrode layer. A protective layer is conformally arranged on the plurality of piezoelectric material units. A second metal block layer is arranged above the plurality of piezoelectric material units and includes a first component and a second component. The first component is arranged on the plurality of piezoelectric material units through the protective layer and serves as a second electrode layer. The second component is at the same height as the first component and is at least electrically connected to the first electrode layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor manufacturing technology, and in particular to a semiconductor element structure and a manufacturing method thereof. Background Art

[0002] Surface acoustic waves (SAW) are sound waves that propagate along the surface of elastic materials, and their amplitude usually decays exponentially with the depth of penetration into the material.

[0003] Surface acoustic wave devices are used as components in circuits to provide a variety of functions, including delay lines, filters, correlators, and DC-DC converters. Due to their lightweight and compact structure, surface acoustic wave devices are also used in mobile phones.

[0004] With the adoption of higher-frequency circuits, such as the high-frequency operation of 5G mobile phones, surface acoustic wave (SAW) filters are being replaced with bulk acoustic wave (BAW) filters, which are suitable for higher-frequency operation. In integrated circuits, BAW filters are integrated with the circuit substrate during manufacturing. This circuit substrate, for example, includes both conventional silicon-based operating circuits and GaN-based high-frequency operating circuits.

[0005] The manufacturing technology for effectively integrating BAW filters into circuit substrates is still under development. Summary of the Invention

[0006] The present invention proposes a structure for integrating a BAW filter into a circuit substrate and a manufacturing method thereof, which can effectively combine the BAW filter and its application circuit together.

[0007] In one embodiment, the present invention provides a semiconductor device structure comprising a circuit substrate. A first metal block layer is disposed on the circuit substrate. A buffer layer is disposed on the first metal block layer. An absorption layer is disposed on the buffer layer. A first electrode layer is disposed on the absorption layer. A plurality of piezoelectric material units are disposed on the first electrode layer. A protective layer is conformally disposed on the plurality of piezoelectric material units. A second metal block layer is disposed above the plurality of piezoelectric material units and comprises a first component and a second component. The first component is disposed on the plurality of piezoelectric material units through the protective layer and serves as a second electrode layer. The second component is at the same height as the first component and is electrically connected to at least the first electrode layer.

[0008] In one embodiment, the semiconductor device structure further includes an inter-layer dielectric layer to support the second metal block layer, wherein the protection layer is harder than the inter-layer dielectric layer.

[0009] In one embodiment, for the semiconductor device structure, the absorption layer is a multi-layer stacked structure.

[0010] In one embodiment, for the semiconductor device structure, the absorption layer includes a plurality of buried air gap regions corresponding to the plurality of piezoelectric material units.

[0011] In one embodiment, for the semiconductor device structure, the first electrode layer has a connecting portion extending from the plurality of piezoelectric material units, and a plug is connected between the connecting portion and the second component of the second metal block layer.

[0012] In one embodiment, for the semiconductor device structure, the second metal block layer further includes a third component electrically connected to the first metal block layer via a plug structure.

[0013] In one embodiment, for the semiconductor device structure, the first metal block layer is also electrically connected to the wiring structure of the circuit substrate.

[0014] In one embodiment, for the semiconductor device structure, the circuit substrate includes a first device circuit layer and a second device circuit layer above the first device circuit layer.

[0015] In one embodiment, for the semiconductor device structure, the first device circuit layer includes silicon devices, and the second device circuit layer includes GaN devices.

[0016] In one embodiment, for the semiconductor device structure, the first device circuit layer of the circuit substrate includes a thermal detection device.

[0017] In one embodiment, for the semiconductor device structure, the first electrode layer below the plurality of piezoelectric material units is surrounded by an interlayer dielectric layer on the absorption layer.

[0018] In one embodiment, the present invention further provides a method for manufacturing a semiconductor element, comprising providing a circuit substrate. Forming a first metal block layer on the circuit substrate. Forming a buffer layer on the first metal block layer. Forming an absorption layer on the buffer layer. Forming a first electrode layer on the absorption layer. Forming a plurality of piezoelectric material units on the first electrode layer. Forming a protective layer conformally disposed on the plurality of piezoelectric material units. Forming a second metal block layer above the plurality of piezoelectric material units. The second metal block layer includes a first component and a second component. The first component is disposed on the plurality of piezoelectric material units through the protective layer and serves as a second electrode layer. The second component is at the same height as the first component and is at least electrically connected to the first electrode layer.

[0019] In one embodiment, the method for manufacturing a semiconductor device further includes forming an inter-layer dielectric layer to support the second metal block layer, wherein the protection layer is harder than the inter-layer dielectric layer.

[0020] In one embodiment, in the method for manufacturing a semiconductor device, the step of forming the absorption layer is to form a multi-thin layer stack structure formed by alternating multiple layers of two different materials.

[0021] In one embodiment, in the method for manufacturing a semiconductor device, the step of forming the absorption layer includes forming a dielectric layer comprising a sacrificial material layer embedded in the dielectric layer. After forming the protective layer on the plurality of piezoelectric material units, the sacrificial material layer is removed to form a plurality of air gap regions. The plurality of air gap regions correspond to the plurality of piezoelectric material units.

[0022] In one embodiment, for the method of manufacturing a semiconductor device, the first electrode layer has a connecting portion extending from the plurality of piezoelectric material units, and a plug is connected between the connecting portion and the second component of the second metal block layer.

[0023] In one embodiment, in the method for manufacturing a semiconductor device, the second metal block layer formed further includes a third component electrically connected to the first metal block layer via a plug structure.

[0024] In one embodiment, in the method for manufacturing a semiconductor device, the formed first metal block layer is also electrically connected to the line wiring structure of the circuit substrate.

[0025] In one embodiment, for the method of manufacturing a semiconductor device, the circuit substrate provided includes a first device circuit layer and a second device circuit layer above the first device circuit layer.

[0026] In one embodiment, in the method for manufacturing a semiconductor device, the first device circuit layer includes silicon devices, and the second device circuit layer includes GaN devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0028] Figure 1 1 is a schematic cross-sectional view of a semiconductor device integrated with a BAW filter according to an embodiment;

[0029] Figures 2 to 5 is a schematic diagram of a cross-sectional structure of a manufacturing process for manufacturing a semiconductor device including a BAW filter according to an embodiment; and

[0030] Figures 6 to 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a manufacturing process for a semiconductor device including a BAW filter according to an embodiment.

[0031] Explanation of Figure Numbers

[0032] 50: Circuit board 50

[0033] 60: Acoustic filter

[0034] 100: shielding metal layer

[0035] 102: buffer layer

[0036] 104: Silicon layer

[0037] 106: Silicon components

[0038] 108: Inline structure

[0039] 110: buffer layer

[0040] 112:GaN components

[0041] 114: Inline structure

[0042] 120:BAW filter layer

[0043] 122: Metal layer

[0044] 124: Plug

[0045] 200:Metal layer

[0046] 202: buffer layer

[0047] 204: Absorption layer

[0048] 204a: Multi-layer stacking structure

[0049] 204b: Air gap structure

[0050] 206: electrode layer

[0051] 206a: Extension area

[0052] 208: Inner dielectric layer

[0053] 210: piezoelectric material layer

[0054] 210': Piezoelectric material unit

[0055] 212, 214: protective layer

[0056] 214: Protective layer

[0057] 216:Metal block layer

[0058] 216a, 216b, 216c: components

[0059] 218: Plug

[0060] 220: Inner dielectric layer

[0061] 222: Path

[0062] 250: Absorption layer

[0063] 252: Sacrificial layer

[0064] 254: Air gap DETAILED DESCRIPTION

[0065] The present invention relates to a structure of a semiconductor device including an acoustic wave filter and a method for manufacturing the same. The acoustic wave filter is, for example, a BAW filter. The BAW filter can be manufactured on a circuit substrate using semiconductor manufacturing technology and can be adequately protected.

[0066] The following provides multiple embodiments to illustrate the present invention, but the present invention is not limited to the multiple embodiments given, and the embodiments can also be appropriately combined.

[0067] Figure 1 FIG. 1 is a schematic cross-sectional view of a semiconductor device integrated with a BAW filter according to an embodiment. Figure 1 In semiconductor manufacturing, an integrated circuit (IC) of an electronic device includes various operating circuits. These operating circuits are fabricated using semiconductor manufacturing techniques to form a circuit substrate 50, which includes silicon devices 106 and GaN devices 112 suitable for high-frequency operation. The circuits on circuit substrate 50 may be the basic circuitry of a mobile phone, for example. To meet the needs of wireless communications, a BAW acoustic wave filter 60 may be further formed on circuit substrate 50 to complete the overall circuit.

[0068] The basic structure of the circuit substrate 50 includes a buffer layer 102 and a buffer layer 110 in the middle, and a circuit including a silicon element 106 and a circuit including a GaN element 112 are formed on both sides. There can also be a shielding metal layer 100 between the buffer layer 102 and the buffer layer 110 to shield these two circuits. The silicon element 106 is, for example, an element made based on the silicon layer 104, such as a silicon transistor. The GaN element 112 is, for example, a GaN transistor, which is suitable for high-frequency operation, such as can be used in wireless communication circuits. In addition, the interconnection structure 108 and the interconnection structure 114 on both sides provide the required interconnection routing. As usual, the interconnection structure 108 and the interconnection structure 114 include a planar extending metal layer and a vertically connected plug structure to achieve the required connection routing. In addition, based on the semiconductor manufacturing process, it involves an inner dielectric layer to achieve the manufacture and support of the metal element structure.

[0069] Figure 1 The structure of the circuit substrate 50 is merely one embodiment, and the present invention is not limited to the embodiment. The actual integrated circuit of the circuit substrate 50 is determined according to actual needs and is not limited to a specific structure. The structure of the circuit substrate 50 is not limited to the embodiment.

[0070] After the circuit substrate 50 is fabricated, the acoustic wave filter circuit 60 can be further manufactured into a complete integrated circuit. The acoustic wave filter circuit 60, for example, includes a BAW filter layer 120 and the required metal layer 122, electrically connected to the circuit substrate 50 via a plug 124. The metal layer 122 is relatively thick, allowing it to simultaneously serve as a signal receiver, shield, and heat sink. The acoustic wave filter circuit 60, for example, is a passive component, facilitating subsequent application in other functional circuits.

[0071] The present invention proposes a manufacturing process for an acoustic wave filter circuit 60 based on a circuit substrate 50 . Figures 2 to 5 FIG. 1 is a schematic diagram showing a cross-sectional structure of a manufacturing process for a semiconductor device including a BAW filter unit according to an embodiment.

[0072] See Figure 2 , for example, a metal layer 200 is first formed on the circuit substrate 50. Then, the metal layer 200 is electrically connected to the circuit substrate 50 through a plug, for example, the interconnect structure 114 within the circuit substrate 50. The metal layer 200 is relatively thick. In addition to providing the wiring required for electrical connection, it can also provide electrical shielding and heat dissipation functions. The metal layer 200 also provides mechanical support strength to facilitate the subsequent formation of the acoustic wave filter. Next, a buffer layer 202, such as an oxide layer, is formed on the metal layer 200 to serve as the foundation for the structure to be formed subsequently, and also provides a flat processing surface.

[0073] Absorption layer 204 is formed on buffer layer 202. Because BAW filter units are subject to stress, absorption layer 204 can absorb mechanical stress. In one embodiment, absorption layer 204 comprises a multi-layer laminate structure 204a formed by alternating layers of two different materials. Absorption layer 204 can also comprise a plurality of air gap structures 204b, corresponding to the filter units to be formed later. Figure 2 The multi-thin layer stack structure 204 a or the air gap structure 204 b is intended to illustrate an embodiment of the detailed structure of the absorption layer 204 .

[0074] See Figure 3 Electrode layer 206, intended to serve as the bottom electrode of the filter unit, is formed on absorption layer 204. Electrode layer 206 is formed by forming an interlayer dielectric layer 208 through a patterning process. Subsequently, metal material is filled into the pattern of interlayer dielectric layer 208 through processes such as deposition and polishing to complete electrode layer 206.

[0075] A piezoelectric material layer 210 is formed on the electrode layer 206 and the interlayer dielectric layer 208. This piezoelectric material layer 210 serves as the initial material layer for the BAW filter unit to be subsequently formed. The piezoelectric material layer 210 has a predetermined thickness to achieve the BAW filtering effect. Because the piezoelectric material layer 210 needs to be patterned to form multiple filter units, the patterning process involves an etching process. A protective layer 212 may also be formed on the piezoelectric material layer 210 to provide protection during the subsequent etching process.

[0076] See Figure 4 , a patterning process is applied to the piezoelectric material layer 210 to form a plurality of piezoelectric material units 210'. The function of these piezoelectric material units 210' constitutes a BAW filter. The protective layer 214 is conformally formed on the plurality of piezoelectric material units 210' constituted by the piezoelectric material layer 210. The protective layer 214 is a harder material and at least protects the side walls of the piezoelectric material unit 210'. The protective layer 212 previously formed on the top surface of the piezoelectric material unit 210' can be removed first, or it can be retained and merged with the protective layer 214. In addition, the electrode layer 206 will have an extension area 206a, which extends out of the piezoelectric material unit constituted by the piezoelectric material layer 210. As described later, the extension area 206a is used, for example, to connect the electrode layer 206 vertically upward to other application circuits at the back end through a conductive plug.

[0077] See Figure 5, a plurality of plugs 218 are formed using a patterned inner dielectric layer 220 structure. The plugs 218 are in contact with corresponding different components, such as the electrode layer 206 or the metal layer 200, to provide vertical electrical connections. Next, a metal block layer 216 is formed above the plurality of piezoelectric material units 210', which, for example, includes a component 216a, which passes through the protective layer 214 and is disposed on the plurality of piezoelectric material units 210' of the piezoelectric material layer 210, serving as a second electrode layer. The metal block layer 216 also includes another component 216b at the same height as the aforementioned component 216a, and is at least electrically connected to the electrode layer 206. The metal block layer 216 may also include a component 216c, which is in contact with the metal layer 200 through the plug 218.

[0078] To control the temperature of the piezoelectric material unit 210', the circuit substrate 50 may also be provided with a temperature detection element and a temperature compensation element, depending on actual needs. These elements also detect and compensate the piezoelectric material unit 210' via the path 222. Here, the path 222 is merely schematically depicted; the actual path 222 may be a serpentine path, which is not particularly limited.

[0079] in front of Figure 2 The absorption layer 204 is formed, for example, by a multi-layer stacked structure 204a. In one embodiment, the absorption layer 204 may also include a structure comprising a plurality of air gap structures 204b.

[0080] Figures 6 to 8 FIG1 is a schematic diagram of a cross-sectional structure of a manufacturing process for a semiconductor device including a BAW filter according to an embodiment. Figure 6 If the absorption layer 204 is to form an air gap structure 204b, it may be formed as a dielectric layer 250. A buried sacrificial layer 252 is also formed in a predetermined region within the dielectric layer 250. The dielectric layer 250 and the sacrificial layer 252 are made of different materials, so that the sacrificial layer 252 can be removed using an etching process in a later stage of the manufacturing process to form the air gap structure.

[0081] See Figure 7 ,like Figure 3 and Figure 4 During fabrication, a protective layer 214 is formed on the piezoelectric material unit 210'. The position of the piezoelectric material unit 210' corresponds to the position of the sacrificial layer 252, thereby absorbing the pressure on the piezoelectric material unit 210'. After forming the protective layer 214 on the piezoelectric material unit 210', a small opening can be formed on the side of the piezoelectric material unit 210'. This allows the sacrificial layer 252 to be removed, for example, by etching, to form an air gap 254.

[0082] See Figure 8 ,according to Figure 5In the manufacturing process, after the subsequent formation of the metal block layer 216 is completed, the inter-layer dielectric layer 220 will seal the air gap 254. In this way, the absorption layer 250 has a structure containing the air gap 254.

[0083] The manufacturing process of the present invention allows a BAW filter to be integrated on a circuit substrate 50, for example, by directly forming the BAW filter on the circuit substrate 50 using the flat surface provided by the buffer layer 202. The BAW filter can be manufactured on the circuit substrate 50 by combining a thick metal layer and a protective layer for the filter unit.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device structure, characterized in that: include: Circuit board; a first metal block layer, disposed on the circuit substrate; a buffer layer, disposed on the first metal block layer; an absorption layer, disposed on the buffer layer; a first electrode layer, disposed on the absorption layer; a plurality of piezoelectric material units, disposed on the first electrode layer; a protective layer covering the entire side walls of the plurality of piezoelectric material units; as well as A second metal block layer, disposed above the plurality of piezoelectric material units, comprises: A first component is provided on the plurality of piezoelectric material units through the protective layer and serves as a second electrode layer; as well as The second component is at the same height as the first component and is electrically connected to at least the first electrode layer.

2. The semiconductor device structure according to claim 1, wherein: An inter-layer dielectric layer is further included to support the second metal block layer, wherein the protection layer is harder than the inter-layer dielectric layer.

3. The semiconductor device structure according to claim 1, wherein: The absorption layer is a multi-thin layer stacking structure.

4. The semiconductor device structure according to claim 1, wherein: The absorption layer includes a plurality of buried air gap regions corresponding to the plurality of piezoelectric material units.

5. The semiconductor device structure according to claim 1, wherein: The first electrode layer has a connecting portion extending from the plurality of piezoelectric material units, and a plug is connected between the connecting portion and the second component of the second metal block layer.

6. The semiconductor device structure according to claim 1, wherein: The second metal block layer further includes a third component electrically connected to the first metal block layer through a plug structure.

7. The semiconductor device structure according to claim 6, wherein: The first metal block layer is also electrically connected to the line wiring structure of the circuit substrate.

8. The semiconductor device structure according to claim 1, wherein: The circuit substrate includes a first element circuit layer and a second element circuit layer above the first element circuit layer.

9. The semiconductor device structure according to claim 8, wherein: The first element circuit layer includes silicon elements, and the second element circuit layer includes GaN elements.

10. The semiconductor device structure according to claim 9, wherein: The first component circuit layer of the circuit substrate includes a thermal detection component.

11. The semiconductor device structure according to claim 1, wherein: The first electrode layer below the plurality of piezoelectric material units is surrounded by an inner dielectric layer on the absorption layer.

12. A method for manufacturing a semiconductor device, characterized in that: include: providing a circuit substrate; forming a first metal block layer on the circuit substrate; forming a buffer layer on the first metal block layer; forming an absorption layer on the buffer layer; forming a first electrode layer on the absorption layer; forming a plurality of piezoelectric material units on the first electrode layer; forming a protective layer to cover the entire sidewalls of the plurality of piezoelectric material units; as well as forming a second metal block layer above the plurality of piezoelectric material units, the second metal block layer comprising: A first component is provided on the plurality of piezoelectric material units through the protective layer and serves as a second electrode layer; as well as The second component is at the same height as the first component and is electrically connected to at least the first electrode layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The method further includes forming an inter-layer dielectric layer to support the second metal block layer, wherein the protection layer is harder than the inter-layer dielectric layer.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The step of forming the absorption layer is to form a multi-thin layer stack structure in which multiple layers of two different materials are alternately stacked.

15. The method for manufacturing a semiconductor device according to claim 12, wherein: The steps of forming the absorption layer include: forming a dielectric layer comprising a sacrificial material layer embedded in the dielectric layer; and After forming the protective layer on the plurality of piezoelectric material units, removing the sacrificial material layer to form a plurality of air gap regions, The plurality of air gap regions correspond to the plurality of piezoelectric material units.

16. The method for manufacturing a semiconductor device according to claim 12, wherein: The first electrode layer has a connecting portion extending from the plurality of piezoelectric material units, and a plug is connected between the connecting portion and the second component of the second metal block layer.

17. The method for manufacturing a semiconductor device according to claim 12, wherein: The formed second metal block layer further includes a third component electrically connected to the first metal block layer through a plug structure.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The formed first metal block layer is also electrically connected to the line wiring structure of the circuit substrate.

19. The method for manufacturing a semiconductor device according to claim 12, wherein: The provided circuit substrate includes a first component circuit layer and a second component circuit layer above the first component circuit layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein The first element circuit layer includes silicon elements, and the second element circuit layer includes GaN elements.

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