Semiconductor Structure and Method of Forming the Same

Abstract

The present application discloses a semiconductor structure and a method for forming the same. The semiconductor structure includes: a first substrate; an application circuit layer located on the surface of the first substrate; and a functional film layer bonded to the application circuit layer. The preparation process conditions adopted during the formation of the functional film layer have a negative impact on at least some of the structures in the application circuit layer. The above semiconductor structure reduces the difficulty of integrating a single-chip integrated functional structure and an application circuit.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Currently commonly used MEMS devices generally include a MEMS structure and a read circuit, and the read circuit is used to obtain an electrical signal generated by the MEMS structure.

[0003] In the prior art, one way to form a MEMS device is to separately form a MEMS structure chip and a read circuit chip, and then form an electrical connection between the two chips through a wire bonding process. However, wire bonding will introduce relatively large signal noise, increasing the design difficulty of the MEMS structure and the read circuit. At the same time, the bonding of the two chips also makes the volume of the MEMS device chip relatively large.

[0004] In order to further improve the performance of MEMS devices and reduce the chip volume, the prior art also adopts another way, which specifically includes: integrating a MEMS structure and a read circuit on the same chip, and realizing the electrical connection between the MEMS structure and the read circuit through a metal interconnection process. In this process, both the MEMS structure and the read circuit can be fabricated using a CMOS process, but it is necessary to take into account the performance of the devices in both the MEMS structure and the read circuit at the same time, resulting in a large process development difficulty and a long cycle. And, the most prominent problem among them is that due to the performance requirements of the MEMS structure, usually its core film layer will adopt film layers such as silicon and polysilicon, which need to be formed using a high-temperature process. Therefore, it must be completed before the metal process to avoid affecting the electrical connection reliability of the metal interconnection structure. This limits the process of the read circuit and increases the difficulty of integrating the read circuit and the MEMS structure on a single chip using the COMS process.

[0005] How to reduce the difficulty of integrating a MEMS structure and a read circuit on a single chip is an urgent problem to be solved currently. Summary of the Invention

[0006] In view of this, this application provides a semiconductor structure and a method for forming the same to reduce the difficulty of integrating existing single-chip devices.

[0007] A semiconductor structure provided by this application includes: a first substrate; an application circuit layer located on the surface of the first substrate; and a functional film layer bonded to the application circuit layer, and the preparation process conditions adopted during the formation of the functional film layer have a negative impact on at least some structures in the application circuit layer.

[0008] The process adopted during the formation of the functional film layer includes a high-temperature process, and the temperature of the high-temperature process is above 450°C.

[0009] Optionally, the application circuit layer includes an application circuit and a first interconnect structure connecting the application circuit.

[0010] Optionally, functional structures are formed in the functional film layer, and a second interconnect structure connecting the functional structures and the first interconnect structure.

[0011] Optionally, the surface of the functional film layer is directly bonded to the surface of the application circuit layer.

[0012] Optionally, the functional film layer is bonded to the surface of the application circuit layer through a bonding layer.

[0013] Optionally, the functional film layer is a single-layer structure.

[0014] Optionally, the functional film layer is a multi-layer structure, and the adjacent layers are bonding interfaces or deposition interfaces.

[0015] Optionally, the functional film layer includes at least one of a single-crystalline silicon layer, a polycrystalline silicon layer, a silicon carbide layer, a germanium layer, a germanium-silicon layer, and a doped semiconductor layer.

[0016] Optionally, the functional structure includes a MEMS structure.

[0017] Optionally, the MESM structure includes at least one of a thermocouple structure, a piezoresistive structure, an acceleration sensing structure, and a silicon microphone structure.

[0018] The present application also provides a method for forming a semiconductor structure, including: providing a first substrate, forming an application circuit layer on the first substrate; providing a second substrate, a functional film layer is formed on the surface of the second substrate, and the preparation process conditions adopted in the formation process of the functional film layer have a negative impact on at least part of the structures in the application circuit layer; bonding and fixing the second substrate and the first substrate relatively, wherein the functional film layer faces the application circuit layer; removing the second substrate.

[0019] Optionally, the process adopted in the formation process of the functional film layer includes a high-temperature process, and the temperature of the high-temperature process is above 450 °C.

[0020] Optionally, the method for forming the application circuit layer includes: forming an application circuit and a first interconnect structure connecting the application circuit.

[0021] Optionally, after removing the second substrate, it further includes: at least processing the functional film layer to form a functional structure; forming a second interconnect structure connecting the functional structure and the first interconnect structure.

[0022] Optionally, the processing of the functional film layer includes at least one of ion implantation, etching, and patterning.

[0023] Optionally, the method for relatively bonding and fixing the second substrate to the first substrate includes directly bonding the surface of the functional film layer to the surface of the application circuit layer.

[0024] Optionally, the method for relatively bonding and fixing the second substrate to the first substrate includes bonding the functional film layer to the surface of the application circuit layer through a bonding layer.

[0025] Optionally, the functional film layer is a single-layer structure or a multi-layer structure.

[0026] Optionally, the functional film layer includes at least one of a single-crystalline silicon layer, a polycrystalline silicon layer, a silicon carbide layer, a germanium layer, a germanium-silicon layer, and a doped semiconductor layer.

[0027] Optionally, the functional structure includes a MEMS structure.

[0028] Optionally, the material of the first interconnect structure includes at least metal.

[0029] Optionally, it includes providing an SOI substrate, where the SOI substrate includes a bulk silicon layer, a top single-crystalline silicon layer, and a silicon oxide layer located between the top single-crystalline silicon layer and the bulk silicon layer; using the single-crystalline silicon layer as the functional film layer, and the bulk silicon layer and the silicon oxide layer as the second substrate.

[0030] In the method for forming the semiconductor structure of the present application, a functional film layer that has a process conflict with the manufacturing process of the application circuit layer is separately formed on an independent second substrate, and then bonded to the application circuit layer through a bonding process, and the second substrate is removed to complete the transfer of the functional film layer, integrating the functional film layer and the application circuit layer within the same chip. The manufacturing processes of the functional film layer and the application circuit are independent of each other, which can avoid mutual influence and reduce the difficulty of integrating the application circuit and the functional film layer on a single chip. Description of the Drawings

[0031] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following-described drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0032] Figure 1 is a schematic flow chart of the method for forming a semiconductor structure according to an embodiment of the present application;

[0033] Figures 2 to 7 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present application. Detailed Embodiments

[0034] As described in the background art, there are process compatibility problems between high-temperature processes and metal processes in integrating MEMS structures and read circuits on a single chip, resulting in high difficulty in single-chip integration. If a high-temperature process is carried out after the metal process, problems such as metal melting and aggravated electromigration will occur, leading to a reduction in the interconnect reliability of the metal. In other cases, in the process of integrating functional structures and read circuits, there will be other negative situations, for example: when doping and other treatments are required in the functional structure, a protective layer needs to be formed in the area of the read circuit, resulting in complex process steps.

[0035] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. Without conflict, the following various embodiments and their technical features can be combined with each other.

[0036] Please refer to Figure 1 , which is a schematic flowchart of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0037] The formation process of the semiconductor structure includes the following steps:

[0038] Step S101: Provide a first substrate, and form an application circuit layer on the first substrate.

[0039] Step S102: Provide a second substrate, on the surface of which a functional film layer is formed. The preparation process conditions used in the formation process of the functional film layer have a negative impact on at least some of the structures in the application circuit layer.

[0040] The negative impacts include various situations that are not conducive to integration, such as deteriorated performance, reduced reliability, decreased yield, increased process preparation difficulty, and process parameter conflicts.

[0041] In some embodiments, the process used in the formation process of the functional film layer includes a high-temperature process. The temperature of the high-temperature process is above 450°C. The high-temperature process will have a negative impact on the reliability of the electrical interconnect structure in the application circuit layer.

[0042] Step S103: Bond and fix the second substrate and the first substrate relative to each other, wherein the functional film layer faces the application circuit layer.

[0043] Step S104: Remove the second substrate.

[0044] Through the above method, the functional film layer can be transferred from the second substrate to the application circuit layer on the first substrate. In this way, the functional film layer and the application circuit layer can be formed separately, and the process flows of the two will not interfere with each other. The high-temperature process in the formation process of the functional film layer will not affect the structure within the application circuit layer. Subsequently, based on step S104, the functional film layer can be processed to form a functional structure, such as a MEMS structure, thereby realizing the monolithic integration of the MEMS structure and the read circuit.

[0045] The formation method of the semiconductor structure will be specifically described below with reference to the accompanying drawings.

[0046] Please refer to Figure 2 , provide a first substrate 100, and form an application circuit layer 110 on the first substrate 100.

[0047] The first substrate 100 can be a semiconductor substrate, such as a single-crystalline silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, etc. The formation process of the application circuit layer 110 includes forming structures such as MOS transistors, interlayer dielectric layers, conductive pillars, and interconnecting lines.

[0048] Form the application circuit layer 110 on the first substrate 100. The application circuit layer 110 includes a read circuit 111, a first interconnect structure 112, and an isolation dielectric layer 113 filled between the components of the read circuit 111 and covering the read circuit 111 and the first interconnect structure 112.

[0049] The read circuit 111 is an application-specific integrated circuit (ASIC). Those skilled in the art can design a suitable ASIC circuit according to the requirements of the semiconductor structure to be formed, which is not limited herein. The read circuit 111 at least includes MOS transistors and the interconnect structure between the transistors to form a CMOS circuit.

[0050] The first interconnect structure 112 at least includes a bottom connection layer 1121, a top connection layer 1123, and an interlayer interconnect pillar 1122 connecting the bottom connection layer 1121 and the top connection layer 1123. Figure 2 In [description], the first interconnect structure 112 is only schematic and can include multiple layers of interconnections. The specific structure and wiring method of the first interconnect structure 112 can be designed according to requirements, which is not limited herein. An electrical connection is formed between the first interconnect structure 112 and the read circuit 111 for electrically leading out the read circuit 111 and forming an electrical connection with an external structure through the top connection layer 1123.

[0051] The material of the first interconnect structure 112 at least includes a metal, such as any one or several of W, Au, Al, Cu, Ag, etc. The first interconnect structure 111 may also include non-metal conductive materials such as polysilicon, doped polysilicon, or metal silicide.

[0052] The material of the isolation dielectric layer 113 includes dielectric materials such as silicon oxide, silicon oxynitride, silicon carbonitride, etc. The isolation dielectric layer 113 is usually a multi-layer structure.

[0053] Structures such as cavities and voids may also be formed within the isolation dielectric layer 113.

[0054] Please refer to Figure 3 , a second substrate 200 is provided, and a functional film layer 210 is formed on the surface of the second substrate 200.

[0055] In this embodiment, the functional film layer 210 is a single-crystalline silicon layer on the surface layer of the SOI substrate. The second substrate 200 includes a bulk silicon layer 201 in the SOI substrate and a silicon oxide layer 202 located between the bulk silicon layer 201 and the functional film layer 210.

[0056] In other embodiments, the second substrate 200 may also be a single material layer, such as a silicon layer, glass, etc., as a carrier plate, and then the functional film layer 210 is formed on the surface of the second substrate 200 through a certain process.

[0057] The functional film layer 210 is used to form a specific functional structure, such as a MEMS structure, through the CMOS process. The functional film layer 210 includes at least one of a single-crystalline silicon layer, a polysilicon layer, a silicon carbide layer, a germanium layer, a germanium-silicon layer, and a doped semiconductor layer. The process used in the formation of the functional film layer 210 includes a high-temperature process, and the temperature of the high-temperature process is above 450°C. The high-temperature process includes a deposition process, a thermal annealing process, etc. In one embodiment, the functional film layer 210 is a single-crystalline silicon layer, and a single-crystalline silicon layer is epitaxially grown on the surface of the second substrate by vapor phase epitaxy at a temperature in the range of 700°C to 1500°C, or the single-crystalline silicon layer is deposited on the surface of the second substrate 200 by chemical vapor deposition, and the temperature of the chemical vapor deposition process is usually in the range of 600°C to 1500°C. In another embodiment, the functional film layer 210 may also be a doped semiconductor layer. After the semiconductor layer is formed by a deposition process at a high temperature, the semiconductor layer is ion-doped and annealed for activation. At this time, both the deposition process and the annealing process are high-temperature processes in the CMOS process. In other embodiments, the functional film layer 210 may also be formed by only ion implanting and annealing the second substrate 200.

[0058] In this embodiment, the functional film layer 210 is a single-layer structure. In other embodiments, the functional film layer 210 is a multi-layer structure, such as a combination of various material layers like Si / SiO2 / Si, Si / Si3N4 / Si, Si / Poly, etc. Each material layer can be sequentially stacked through a deposition process. The material and structure of the functional film layer 210 are reasonably set according to the requirements of the functional structure to be finally formed.

[0059] There is a high etching selectivity between the second substrate 200 and the functional film layer 210, which facilitates the subsequent removal of the second substrate 200.

[0060] Please refer to Figure 4 , and the second substrate 200 is fixedly bonded to the first substrate 100 relatively, wherein the functional film layer 210 faces the application circuit layer 110.

[0061] The method of fixedly bonding the second substrate 200 to the first substrate 100 relatively includes: directly bonding the surface of the functional film layer 210 to the surface of the application circuit layer 110. The surface of the functional film layer 210 is in direct contact with the surface of the application circuit layer 110. Under a certain pressure and temperature, a bonding interface is formed between the functional film layer 210 and the application circuit layer 110.

[0062] In this embodiment, the functional film layer 210 is a polysilicon layer, and the surface of the application circuit layer 110 includes the surface of the isolation dielectric layer 113 and the top interconnect layer 1123. The material of the isolation dielectric layer 113 is SiO2, and the material of the top interconnect layer 1123 is Cu. The bonding between the functional film layer 210 and the application circuit layer 110 includes Si - SiO2 bonding and Si - Cu bonding. In other embodiments, the bonding interface between the functional film layer 210 and the application circuit layer 110 can also be other bonding types, and appropriate bonding pressure, temperature and other parameters can be set according to the specific bonding type.

[0063] In other embodiments, the functional film layer 210 can also be bonded to the surface of the application circuit layer 110 through a one-key lamination. The bonding layer can be a single-layer or multi-layer structure, including at least one of a metal layer and a dielectric layer. After forming the bonding layer on the surface of the functional film layer 210, the surface of the bonding layer can be bonded to the surface of the application circuit layer 110; alternatively, a bonding layer can be formed on the surface of the application circuit layer 110, and then the surface of the functional film layer 210 can be bonded to the surface of the bonding layer; or, the bonding layer includes two bonding sub-layers, and a bonding sub-layer is formed on the surfaces of the functional film layer 210 and the application circuit layer 110 respectively, and then the two bonding sub-layers are bonded to each other. Those skilled in the art can set a bonding layer made of a suitable material between the functional film layer 210 and the application circuit layer 110 according to requirements.

[0064] Please refer to Figure 5 , and remove the second substrate 200.

[0065] The second substrate 200 can be removed by a dry or wet etching process, and only the functional film layer 210 is left on the surface of the application circuit layer 110. Thus, the functional film layer 210 is transferred from the second substrate 200 to the surface of the application circuit layer 110.

[0066] Since the functional film layer 210 is not directly formed on the surface of the application circuit layer 110, the formation process of the functional film layer 210 will not affect the devices in the application circuit layer 110 and in the first substrate 100, and there will be no problem of mutual restriction between the process flows of the two, thereby reducing the formation difficulty of the application circuit layer 110 and the functional film layer 210. Moreover, the functional film layer 210 is stacked on the application circuit layer 110, which can reduce the chip area and improve the integration degree.

[0067] In other embodiments, the functional film layer 210 can also be transferred to the application circuit layer 210, and other film layers can be bonded to the surface of the functional film layer 210 through multiple bonding and stacking to form a stacked structure.

[0068] Please refer to Figure 6 , and process the functional film layer 210 (please refer to Figure 5 ) to form a functional structure 220.

[0069] In this embodiment, the functional structure 220 is a thermocouple structure, specifically including: processing the functional film layer 210 through doping and patterning processes to form a first thermocouple strip 221 and a second thermocouple strip 222. The materials of the first thermocouple strip 221 and the second thermocouple strip 222 are polysilicon doped with different types. Specifically, the first thermocouple strip 221 is N-type doped polysilicon, and the second thermocouple strip 222 is P-type doped polysilicon. The first thermocouple strip 221 and the second thermocouple strip 222 can be in the form of long straight lines, arcs, or various suitable shapes.

[0070] Please refer to Figure 7 , to form a second interconnect structure 240 connecting the functional structure 220 and the first interconnect structure 112.

[0071] After forming a dielectric layer 230 covering the functional structure 220, the dielectric layer 230 is etched to form vias, and then conductive materials are filled in the vias to form interconnect posts 241, and interconnect lines 242 are formed on the surface of the dielectric layer 230. Part of the interconnect posts 241 are formed on the first thermocouple strip 221 and the second thermocouple strip 222. Through the interconnect posts 241 and interconnect lines 242, a series connection between the first thermocouple strip 221 and the second thermocouple strip 222 is achieved to form a thermopile. The second interconnect structure 240 is also connected to the first interconnect structure 112 in the application circuit layer 110 for realizing the electrical connection between the functional structure 220 and the reading circuit 111. The electrical signal generated by the functional structure 220 is transmitted to the reading circuit 111 through the second interconnect structure 240 and the first interconnect structure 112.

[0072] In other embodiments, the functional structure 220 may further include other structures, such as MEMS structures. The MEMS structures include but are not limited to at least one of thermocouple structures, piezoresistive structures, acceleration sensing structures, or silicon microphone structures, which are not limited herein. The functional film layer 210 can be processed to form by at least one of ion implantation, etching, or patterning. In addition to processing the functional film layer 210, the isolation dielectric layer 113 in the application circuit layer 110 can also be etched and other treatments according to needs to form structures such as cavities to meet the functional requirements of the functional structure 220. Those skilled in the art can, according to needs, set a sacrificial layer or other necessary structures in advance in the isolation dielectric layer 113 during the formation of the isolation dielectric layer 113.

[0073] The material of the second interconnect structure 240 at least includes metals, such as any one or several of W, Au, Al, Cu, Ag, etc. The second interconnect structure 230 is formed by a metal process, and the temperature is relatively low, which will not affect other structures.

[0074] In the above method for forming a semiconductor structure, a functional film layer that conflicts with the forming process of the application circuit layer is separately formed on an independent second substrate, and then bonded to the application circuit layer through a bonding process, and the second substrate is removed to complete the transfer of the functional film layer, and the functional film layer and the application circuit layer are integrated in the same chip. Moreover, the manufacturing processes of the functional film layer and the application circuit are independent of each other, which can avoid mutual influence and improve the reliability of the chip.

[0075] An embodiment of the present invention further provides a semiconductor structure.

[0076] Please refer to Figure 5 , which is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

[0077] The semiconductor structure includes: a first substrate 100; an application circuit layer 110 located on the surface of the first substrate 100; and a functional film layer 210 bonded and fixed to the application circuit layer 110.

[0078] The first substrate 100 may be a semiconductor substrate, such as a single crystal silicon substrate, a germanium silicon substrate, a silicon carbide substrate, etc. The application circuit layer 110 includes a read circuit 111, a first interconnect structure 112, and an isolation dielectric layer 113 filled between the components of the read circuit 111 and covering the read circuit 111 and the first interconnect structure 112. The read circuit 111 is an application specific integrated circuit (ASIC), and those skilled in the art can design a suitable ASIC circuit according to the requirements of the semiconductor structure to be formed, which is not limited herein.

[0079] The first interconnect structure 112 at least includes a bottom connection layer 1121, a top connection layer 1123, and an interlayer interconnect pillar 1122 connecting the bottom connection layer 1121 and the top connection layer 1123. The first interconnect structure 112 is electrically connected to the read circuit 111 for electrically leading out the read circuit 111 and forming an electrical connection with an external structure through the top connection layer 1123. Figure 5 The first interconnect structure 112 shown in is only schematic and may include multiple layers of interconnects. The specific structure and wiring method can be designed according to requirements, which is not limited herein. The material of the isolation dielectric layer 113 includes dielectric materials such as silicon oxide, silicon oxynitride, and silicon carbonitride. The isolation dielectric layer 113 may be a single-layer or multi-layer structure. According to needs, other device structures may also be formed in the isolation dielectric layer 110, which is not limited herein.

[0080] The functional film layer 210 includes at least one of a single crystal silicon layer, a polycrystalline silicon layer, a silicon carbide layer, a germanium layer, a germanium silicon layer, and a doped semiconductor layer. The process used in the formation process of the functional film layer includes a high-temperature process, and the temperature of the high-temperature process is above 450°C.

[0081] In this embodiment, the surface of the functional film layer 210 is directly bonded to the surface of the application circuit layer 110. In other embodiments, the functional film layer is bonded to the surface of the application circuit layer through a bonding layer.

[0082] In one embodiment, the functional film layer 210 has a single-layer structure. In other embodiments, the functional film layer 210 may also have a multi-layer structure, such as a combination of various material layers such as Si / SiO2 / Si, Si / Si3N4 / Si, Si / Poly, etc. Each material layer can be sequentially stacked by a deposition process or a bonding method. There is a deposition interface or a bonding interface between the material layers within the functional film layer 210.

[0083] After the application circuit layer 110 is formed, the functional film layer 210 is transferred onto the application circuit layer 110 through a bonding process. The process in the formation of the application circuit layer 110 is independent of the process in the formation of the functional film layer 210. The high-temperature process in the formation of the functional film layer 210 will not have an adverse effect on the devices within the application circuit layer 110. Moreover, the functional film layer 210 is stacked on the application circuit layer 110, which can reduce the chip area and improve the integration degree.

[0084] Please refer to Figure 6 , which is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.

[0085] In this embodiment, based on the structure shown in Figure 5 , the functional film layer 210 (please refer to Figure 5 ) is processed into a functional structure 220. The functional structure 220 may include a MEMS structure, including but not limited to at least one of a thermocouple structure, a piezoresistive structure, an acceleration sensing structure, or a silicon microphone structure. The functional structure 220 can be formed by processing the functional film layer 210 through processes such as ion implantation, etching, or patterning.

[0086] The semiconductor structure further includes a second interconnect structure 240. The second interconnect structure 240 connects the functional structure 220 and the first interconnect structure 112, and can transmit the electrical signals generated by the functional structure 220 to the reading circuit 111 through the second interconnect structure 230 and the first interconnect structure 112.

[0087] In this embodiment, the functional structure 220 is a thermocouple structure, including a first thermocouple strip 221 and the second thermocouple strip 222. The first thermocouple strip 221 is N-type doped polysilicon, and the second thermocouple strip 222 is P-type doped polysilicon. The first thermocouple strip 221 and the second thermocouple strip 222 can be long strip-shaped, arc-shaped or various suitable shapes.

[0088] The semiconductor structure further includes a dielectric layer 230 covering the functional structure 220. The second interconnect structure 240 includes interconnect posts 241 located in the dielectric layer 230 and interconnect lines 242 formed on the surface of the dielectric layer 240 and connected to the interconnect posts 241. Some of the interconnect posts 241 are formed on the first thermocouple strip 221 and the second thermocouple strip 222. Through the interconnect posts 241 and the interconnect lines 242, a series connection between the first thermocouple strip 221 and the second thermocouple strip 222 is achieved. Some of the interconnect posts 241 are connected to the top interconnect layer 1123 in the application circuit layer 110 to achieve an electrical connection between the functional structure 220 and the read circuit 111.

[0089] In other embodiments, according to the structural requirements of the functional structure 220, structures such as cavities and reflective layers can also be formed in the isolation dielectric layer 113 of the application circuit layer 110. There is no further limitation here, and those skilled in the art can set them according to needs.

[0090] The functional structure 220 is integrated above the application circuit layer 110 and forms an electrical connection through the interconnect structure, which improves the integration of the chip.

[0091] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the content of the specification and drawings of the present application, such as the mutual combination of technical features between embodiments, or direct or indirect application in other related technical fields, shall be included in the patent protection scope of the present application by the same token.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a first substrate, forming an application circuit layer on the first substrate, including forming an application circuit and a first interconnect structure connecting the application circuits; Providing a second substrate, on the surface of the second substrate, a functional film layer is formed, the functional film layer includes at least one of a single crystal silicon layer, a polycrystalline silicon layer, a silicon carbide layer, a germanium layer, a germanium-silicon layer, a doped semiconductor layer, and the manufacturing process used in the formation process of the functional film layer includes a high-temperature process, the temperature of the high-temperature process is above 450°C, which has a negative impact on at least part of the structure in the application circuit layer; Bonding and fixing the second substrate and the first substrate relative to each other, wherein the functional film layer faces the application circuit layer; Removing the second substrate; Processing the functional film layer to form a functional structure and a second interconnect structure connecting the functional structure and the first interconnect structure.

2. The forming method according to claim 1, characterized in that, Processing the functional film layer includes at least one of ion implantation, etching, or patterning.

3. The forming method according to claim 1, wherein The method of bonding and fixing the second substrate and the first substrate relative to each other includes: directly bonding the surface of the functional film layer to the surface of the application circuit layer.

4. The forming method according to claim 1, characterized in that, The method of bonding and fixing the second substrate and the first substrate relative to each other includes: bonding the functional film layer to the surface of the application circuit layer through a bonding layer.

5. The forming method according to claim 1, characterized in that, The functional film layer is a single-layer structure or a multi-layer structure.

6. The forming method according to claim 3, wherein The functional structure includes a MEMS structure.

7. The forming method according to claim 1, wherein The material of the first interconnect structure includes at least metal.

8. The forming method according to claim 1, characterized in that, Comprising: Providing a SOI substrate, the SOI substrate includes a bulk silicon layer, a top single crystal silicon layer, and a silicon oxide layer located between the top single crystal silicon layer and the bulk silicon layer; Using the single crystal silicon layer as the functional film layer, and the bulk silicon layer and the silicon oxide layer as the second substrate.

9. A semiconductor structure, characterized in that, Prepared by the method according to any one of claims 1 to 8, the semiconductor structure includes: A first substrate; An application circuit layer located on the surface of the first substrate; A functional film layer bonded to the application circuit layer.

10. The semiconductor structure according to claim 9, wherein The surface of the functional film layer is directly bonded to the surface of the application circuit layer.

11. The semiconductor structure according to claim 9, wherein The functional film layer is bonded to the surface of the application circuit layer through a bonding layer.

12. The semiconductor structure according to claim 9, wherein The functional film layer is a single-layer structure.

13. The semiconductor structure according to claim 9, wherein The functional film layer is a multi-layer structure, and the adjacent layers are bonding interfaces or deposition interfaces.

14. The semiconductor structure according to claim 9, wherein, The functional structure includes a MEMS structure.

15. The semiconductor structure according to claim 14, wherein, The MEMS structure includes at least one of a thermocouple structure, a pressure sensing structure, an acceleration sensing structure, or a silicon microphone structure.

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