A FIFO encapsulation structure and method for CIB protocol handshake

Abstract

The present invention relates to a FIFO encapsulation structure for CIB protocol handshake. CIB is a bus protocol for interconnecting multiple bare cores and mainly relies on three signals: valid, data and ready, wherein valid is sent by the upstream to inform the downstream whether the data on the current data bus is valid; data is a data signal sent from the upstream to the downstream; and ready is a handshake signal returned from the downstream to the upstream. The CIB protocol provides a unified standard for core-grain interconnection and communication and is the basis for building a multi-bare core integrated system. The encapsulation structure includes a standard FIFO, a state machine and a combinational logic circuit, which externally displays six signals: din, valid_up, ready_up, dout, valid_down and ready_down. The FIFO encapsulation method for CIB protocol handshake solves the problem that the standard FIFO is not suitable for CIB handshake, and provides great convenience for the system design based on the CIB protocol, especially the design of the data stream structure; the modular encapsulation method is adopted, which is conducive to reducing the amount of design code and facilitating the maintenance and update of the design.

Description

Technical Field

[0001] The present invention relates to a CIB protocol-based encapsulation technology, in particular to a CIB protocol handshake-oriented FIFO encapsulation structure and method. Background Art

[0002] With the development of digital integrated circuits, System-on-Chip (SoC), which integrates multiple functional modules onto a single silicon wafer, has become a near-essential solution for achieving high-performance systems. Manufacturers are continuously expanding the scale of SoCs to meet user performance demands. However, due to limitations in processing technology and other factors, Moore's Law (the rule that the number of transistors that can be accommodated on an integrated circuit doubles approximately every 24 months) is gradually failing. This makes the cost and development cycle of expanding the scale of integrated circuits on a single silicon wafer extremely high.

[0003] In the future, integrated circuits will develop towards multi-die integration. This involves interconnecting and assembling multiple verified, unpackaged chip components with different functions and packaging them into a single chip within the same package, forming a multi-chip module (MCM). The die that make up an MCM are called chiplets. Each chiplet within the same package can use a different process and come from a different manufacturer, significantly shortening and reducing the development cycle and difficulty. Summary of the Invention

[0004] The Chiplet Interconnect Bus (CIB) is a bus protocol for multi-chip interconnection, consisting of two parts: CIBD (CIB on Die) and CIBP (CIB on Package). The CIB protocol is based on packet switching. At the data link layer, CIB relies primarily on three signals: valid, data, and ready. "valid" is sent by the upstream link to inform the downstream link whether the data on the data bus is valid; "data" is a data signal sent from the upstream link to the downstream link; and "ready" is a handshake signal returned from the downstream link to the upstream link. When both "valid" and "ready" are high, the handshake is successful and the current data transfer is complete. The CIB protocol provides a unified standard for chiplet interconnection and communication, and is the foundation for building multi-chip integrated systems.

[0005] When building a chip interconnection system based on the CIB protocol, it is often necessary to use FIFO (First In First Out) as a data buffer. Since in the CIB bus protocol, data exists in the transmission link in the form of a flow, the premise of using FIFO as a data buffer is to ensure that the data "flows continuously". The input end of the FIFO is used to receive upstream data, and the output end is used to send the received data to the downstream, and at the same time ensure the correct handshake of the upstream and downstream. According to Xilinx's definition, common FIFOs are roughly divided into two categories: standard FIFO (Standard FIFO) and FWFT FIFO (First Word Fall Through FIFO). The input timing of the two FIFOs is the same, but the output timing is different. Figure 1 As shown in the figure, the output behavior of the FWFT FIFO is similar to that of a register. The data is available on the output bus in the next clock cycle after the input data is read in. The empty signal becomes valid only after all output data has been completely read out. Compared to the FWFT FIFO, the data output of the standard FIFO is delayed by one clock cycle, and the empty signal also transitions from invalid to valid one clock cycle earlier. Practice has proven that the FWFT FIFO is more suitable for CIB protocol handshaking than the standard FIFO. When using the FWFT FIFO as a CIB protocol data buffer, a simple combinational logic circuit is required: setting valid = ~empty and rd_en = valid&ready to achieve correct handshaking between upstream and downstream nodes.

[0006] To this end, the present invention provides a FIFO encapsulation structure for CIB protocol handshake, which includes a standard FIFO, a state machine and a combinational logic circuit, and externally displays six signals: din, valid_up, ready_up, dout, valid_down, and ready_down. Among them, din, valid_up, and ready_up are CIB signals connected to the upstream, and generate a handshake with the upstream; dout, valid_down, and ready_down are CIB signals connected to the downstream, and generate a handshake with the downstream; din serves as the data input of the encapsulation structure and is connected to the data input end of the standard FIFO; dout is sent from the data output end of the standard FIFO and serves as the data output of the encapsulation structure. Under the premise that valid is 1 and invalid is 0 by default, the full flag of the standard FIFO passes through a NOT Gate as the ready_up output of the package; the valid_up signal of the external input is ANDed with the ready_up and then serves as the wr_en (write enable) input of the standard FIFO; the state machine receives the empty flag from the standard FIFO and the ready_down signal from the outside, outputs rd_en (read enable) as the input of the standard FIFO, and outputs the valid_down signal to the outside. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0008] Figure 1 This is a schematic diagram of the output timing of the standard FIFO and FWFT FIFO;

[0009] Figure 2 This is a standard FIFO package structure diagram of the present invention;

[0010] Figure 3 It is the state transition diagram of the state machine of the present invention. DETAILED DESCRIPTION

[0011] like Figure 2As shown, this embodiment provides a FIFO encapsulation structure for CIB protocol handshake. The encapsulation structure consists of a standard FIFO, a state machine, and some combinational logic circuits, including six signals: din, valid_up, ready_up, dout, valid_down, and ready_down. din, valid_up, and ready_up are CIB signals connected to the upstream and generate a handshake with the upstream. Dout, valid_down, and ready_down are CIB signals connected to the downstream and generate a handshake with the downstream. din serves as the data input of the encapsulation body and is connected to the data input end of the standard FIFO. Dout is sent from the data output end of the standard FIFO and serves as the data output of the encapsulation body. Under the assumption that valid is 1 and invalid is 0 by default, the full flag of the standard FIFO passes through a NOT gate (NOTGate) and serves as the ready_up output of the encapsulation body. The valid_up signal from the external input is ANDed with the ready_up and serves as the wr_en (write enable) input of the standard FIFO. The state machine receives the empty flag from the standard FIFO and the ready_down signal from the outside, outputs rd_en (read enable) as the input of the standard FIFO, and outputs a valid_down signal to the outside.

[0012] The state transition diagram of the state machine is as follows Figure 3 shown.

[0013] The state setting method of the package body is as follows: the state machine maintains three states in total: IDLE, TRANS and WAIT.

[0014] The state transition method of the package body is as follows: when the system reset is released, the state machine enters the IDLE state. In the IDLE state, when its input signal empty is invalid (FIFO is not empty), it switches to the TRANS state, otherwise, it remains in the IDLE state. In the TRANS state, if empty is invalid, it remains in the TRANS state. If empty is valid (FIFO is empty), the state transition is determined according to its input signal ready: if ready is valid, it switches to the IDLE state, otherwise, it switches to the WAIT state. In the WAIT state, if empty is invalid and ready is valid, it switches to the TRANS state. Otherwise, if empty is valid and ready is valid, it switches to the IDLE state. Otherwise, it remains in the WAIT state.

[0015] The output mode of the state machine is: under the premise that valid is 1 and invalid is 0 by default, in the IDLE state, valid is invalid and rd_en is the negation of empty; in the TRANS state, valid is valid and rd_en is the negation of empty and the AND of ready; in the WAIT state, valid is valid and rd_en is equal to ready.

[0016] Although FWFT FIFO is more suitable for CIB protocol handshake, its use should be avoided in actual projects as much as possible. This is because FWFT has security risks: only when two or more data are read into the FIFO can the data be output normally. This greatly hinders the transmission of single-flit data packets and is not conducive to the scalability design of the network.

[0017] However, when using standard FIFO as the data buffer for the CIB protocol, simple combinational logic circuits are no longer sufficient to cope with the delayed output of initial data and the early transition of the empty signal, which poses an obstacle to the design of CIB systems based on standard FIFO.

[0018] To address the above issues, the present invention proposes a FIFO encapsulation method for CIB protocol handshakes. This method addresses the problem of standard FIFOs being unsuitable for CIB protocol handshakes by using a state machine encapsulation approach. This method encapsulates the standard FIFO into a data flow component that only displays CIB protocol signals and exhibits FWFT behavior, significantly facilitating the design of CIB-based systems.

[0019] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A FIFO encapsulation structure for CIB protocol handshake, characterized in that: The encapsulation structure includes a standard FIFO, a state machine and a combinational logic circuit, which externally displays six signals: din, valid_up, ready_up, dout, valid_down, and ready_down, wherein din, valid_up, and ready_up are CIB signals connected to the upstream and generate a handshake with the upstream, and dout, valid_down, and ready_down are CIB signals connected to the downstream and generate a handshake with the downstream; din is used as the data input of the encapsulation structure and is connected to the data input end of the standard FIFO, and dout is sent from the data output end of the standard FIFO and is used as the data output of the encapsulation structure; Under the premise that the default valid signal is 1 and the invalid signal is 0, the full of the standard FIFO is used as the ready_up output of the package structure after passing through a NOT gate; the external input valid_up signal is ANDed with the ready_up and then used as the wr_en input of the standard FIFO; the state machine accepts the empty from the standard FIFO and the ready_down signal from the outside, outputs rd_en as the input of the standard FIFO, and outputs the valid_down signal to the outside.

2. A FIFO encapsulation method for CIB protocol handshake, characterized in that: The state setting method of the encapsulation structure is as follows: the state machine therein maintains a total of 3 states: IDLE, TRANS and WAIT; the state transfer method of the encapsulation structure is as follows: Step S1: When the system reset is released, the state machine enters the IDLE state; Step S2: In the IDLE state, when its input signal empty is invalid and the FIFO is not empty, it switches to the TRANS state, otherwise, it remains in the IDLE state; Step S3: In the TRANS state, if empty is invalid, then keep in the TRANS state; if empty is valid and the FIFO is empty, then decide the state transition according to its input signal ready: if ready is valid, then transition to the IDLE state; otherwise, transition to the WAIT state; Step S4: In the WAIT state, if empty is invalid and ready is valid, then switch to the TRANS state; otherwise, if empty is valid and ready is valid, then switch to the IDLE state; otherwise, remain in the WAIT state; In addition, the output mode of the state machine is as follows: Step S1: Under the premise that valid is 1 and invalid is 0 by default, in the IDLE state, valid is invalid and rd_en is the negation of empty; Step S2: In the TRANS state, valid is valid, rd_en is the negation of empty and the AND of ready; in the WAIT state, valid is valid, rd_en is equal to ready.

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