Signal level conversion circuit, drive circuit, display driver, and display device

Abstract

A signal level conversion circuit, a driving circuit, a display driver, and a display device, comprising: a first level shifter, generating a voltage signal that converts the amplitude of an input voltage signal to an amplitude between a first negative power supply voltage and a first positive power supply voltage; a second level shifter, generating a first polarity voltage signal that converts the amplitude of the voltage signal to an amplitude between a reference power supply voltage and the first positive power supply voltage; a third level shifter, outputting a first polarity high voltage signal that converts the amplitude of the first polarity voltage signal to an amplitude between a second positive power supply voltage higher than the first positive power supply voltage and the reference power supply voltage; a fourth level shifter, generating a second polarity voltage signal that converts the amplitude of the voltage signal to an amplitude between the reference power supply voltage and the first negative power supply voltage; and a fifth level shifter, outputting a second polarity high voltage signal that converts the amplitude of the second polarity voltage signal to an amplitude between a second negative power supply voltage lower than the first negative power supply voltage and the reference power supply voltage.

Description

Technical Field

[0001] The present invention relates to a signal level conversion circuit, a driving circuit including the signal level conversion circuit, a display driver including the driving circuit, and a display device. The signal level conversion circuit converts an input signal into a positive polarity high voltage signal and a negative polarity high voltage signal. Background Art

[0002] Currently, liquid crystal displays (LCDs) using active matrix drive systems are used as display devices in various display devices, including televisions, monitors, personal computers, and car navigation systems. These LCDs are becoming increasingly larger and higher quality, leading to increasing demand for higher resolution and higher drive frequencies.

[0003] In a liquid crystal display, a plurality of data lines extending vertically along a two-dimensional screen and a plurality of gate lines extending horizontally along the two-dimensional screen are intersectingly arranged. Furthermore, at each intersection of these plurality of data lines and the plurality of gate lines, a pixel portion connected to the data lines and the gate lines is formed.

[0004] The liquid crystal display device includes the liquid crystal panel and a data driver that supplies grayscale data signals having analog voltage values ​​corresponding to the brightness level of each pixel to data lines in data pulses per horizontal scanning period.

[0005] To prevent degradation of the liquid crystal panel, the data driver performs polarity inversion driving, that is, alternately supplies grayscale data signals of a first polarity (positive) and a second polarity (negative) to the liquid crystal panel in units of a predetermined frame period.

[0006] As a data driver for performing such polarity inversion driving, a data driver including a drive circuit that switches and outputs a positive drive voltage and a negative drive voltage based on a 0V reference has been proposed (for example, see Patent Document 1). Figure 8 to Figure 1 0). The driving circuit described in Patent Document 1 is Figure 8 The switches SW1 to SW12 shown in the figure are switched so that the positive voltage signal (5V) is output from the output pad OUT1 (the reference Figure 8 ), switches to a state where a negative voltage signal (-5 V) is output from the output pad OUT1 (the state of FIG. 10 of the aforementioned document).

[0007] Furthermore, when performing this polarity switching, the driving circuit temporarily sets one end of each switch to 0V, as shown in Figure 9 of the aforementioned document, and then switches to the state shown in Figure 10 of the aforementioned document. This allows the normal operating voltage of each switch (transistor) to be configured using low-voltage components with a voltage range of approximately 1 / 2 of the liquid crystal drive voltage range.

[0008] [Prior art literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-102211 Summary of the Invention

[0011] [Problems to be solved by the invention]

[0012] Here, the switch SW1 described in Patent Document 1 is a switch (e.g., a complementary metal-oxide-semiconductor (CMOS) transistor switch) that passes a positive voltage signal (0V to 5V) and operates within the positive voltage range. Switch SW9 is a switch (e.g., an NMOS transistor switch) that resets the node through which the positive voltage signal passes to 0V and operates within the positive voltage range. When turned on, switch SW5 outputs a positive voltage signal (0V to 5V) to output terminal OUT1. When turned off, it blocks the negative voltage signal (0V to -5V) outputted from output terminal OUT1 from entering the positive voltage signal output circuit. Therefore, switch SW5 comprises a PMOS transistor switch. At this time, the PMOS transistor switch SW5 allows positive voltage signals (0V to 5V) to pass through, so the gate of the PMOS transistor switch SW5 must be controlled within the negative voltage range (0V to -5V) within the device's withstand voltage. Furthermore, switch SW2 is a switch (e.g., a CMOS transistor switch) that allows negative voltage signals (0V to -5V) to pass through and operates within the negative voltage range. Switch SW10 is a switch (e.g., a PMOS transistor switch) that resets the node through which negative voltage signals pass to 0V and operates within the negative voltage range. When switched on, switch SW6 outputs a negative voltage signal (0V to -5V) to output terminal OUT1. When switched off, it blocks the positive voltage signal (0V to 5V) outputted from output terminal OUT1 from entering the negative voltage signal output circuit. Therefore, switch SW6 comprises an NMOS transistor switch. In addition, the NMOS transistor switch SW6 passes a negative voltage signal (0V to -5V), and therefore the gate of the NMOS transistor switch SW6 must be controlled within the positive voltage range (0V to 5V) within the element withstand voltage.

[0013] As described above, in the drive circuit described in Patent Document 1, when a positive voltage signal is output to output terminal OUT1, switches SW1 and SW9 need to be controlled by a control signal in the positive voltage range, and switch SW5 needs to be controlled by a control signal in the negative voltage range. Furthermore, when a negative voltage signal is output to output terminal OUT1, switches SW2 and SW10 need to be controlled by a control signal in the negative voltage range, and switch SW6 needs to be controlled by a control signal in the positive voltage range.

[0014] Furthermore, in the driving circuit, in order to accurately switch the polarity, it is necessary to synchronize the timing of the control signal on the positive side and the control signal on the negative side.

[0015] However, the positive-side control signal is configured within the positive-side voltage range (0V to 5V) (positive-side control circuit), while the negative-side control signal is configured within the negative-side voltage range (0V to -5V) (negative-side control circuit). Furthermore, from a cost-effective perspective, it is not possible to use components with voltage tolerances spanning both the positive and negative polarity ranges. Furthermore, due to the circuit structure, the circuit delays of the positive-side control circuit and the negative-side control circuit may not match.

[0016] At this time, if the timing of the control signal on the positive side and the control signal on the negative side are not synchronized, then in the drive control performed by the above-mentioned drive circuit, signal noise or power consumption may increase due to the generation of through-current in the drive circuit, or the period during which one end of the switch is driven to 0V may be extended to prevent the element from exceeding the withstand voltage when the polarity is switched, resulting in limitations in coping with high drive frequencies.

[0017] Therefore, the purpose of the present invention is to provide a signal level conversion circuit, a driving circuit including the signal level conversion circuit, a display driver and a display device. The signal level conversion circuit can use a switching element with a component voltage resistance lower than the output voltage range to convert a low-voltage input voltage signal into a high-voltage signal of a first polarity and a high-voltage signal of a second polarity, and output them respectively with synchronized timing.

[0018] [Technical means to solve the problem]

[0019] The signal level conversion circuit of the present invention performs level shifting on the amplitude of an input voltage signal, and includes: a first level shifting unit, generating a voltage signal by converting the amplitude of the input voltage signal into an amplitude between a first power supply voltage and a second power supply voltage, wherein the first power supply voltage has a first polarity relative to a specified reference power supply voltage, and the second power supply voltage has a second polarity opposite to the first polarity relative to the reference power supply voltage; a second level shifting unit, generating a signal by converting the amplitude of the voltage signal into an amplitude between the reference power supply voltage and the first power supply voltage as a first polarity voltage signal; and a third level shifting unit, outputting a signal by converting the amplitude of the first polarity voltage signal into an amplitude between a third power supply voltage and the reference power supply voltage as a first polarity high voltage signal, wherein the third power supply voltage has the first polarity and a voltage difference with the reference power supply voltage is greater than the first power supply voltage. Alternatively, the signal level conversion circuit also includes: a fourth level shifter, which generates a signal by converting the amplitude of the voltage signal generated by the first level shifter into an amplitude between the reference power supply voltage and the second power supply voltage, as a second polarity voltage signal; and a fifth level shifter, which outputs a signal by converting the amplitude of the second polarity voltage signal into an amplitude between a fourth power supply voltage and the reference power supply voltage, as a high voltage signal of the second polarity, wherein the fourth power supply voltage is of the second polarity, and the voltage difference between the fourth power supply voltage and the reference power supply voltage is greater than the second power supply voltage.

[0020] Moreover, the signal level conversion circuit of the present invention performs level shifting on the amplitudes of the first input voltage signal and the second input voltage signal, and includes: a first level shifting unit, generating a first voltage signal by converting the amplitude of the first input voltage signal into an amplitude between a first power supply voltage and a second power supply voltage, wherein the first power supply voltage has a first polarity relative to a prescribed reference power supply voltage, and the second power supply voltage has a second polarity opposite to the first polarity relative to the reference power supply voltage; a second level shifting unit, generating a signal by converting the amplitude of the first voltage signal into an amplitude between the reference power supply voltage and the first power supply voltage, as a first polarity voltage signal; and a third level shifting unit, outputting a signal by converting the amplitude of the first polarity voltage signal into an amplitude between a third power supply voltage and the reference power supply voltage. signal, as a high voltage signal of a first polarity, the third power supply voltage is of the first polarity, and the voltage difference between the third power supply voltage and the reference power supply voltage is greater than the first power supply voltage; a fourth level shifter, generating a second voltage signal by converting the amplitude of the second input voltage signal into an amplitude between the first power supply voltage and the second power supply voltage; a fifth level shifter, generating a signal by converting the amplitude of the second voltage signal into an amplitude between the reference power supply voltage and the second power supply voltage, as a second polarity voltage signal; and a sixth level shifter, outputting a signal by converting the amplitude of the second polarity voltage signal into an amplitude between the fourth power supply voltage and the reference power supply voltage, as a high voltage signal of a second polarity, the fourth power supply voltage is of the second polarity, and the voltage difference between the fourth power supply voltage and the reference power supply voltage is greater than the second power supply voltage.

[0021] Moreover, the driving circuit of the present invention controls the driving timing based on a low-voltage control signal group. When driving a load, a first-polarity driving voltage signal of a high voltage with a first polarity relative to a specified reference power supply voltage is output from an output terminal, and the driving circuit includes: an output unit that receives a high-voltage input signal of a first polarity and outputs the first-polarity driving voltage signal obtained by amplifying the high-voltage input signal of the first polarity to a first node according to a high-voltage control signal of a first polarity; a first-conductivity-type transistor switch that supplies the voltage of the first node to the output terminal when in an on state and, on the other hand, blocks the connection between the first node and the output terminal when in an off state; a control unit that supplies a second-polarity high-voltage output control signal for controlling the on-off of the first-conductivity-type transistor switch to a control end of the first-conductivity-type transistor switch according to a high-voltage control signal with a second polarity relative to the reference power supply voltage; and a signal level conversion unit including a first A signal level conversion circuit and a second signal level conversion circuit, wherein the first signal level conversion circuit temporarily converts the amplitude of the first control signal of the low-voltage control signal group into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts it into an amplitude between a third power supply voltage of a first polarity whose voltage difference with the reference power supply voltage is greater than that of the first power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal of the first polarity to the first output unit, and the second signal level conversion circuit temporarily converts the amplitude of the second control signal of the low-voltage control signal group into an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts it into an amplitude between a fourth power supply voltage of a second polarity whose voltage difference with the reference power supply voltage is greater than that of the second power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal of the second polarity to the first control unit.

[0022] Moreover, the driving circuit of the present invention controls the driving timing based on a low-voltage control signal group. When driving a load, one of a first polarity driving voltage signal having a high voltage of a first polarity relative to a specified reference power supply voltage and a second polarity driving voltage signal having a high voltage of a second polarity is selected and output from an output terminal. The driving circuit includes: a first output unit, which receives a high-voltage input signal of a first polarity and outputs the first polarity driving voltage signal obtained by amplifying the high-voltage input signal of the first polarity to a first node according to a first high-voltage control signal of the first polarity; a first conductive type transistor switch, which supplies the voltage of the first node to the output terminal when in an on state and, on the other hand, blocks the connection between the first node and the output terminal when in an off state; and a first control unit, which controls the first polarity according to the first high-voltage control signal of the second polarity. a second-polarity high-voltage output control signal for controlling the on / off operation of the first-conductivity-type transistor switch being supplied to the control terminal of the first-conductivity-type transistor switch; a second output unit receiving a second-polarity high-voltage input signal and outputting a second-polarity drive voltage signal, obtained by amplifying the second-polarity high-voltage input signal, to a second node in accordance with a second-polarity high-voltage control signal; the second-conductivity-type transistor switch supplying a voltage at the second node to the output terminal when in an on state and blocking the connection between the second node and the output terminal when in an off state; and a second control unit supplying a first-polarity high-voltage output control signal for controlling the on / off operation of the second-conductivity-type transistor switch to the control terminal of the second-conductivity-type transistor switch in accordance with the second-polarity high-voltage control signal;and a signal level conversion unit, comprising a first signal level conversion circuit to a fourth signal level conversion circuit, wherein the first signal level conversion circuit temporarily converts the amplitude of the first control signal of the low-voltage control signal group into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a third power supply voltage of a first polarity whose voltage difference with the reference power supply voltage is greater than that of the first power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal of the first polarity to the first output unit, and the second signal level conversion circuit temporarily converts the amplitude of the second control signal of the low-voltage control signal group into an amplitude between the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a fourth power supply voltage of a second polarity whose voltage difference with the reference power supply voltage is greater than that of the second power supply voltage and the reference power supply voltage. The generated signal is supplied to the first control unit as a first high-voltage control signal of the second polarity. The third signal level conversion circuit temporarily converts the amplitude of the third control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts it to an amplitude between the fourth power supply voltage of the second polarity and the reference power supply voltage. The generated signal is supplied to the second output unit as a second high-voltage control signal of the second polarity. The fourth signal level conversion circuit temporarily converts the amplitude of the fourth control signal of the low-voltage control signal group to an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts it to an amplitude between the third power supply voltage of the first polarity and the reference power supply voltage. The generated signal is supplied to the second control unit as a second high-voltage control signal of the first polarity.

[0023] Furthermore, the display driver of the present invention includes: a data register latch for importing a series of pixel data pieces representing the brightness level of each pixel based on an image signal and outputting a plurality of the imported pixel data pieces; a plurality of level shift circuit groups for converting the signal levels of the plurality of pixel data pieces output from the data register latch into a positive high voltage signal and a negative high voltage signal, respectively; a decoder unit for converting the positive high voltage signal and the negative high voltage signal of each pixel data piece into a positive grayscale voltage signal and a negative grayscale voltage signal, respectively; and a drive circuit group for alternately selecting the positive grayscale voltage signal and the negative grayscale voltage signal for each output channel based on a low voltage control signal group for controlling a drive timing. The signal of the voltage signal is output as a driving voltage signal via the output terminal, and the driving circuit group includes: a signal level conversion unit, which is supplied with a driving reference power supply voltage, a low-voltage positive power supply voltage and a high-voltage positive power supply voltage with positive polarity relative to the reference power supply voltage, and a low-voltage negative power supply voltage and a high-voltage negative power supply voltage with negative polarity relative to the reference power supply voltage, and converts the voltage amplitude of the low-voltage control signal group to generate a high-voltage control signal group, and further, the driving circuit group is entirely composed of transistors whose element withstand voltage is lower than the voltage difference between the high-voltage positive power supply voltage and the high-voltage negative power supply voltage, and each driving circuit of the driving circuit group is the driving circuit of the present invention.

[0024] Furthermore, the display device of the present invention includes: the display driver of the present invention; and a liquid crystal display panel driven according to the driving voltage signal output from the output terminal of each of the output channels of the display driver.

[0025] [Effects of the Invention]

[0026] In the signal level conversion circuit of the present invention, a first level shifter first shifts the amplitude of a low-voltage input signal toward a polarity opposite to that of the input signal, thereby obtaining a voltage signal having an amplitude ranging from a positive low voltage to a negative low voltage. Next, a second level shifter converts the voltage signal having an amplitude ranging from a positive low voltage to a negative low voltage into a positive low voltage signal, and a third level shifter level-shifts the amplitude of the positive low voltage signal into a positive high voltage signal. Furthermore, a fourth level shifter converts the voltage signal having an amplitude ranging from a positive low voltage to a negative low voltage into a negative low voltage signal, and a fifth level shifter level-shifts the amplitude of the negative low voltage signal into a negative high voltage signal.

[0027] According to the above configuration, the processing time in the positive polarity signal level conversion section including the first level shift section, the second level shift section, and the third level shift section can be made equal to the processing time in the negative polarity signal level conversion section including the first level shift section, the fourth level shift section, and the fifth level shift section.

[0028] Furthermore, each of the first to fifth level shifters may use a switching element (transistor) having a withstand voltage lower than the output voltage range from a negative high voltage signal to a positive high voltage signal.

[0029] Therefore, the signal level conversion circuit according to the present invention can use a switching element with a withstand voltage lower than the output voltage range to convert a low-voltage input voltage signal into a high-voltage signal of the first polarity and a high-voltage signal of the second polarity, and output them in a synchronized timing sequence. Furthermore, even when the signal level conversion circuit according to the present invention is used to convert multiple low-voltage input voltage signals into high-voltage signals of the first polarity or high-voltage signals of the second polarity, the conversion into high-voltage signals of the first polarity or high-voltage signals of the second polarity can be achieved while maintaining the timing sequence between the multiple low-voltage input voltage signals.

[0030] Moreover, by adopting the signal level conversion circuit in a driving circuit that alternately outputs a positive polarity high voltage driving voltage signal and a negative polarity driving voltage signal from one output terminal according to a low voltage control signal, a low voltage control signal group is converted into a high voltage positive polarity and negative polarity control signal group for driving timing control, thereby realizing an area-saving driving circuit composed of transistors whose element withstand voltage is lower than the output voltage range, and being able to cope with high driving frequencies that require high-precision driving timing control. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 1 is a block diagram showing an example of the structure of a signal level conversion circuit 100 according to the first embodiment of the present invention.

[0032] Figure 2A FIG. 1 is a block diagram showing a modification 100_H of the signal level conversion circuit 100 according to the first embodiment of the present invention.

[0033] Figure 2B FIG. 1 is a block diagram showing another modified example 100_L of the signal level conversion circuit 100 according to the first embodiment of the present invention.

[0034] Figure 3 1 is a circuit diagram showing the structure of a signal level conversion circuit 100_1 according to a second embodiment of the present invention.

[0035] Figure 42 is a block diagram showing the structure of a driving circuit 200_1 according to a third embodiment of the present invention.

[0036] Figure 5 2 is a block diagram showing the structure of a driving circuit 200_2 according to a fourth embodiment of the present invention.

[0037] Figure 6 1 is a timing chart showing a control operation of the drive circuit 200_1 or the drive circuit 200_2 according to the fifth embodiment of the present invention.

[0038] Figure 7 1 is a block diagram showing the structure of a liquid crystal display device 400 as a sixth embodiment of the present invention, which includes a data driver including a signal level conversion circuit and a driving circuit of the present invention.

[0039] Figure 8 is a block diagram showing the structure of the data driver 80.

[0040] [Explanation of Symbols]

[0041] 10: First level shifter

[0042] 20: Second level shifter

[0043] 30: Third level shifter

[0044] 40: Fourth level shifter

[0045] 50: Fifth level shifter

[0046] 80: Data driver

[0047] 100, 100_H, 100_L, 100_1, 100A, 100B, 100C, 100D, 100E: Signal level conversion circuit

[0048] 100_2, 100_3: Signal level conversion unit

[0049] 200_1, 200_2: drive circuit

[0050] 400: Liquid crystal display device DETAILED DESCRIPTION

[0051] [Example 1]

[0052] Figure 1 1 is a block diagram showing an example of the structure of a signal level conversion circuit 100 according to the first embodiment of the present invention.

[0053] For example, the signal level conversion circuit 100 receives a voltage signal S1 of a first polarity (positive polarity) output by the logic circuit 9 based on the input voltage signal SS0, and a complementary signal XS1 that inverts the phase of voltage signal S1. Hereinafter, since voltage signal SS0, voltage signal S1, and voltage signal XS1 are low voltage signals for the logic circuit, they are also referred to as low voltage (LV) voltage signal SS0, LV voltage signal S1, and LV voltage signal XS1, respectively. Furthermore, the signal level conversion circuit 100 receives a supply of multiple power supply voltages (VDD2L, VDD1L, VGND, VDD1H, and VDD2H). These power supply voltages are based on a reference power supply voltage VGND, with voltages above the reference power supply voltage VGND having a first polarity (positive polarity) and voltages below the reference power supply voltage VGND having a second polarity (negative polarity), with the following magnitude relationships. Hereinafter, the reference power supply voltage VGND will be described as 0V in each embodiment.

[0054] VDD2L<VDD1L<VGND<VDD1H<VDD2H

[0055] (VDD1H-VDD1L)≤VDD2H

[0056] (VDD1H-VDD1L)≤|VDD2L|

[0057] In addition, the power supply voltage VDD1H and the power supply voltage VDD1L are also referred to as LV power supply voltages hereinafter. The power supply voltage VDD2H and the power supply voltage VDD2L are also referred to as high voltage (HV) power supply voltages because they are higher than the LV power supply voltages.

[0058] The signal level conversion circuit 100 receives an LV voltage signal S1 and its complementary signal XS1 as input, and converts the LV voltage signal S1 into a voltage signal (hereinafter referred to as an HV voltage signal) of a first polarity (positive) high voltage (VDD2H) and a second polarity (negative) high voltage (VDD2L). Regarding the breakdown voltage (typically, a breakdown voltage is used) of each component constituting the level conversion circuit 100, a breakdown voltage that satisfies the following relationship is employed, with the low-voltage components set to a breakdown voltage of VDD1M and the high-voltage components set to a breakdown voltage of VDD2M.

[0059] VDD1M≈VDD1H+Δ1

[0060] VDD1M≈|VDD1L|+Δ1

[0061] VDD2M≈VDD2H+Δ2

[0062] VDD2M≈|VDD2L|+Δ2

[0063] Δ1, Δ2 = voltage tolerance

[0064] like Figure 1 As shown, the signal level conversion circuit 100 includes a first level shifter 10 , a second level shifter 20 , a third level shifter 30 , a fourth level shifter 40 and a fifth level shifter 50 .

[0065] The first level shifter 10 converts the amplitudes (VDD1H to VGND) of the LV voltage signals S1 and XS1 to the second polarity (negative) using the reference power supply voltage VGND as a reference, converting them into voltage signals with amplitudes (VDD1L to VDD1H) that have been level-shifted. Specifically, the first level shifter 10 converts the LV voltage signals S1 and XS1 into voltage signals S2H (VDD1L, VDD1H) of the first polarity (positive) and HV voltage signals S2L of the second polarity (negative). The first level shifter 10 supplies voltage signal S2H to the second level shifter 20 and voltage signal S2L to the fourth level shifter 40.

[0066] The second level shifter 20 performs level shifting on the amplitude (VDD1L to VDD1H) of the voltage signal S2H supplied from the first level shifter 10 using the reference power supply voltage VGND as a reference, converting the voltage signal S3H and its complementary signal XS3H of the first polarity (positive) having an amplitude (VGND to VDD1H) into the voltage signal S3H and the complementary signal XS3H, and supplies the voltage signal S3H and the voltage signal XS3H to the third level shifter 30.

[0067] The third level shifter 30 expands the amplitude (VGND to VDD1H) of the voltage signal S3H and the voltage signal XS3H toward the first polarity (positive pole) side with the reference power supply voltage VGND as a reference, converts the amplitude (VGND to VDD2H) of the voltage signal S3H and the voltage signal XS3H into an HV voltage signal S4H of the first polarity (positive pole) and its complementary signal XS4H, which are level-shifted in this manner, and outputs one or both of the HV voltage signal S4H and the HV voltage signal XS4H.

[0068] The fourth level shifter 40 performs level shifting on the amplitude (VDD1L to VDD1H) of the voltage signal S2L supplied from the first level shifter 10 using the reference power supply voltage VGND as a reference, converting the voltage signal S3L and its complementary signal XS3L having amplitudes (VGND to VDD1L), and supplies the voltage signal S3L and the voltage signal XS3L to the fifth level shifter 50.

[0069] The fifth level shifter 50 converts the amplitudes (VGND to VDD1L) of the voltage signal S3L and the voltage signal XS3L into the second polarity (negative) side with the reference power supply voltage VGND as a reference, and converts them into the HV voltage signal S4L and its complementary signal XS4L of the second polarity (negative) with the amplitude (VGND to VDD2L) obtained by level shifting in this manner, and outputs one or both of the HV voltage signal S4L and the HV voltage signal XS4L.

[0070] so, Figure 1 In the illustrated signal level conversion circuit 100, the amplitudes of the LV voltage signals S1 and XS1, which are the targets of signal level conversion, are negatively expanded by the first level shifter 10, thereby obtaining voltage signals S2H and S2L having amplitudes ranging from VDD1H to VDD1L, from negative to positive. At this time, the voltage signals S2H and S2L supplied from the first level shifter 10 can be either in-phase or complementary signals. Voltage signal S2H is output as a voltage signal of the first polarity (positive polarity), while voltage signal S2L is output as a voltage signal of the second polarity (negative polarity).

[0071] Next, the voltage signal S2H for the first polarity (positive polarity) is converted into a first polarity (positive polarity) HV voltage signal S4H (XS4H) by means of a first polarity level shifter (20, 30) whose amplitude is level-shifted to VGND to VDD2H. Furthermore, the voltage signal S2L for the second polarity (negative polarity) is converted into a second polarity (negative polarity) HV voltage signal S4L (XS4L) by means of a second polarity level shifter (40, 50) whose amplitude is level-shifted to VGND to VDD2L.

[0072] Importantly, the signal level conversion circuit 100 converts the low voltage input voltage signal into a high voltage signal of the first polarity and a high voltage signal of the second polarity through the following first to fifth level shifting sections. That is, the first level shifting section (10) generates voltage signals (S2H, S2L) by converting the amplitude of the input voltage signal (S1, XS1) to an amplitude between a negative first negative power supply voltage (VDD1L) and a positive first positive power supply voltage (VDD1H). The second level shifting section (20) generates a signal as a first polarity voltage signal (S3H, XS3H) by converting the amplitude of the voltage signal (S2H) to an amplitude between a predetermined reference power supply voltage (VGND) and a first positive power supply voltage (VDD1H). The third level shifter (30) outputs a signal obtained by converting the amplitude of the first polarity voltage signal (S3H, XS3H) into an amplitude between a second positive power supply voltage (VDD2H) higher than the first positive power supply voltage (VDD1H) and a reference voltage as a first polarity high voltage signal (S4H, XS4H). The fourth level shifter (40) generates a signal obtained by converting the amplitude of the voltage signal (S2L) into an amplitude between a reference power supply voltage (VGND) and a first negative power supply voltage (VDD1L) as a second polarity voltage signal (S3L, XS3L). The fifth level shifter (50) outputs a signal obtained by converting the amplitude of the second polarity voltage signal (S3L, XS3L) into an amplitude between a second negative power supply voltage (VDD2L) lower than the first negative power supply voltage (VDD1L) and the reference power supply voltage as a second polarity high voltage signal (S4L, XS4L). In this way, the signal level conversion circuit 100 temporarily converts the low voltage input voltage signal into voltage signals S2H and S2L having amplitudes between VDD1L and VDD1H from the negative pole to the positive pole in the first level shifter (10), and includes level shifters (20, 30, 40, 50) that symmetrically expand the amplitudes of the voltage signals S2H and S2L toward the positive pole and the negative pole, respectively, relative to the reference power supply voltage VGND.

[0073] With the above configuration, the signal level conversion circuit 100 can synchronize the amplitude conversion processing time (timing) of the first polarity high voltage signals (S4H, XS4H) and the second polarity high voltage signals (S4L, XS4L), which are amplitude-expanded signals of the low voltage signals (S1, XS1). Furthermore, fluctuations in the amplitude conversion processing time (timing) can be suppressed due to variations in the characteristics of the components constituting the signal level conversion circuit 100, such as the manufacturing process and ambient temperature. Furthermore, the positive-side power supply voltage VDD1H and the negative-side power supply voltage VDD1L are preferably approximately the same voltage difference from the reference power supply voltage VGND. Furthermore, the positive-side power supply voltage VDD2H and the negative-side power supply voltage VDD2L are also preferably approximately the same voltage difference from the reference power supply voltage VGND.

[0074] Furthermore, the first to fifth level shifters 10 to 50 can each be composed of transistors having a withstand voltage lower than the power supply voltage range (VDD2L to VDD2H) from the negative high voltage signal (S4L) to the positive high voltage signal (S4H) (for example, approximately 1 / 2 of the power supply voltage range (VDD2L to VDD2H) from the positive to negative polarity).

[0075] Therefore, according to Figure 1 The signal level conversion circuit 100 shown can use transistors with a component voltage resistance lower than the output voltage range to convert the LV voltage signal S1 into a first polarity (positive) HV voltage signal S4H and a second polarity (negative) HV voltage signal S4L, and output them respectively in a synchronized timing.

[0076] also, Figure 1 , an example of a configuration in which the first level shifter 10 , the third level shifter 30 , and the fifth level shifter 50 receive two complementary signals and perform amplitude conversion is shown. However, a configuration in which only one of the two signals is received may be adopted.

[0077] In addition, you can also Figure 1 The first polarity level shifter (20, 30) or the second polarity level shifter (40, 50) shown is provided with a function of adjusting the output timing of both.

[0078] also, Figure 1While the illustrated signal level conversion circuit 100 uses a single LV voltage signal S1 (XS1) as the target for signal level conversion, this circuit can also be expanded to include two or more LV voltage signals, each of which is converted into a first polarity (positive) and a second polarity (negative) high voltage signal. By using the signal level conversion circuit 100 to generate high voltage signal groups of first and second polarities, amplitude expansion of multiple different low voltage signals can be achieved. This can also mitigate the effects of fluctuations in component characteristics due to factors such as manufacturing processes and ambient temperature, ensuring that the amplitude conversion processing time (timing) is consistent between polarities and between high voltage signal groups.

[0079] Furthermore, if necessary, the first level shifter 10 may include a logic circuit that generates a control signal for synchronously controlling the first polarity level shifter (20, 30) and the second polarity level shifter (40, 50). Furthermore, in order to cope with excessive element characteristic variations, the signal level conversion circuit 100 may include a function for correcting timing variations between the HV voltage signal S4H and the HV voltage signal S4L using a control signal from outside the signal level conversion circuit 100.

[0080] Moreover, Figure 1 A modified example of the signal level conversion circuit 100 is shown in FIG. Figure 2A and Figure 2B . Figure 2A For Figure 1 The signal level conversion circuit 100_H is obtained by removing the fourth level shifter 40 and the fifth level shifter 50 . Figure 2A The signal level conversion circuit 100_H converts the low voltage signal S1 and the voltage signal XS1 into a high voltage signal S4H (XS4H) of the first polarity (positive). Figure 2B For Figure 1 The signal level conversion circuit 100_L that performs the second level conversion and the third level shift unit 30 is removed. Figure 2B The signal level conversion circuit 100_L converts the low voltage signals S1 and XS1 into high voltage signals S4L (XS4L) of the second polarity (negative polarity).

[0081] Figure 2A and Figure 2BThe signal level conversion circuits 100_H and 100_L can be used to expand the amplitude of a low-voltage voltage signal to only one of the positive and negative polarities. When generating multiple high-voltage signal groups (e.g., timing control signal groups) for each polarity from multiple different low-voltage voltage signal groups, the signal level conversion circuits 100, 100_H, and 100_L can be used to generate multiple high-voltage signal groups. This allows the generation of high-voltage signal groups with expanded amplitudes while maintaining the timing between the multiple different low-voltage voltage signal groups. The high-voltage signal groups of the first and second polarities generated in this manner can suppress the effects of fluctuations in device characteristics, ensuring that the amplitude conversion processing time (timing) is consistent between polarities and between high-voltage signal groups.

[0082] [Example 2]

[0083] Figure 3 1 is a circuit diagram showing the structure of a signal level conversion circuit 100_1 according to a second embodiment of the present invention.

[0084] Figure 3 express Figure 1 Specific circuit examples of the first level shifter 10, the second level shifter 20, the third level shifter 30, the fourth level shifter 40, and the fifth level shifter 50 of the signal level conversion circuit 100 are shown. Figure 3 For convenience, the structure of generating a HV voltage signal (S4H, XS4H) of a first polarity (positive polarity) and a HV voltage signal (S4L, XS4L) of a second polarity (negative polarity) for one LV voltage signal SS0 is shown.

[0085] Figure 3 In the example, the logic circuit 9 includes an inverter I1 that inverts the logic level of the LV voltage signal SS0 and outputs it as the LV voltage signal S1. The first level shifter 10 of the signal level conversion circuit 100_1 receives the LV voltage signal S1 and its complementary signal XS1 (= SS0) output from the inverter I1. Figure 3 The logic circuit 9 has a configuration of only the inverter I1 for the sake of convenience, but may have any configuration that outputs the LV voltage signal S1 or the LV voltage signal XS1.

[0086] The first level shifter 10 includes PMOS transistors Q1 and Q2 receiving a first polarity (positive) power supply voltage VDD1H at their respective sources, and NMOS transistors Q3 and Q4 receiving a negative polarity power supply voltage VDD1L at their respective sources.

[0087] The drain of PMOS transistor Q1 is connected to the drain of NMOS transistor Q3 and the gate of NMOS transistor Q4. The gate of PMOS transistor Q1 is supplied with LV voltage signal S1 output from logic circuit 9. The drain of PMOS transistor Q2 is connected to the drain of NMOS transistor Q4 and the gate of NMOS transistor Q3. The gate of PMOS transistor Q2 is supplied with LV voltage signal XS1.

[0088] According to the above configuration, the first level shifter 10 outputs the signal generated at the connection point between the drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q4 as the negative voltage signal S2L. Furthermore, the first level shifter 10 outputs the signal generated at the connection point between the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q3, that is, a complementary signal with the phase of the voltage signal S2L inverted, as the voltage signal S2H. Furthermore, the voltage signals S2L and S2H do not necessarily need to be complementary signals. For example, either the signal generated at the connection point between the drain of the PMOS transistor Q2 and the drain of the NMOS transistor Q4, or the signal generated at the connection point between the drain of the PMOS transistor Q1 and the drain of the NMOS transistor Q3, can be output as the common voltage signal S2L or the voltage signal S2H.

[0089] The second level shifter 20 includes an inverter I2 and an inverter I3 connected in series. The inverters I2 and I3 receive a power supply voltage VDD1H of a first polarity (positive polarity) and a reference power supply voltage VGND.

[0090] Inverter I2 receives voltage signal S2H and, when voltage signal S2H represents power supply voltage VDD1H of the first polarity (positive polarity), outputs a signal representing reference power supply voltage VGND. On the other hand, when voltage signal S2H represents power supply voltage VDD1L of the second polarity (negative polarity), inverter I2 outputs a signal representing power supply voltage VDD1H of the first polarity (positive polarity). Inverter I2 supplies the signal output as described above to inverter I3 and third level shifter 30 as voltage signal S3H. Inverter I3 supplies a complementary signal, obtained by inverting the phase of voltage signal S3H, to third level shifter 30 as voltage signal XS3H.

[0091] The fourth level shifter 40 includes an inverter I4 and an inverter I5 connected in series. The inverters I4 and I5 receive a reference power supply voltage VGND and a power supply voltage VDD1L of the second polarity (negative polarity).

[0092] Inverter I4 receives voltage signal S2L and, when voltage signal S2L represents power supply voltage VDD1H of first polarity (positive polarity), outputs a signal representing power supply voltage VDD1L of second polarity (negative polarity). Furthermore, when voltage signal S2L represents power supply voltage VDD1L of second polarity (negative polarity), inverter I4 outputs a signal representing reference power supply voltage VGND. Inverter I4 supplies the signal output as described above to inverter I5 and fifth level shifter 50 as voltage signal XS3L. Inverter I5 supplies a complementary signal, obtained by inverting the phase of voltage signal XS3L, to fifth level shifter 50 as voltage signal S3L.

[0093] The third level shifter 30 includes a PMOS transistor Q5 and a PMOS transistor Q6 receiving a first polarity (positive) power supply voltage VDD2H at their respective sources, and an NMOS transistor Q7 and an NMOS transistor Q8 receiving a reference power supply voltage VGND at their respective sources.

[0094] The drain of PMOS transistor Q5 is connected to the gate of PMOS transistor Q6 and the drain of NMOS transistor Q7. The drain of PMOS transistor Q6 is connected to the gate of PMOS transistor Q5 and the drain of NMOS transistor Q8. The gate of NMOS transistor Q7 is supplied with voltage signal XS3H output from second level shifter 20. The gate of NMOS transistor Q8 is supplied with voltage signal S3H output from second level shifter 20.

[0095] According to the above configuration, the third level shifter 30 outputs the signal generated at the connection point between the drain of the PMOS transistor Q6 and the drain of the NMOS transistor Q8 as the HV voltage signal S4H of the first polarity (positive polarity). Furthermore, the third level shifter 30 outputs the signal generated at the connection point between the drain of the PMOS transistor Q5 and the drain of the NMOS transistor Q7 as the HV voltage signal XS4H of the first polarity (positive polarity) by inverting the phase of the HV voltage signal S4H.

[0096] The fifth level shifter 50 includes PMOS transistors Q9 and Q10 receiving the reference power supply voltage VGND at their respective sources, and NMOS transistors Q11 and Q12 receiving the second polarity (negative) power supply voltage VDD2L at their respective sources.

[0097] The drain of the PMOS transistor Q9 is connected to the gate of the NMOS transistor Q12 and the drain of the NMOS transistor Q11, respectively. The drain of the PMOS transistor Q10 is connected to the gate of the NMOS transistor Q11 and the drain of the NMOS transistor Q12, respectively. The gate of the NMOS transistor Q9 is supplied with the voltage signal S3L output from the fourth level shifter 40. The gate of the NMOS transistor Q10 is supplied with the voltage signal XS3L output from the fourth level shifter 40.

[0098] According to the above configuration, the fifth level shifter 50 outputs the signal generated at the connection point between the drain of the PMOS transistor Q10 and the drain of the NMOS transistor Q12 as the HV voltage signal S4L of the second polarity (negative). Furthermore, the fifth level shifter 50 outputs the signal generated at the connection point between the drain of the PMOS transistor Q9 and the drain of the NMOS transistor Q11 as the HV voltage signal XS4L of the second polarity (negative) by inverting the phase of the HV voltage signal S4L.

[0099] This configuration suppresses timing variations in the HV voltage signals between polarities due to variations in the characteristics of the NMOS and PMOS transistors that comprise each level shifter, or changes in temperature conditions. Consequently, the LV voltage signals S1 and XS1 can be converted into HV voltage signals (S4H and XS4H) of a first polarity (positive polarity) and HV voltage signals (S4L and XS4L) of a second polarity (negative polarity), and outputted at synchronized timing.

[0100] also, Figure 3 In the signal level conversion circuit 100_1 shown, the first level shifter 10, the third level shifter 30, and the fifth level shifter 50, which are level shifters for amplifying the voltage amplitude of the input LV voltage signal (S1, XS1), are each formed using four-element MOS transistors. However, other structures may also be used.

[0101] Furthermore, the second level shifter 20 and the fourth level shifter 40 are preferably symmetrical with respect to the reference power supply voltage VGND, and the third level shifter 30 and the fifth level shifter 50 are also preferably symmetrical with respect to the reference power supply voltage VGND. Figure 3As in the configuration example of FIG1 , the fourth level shifter 40 is preferably configured such that the power supply voltage VDD1H of the first polarity (positive polarity) supplied to the second level shifter 20 is replaced with the power supply voltage VDD1L of the second polarity (negative polarity), and the conductivity type of the transistors constituting the second level shifter 20 is replaced. Similarly, the fifth level shifter 50 is preferably configured such that the power supply voltage VDD2H of the first polarity (positive polarity) supplied to the third level shifter 30 is replaced with the power supply voltage VDD2L of the second polarity (negative polarity), and the conductivity type of the transistors constituting the fourth level shifter 40 is replaced.

[0102] This configuration suppresses timing variations in the HV voltage signals between polarities during voltage amplitude conversion. Consequently, the LV voltage signals S1 and XS1 can be converted into HV voltage signals (S4H and XS4H) of a first polarity (positive) and HV voltage signals (S4L and XS4L) of a second polarity (negative), and outputted with synchronized timing.

[0103] [Example 3]

[0104] Figure 4 2 is a block diagram showing the structure of a driving circuit 200_1 according to a third embodiment of the present invention.

[0105] The driver circuit 200_1 receives a positive high-voltage input signal VP with a positive polarity and a high voltage value (VGND to VDD2H) and a negative high-voltage input signal VN with a negative polarity and a high voltage value (VDD2L to VGND) as high-voltage input signals for driving a load. Furthermore, the driver circuit 200_1 receives a polarity switching signal POL indicating polarity switching timing and a plurality of low-voltage control signals SS for controlling output timing. The logic circuit 9 generates the LV voltage signal group (VGND to VDD1H) SA1, SB1, SC1, and SD1, as well as their respective complementary signals XSA1, XSB1, XSC1, and XSD1, required for driving and controlling the driver circuit 200_1. At timings corresponding to the LV voltage signal group, the driver circuit 200_1 alternately switches between high-voltage positive drive voltage signals VPA and negative drive voltage signals VNA, which are amplified from the positive high-voltage input signal VP and the negative high-voltage input signal VN, respectively, and outputs them from the output terminal DL1. Furthermore, the driving circuit 200_1 is composed of transistors having a withstand voltage lower than the output voltage range (VDD2L to VDD2H) of the positive driving voltage signal VPA and the negative driving voltage signal VNA outputted from the output terminal DL1 .

[0106] like Figure 4As shown, the driving circuit 200_1 includes a PMOS output switch 11 and an NMOS output switch 21 , a signal level converter 100_2 , a positive signal output section 111 , a negative signal output section 121 , a positive output SW control section 112 , and a negative output SW control section 122 .

[0107] The signal level conversion unit 100_2 includes multiple systems according to the type of control signal. Figure 1 ( Figure 3 ), Figure 2A and Figure 2B The signal level conversion circuit shown ( Figure 4 100A, 100B, 100C, and 100D in FIG. 100B ). The signal level conversion unit 100_2 is supplied with a reference power supply voltage VGND, a positive power supply voltage VDD1H, and a negative power supply voltage VDD1L. Furthermore, the signal level conversion unit 100_2 is supplied with a positive power supply voltage VDD2H having a voltage difference with respect to the reference power supply voltage VGND greater than the power supply voltage VDD1H, and a negative power supply voltage VDD2L having a voltage difference with respect to the reference power supply voltage VGND greater than the power supply voltage VDD1L.

[0108] As described above, signal level conversion circuit 100A level-shifts the amplitudes of LV voltage signals SA1 and XSA1, which are used to control timing. Specifically, signal level conversion circuit 100A temporarily converts the amplitudes of LV voltage signals SA1 and XSA1 to amplitudes between positive power supply voltage VDD1H and negative power supply voltage VDD1L, then converts them to amplitudes between positive power supply voltage VDD2H and reference power supply voltage VGND. The resulting signals are supplied as positive HV voltage signals SA4H and XSA4H to positive signal output section 111. The signal level conversion circuit 100B temporarily converts the amplitudes of the LV voltage signals SB1 and XSB1 used for timing control to amplitudes between the positive power supply voltage VDD1H and the negative power supply voltage VDD1L, then converts them to amplitudes between the negative power supply voltage VDD2L and the reference power supply voltage VGND, and supplies the generated signals as negative HV voltage signals SB4L and XSB4L to the positive output SW control unit 112. Furthermore, the signal level conversion circuit 100C temporarily converts the amplitudes of the LV voltage signals SC1 and XSC1 used for timing control to amplitudes between the positive power supply voltage VDD1H and the negative power supply voltage VDD1L, then converts them to amplitudes between the negative power supply voltage VDD2L and the reference power supply voltage VGND, and supplies the generated signals as negative HV voltage signals SC4L and XSC4L to the negative signal output unit 121. Furthermore, the signal level conversion circuit 100D temporarily converts the amplitudes of the LV voltage signals SD1 and XSD1 used for timing control into amplitudes between the positive polarity power supply voltage VDD1H and the negative polarity power supply voltage VDD1L, and then converts the amplitudes into amplitudes between the positive polarity power supply voltage VDD2H and the reference power supply voltage VGND, and supplies the generated signals to the negative polarity output SW control unit 122.

[0109] also, Figure 4 In the signal level conversion unit 100_2, the signal level conversion circuits 100A to 100D are signal level conversion circuits for converting LV voltage signals into positive or negative HV voltage signals. For example, the signal level conversion circuits 100A and 100D are applicable to Figure 2A The structure 100_H, the signal level conversion circuit 100B and the signal level conversion circuit 100C are applicable Figure 2B Structure 100_L.

[0110] The positive signal output unit 111 receives the first polarity (positive) HV power supply voltage VDD2H and the reference power supply voltage VGND, and operates within the positive polarity HV voltage range (VGND to VDD2H). Based on the control timing of one or both of the first polarity (positive) HV voltage signal SA4H and the HV voltage signal XSA4H, the positive signal output unit 111 supplies the positive drive voltage signal VPA, which is obtained by amplifying the positive high voltage input signal VP, to the source of the PMOS output switch 11, which is a PMOS transistor, via node Ns11.

[0111] The positive output SW control unit 112 receives the second polarity (negative) HV power supply voltage VDD2L and the reference power supply voltage VGND, and operates within the negative polarity HV voltage range (VDD2L to VGND). Based on the control timing of one or both of the second polarity (negative) HV voltage signal SB4L and the HV voltage signal XSB4L, the positive output SW control unit 112 generates a negative polarity high voltage output control signal GP of at least two values ​​(e.g., VGND and VDD1L) capable of controlling the on / off of the PMOS output switch 11 within a specified device withstand voltage in response to the positive drive voltage signal VPA. The signal is then supplied to the gate of the PMOS output switch 11.

[0112] The PMOS output switch 11 is a PMOS transistor with its drain connected to the output terminal DL1. The PMOS output switch 11 is set to an on or off state based on a positive drive voltage signal VPA supplied to its source and a negative high-voltage output control signal GP received at its gate. When in the on state, the PMOS output switch 11 outputs the positive drive voltage signal VPA supplied by the positive signal output unit 111 to the output terminal DL1. Furthermore, the drain, gate, and source (and back gate) of the PMOS output switch 11 are controlled within a voltage difference below the device's withstand voltage.

[0113] The negative signal output unit 121 receives the second polarity (negative) HV power supply voltage VDD2L and the reference power supply voltage VGND, and operates within the negative polarity HV voltage range (VDD2L-VGND). Based on the control timing of one or both of the second polarity (negative) HV voltage signal SC4L and the HV voltage signal XSC4L, the negative signal output unit 121 supplies a negative drive voltage signal VNA, which is obtained by amplifying the negative high voltage input signal VN, to the source of the NMOS output switch 21 via node Ns21.

[0114] The negative output SW control unit 122 receives the first polarity (positive) HV power supply voltage VDD2H and the reference power supply voltage VGND, and operates within the positive polarity HV voltage range (VGND to VDD2H). Based on the control timing of one or both of the first polarity (positive) HV voltage signal SD4H and the HV voltage signal XSD4H, the negative output SW control unit 122 generates a positive polarity high voltage output control signal GN of at least two values ​​(e.g., VGND and VDD1H) capable of controlling the on / off of the NMOS output switch 21 within the specified device withstand voltage in response to the negative drive voltage signal VPA, and supplies the signal to the gate of the NMOS output switch 21.

[0115] The NMOS output switch 21 is an NMOS transistor with its drain connected to the output terminal DL1. The NMOS output switch 21 is set to an on or off state based on the negative drive voltage signal VNA supplied to its source and the positive high-voltage output control signal GN received at its gate. When in the on state, the NMOS output switch 21 outputs the negative drive voltage signal VNA supplied by the negative signal output unit 121 to the output terminal DL1. Furthermore, the drain, gate, and source (and back gate) of the NMOS output switch 21 are controlled within a voltage difference below the device's withstand voltage.

[0116] With this configuration, in driver circuit 200_1, the polarity switching of the drive voltage signals to output terminal DL1, performed by the positive signal output unit 111, the negative signal output unit 121, the positive output SW control unit 112, and the negative output SW control unit 122, is controlled by the HV voltage signal group (SA1, SB1, SC1, SD1, and their respective complementary signals XSA1, XSB1, XSC1, and XSD1) from signal level conversion circuit 100_2. Signal level conversion circuit 100_2 can output the HV voltage signal group responsible for positive-side output control (SA4H, SB4H, and their respective complementary signals), the HV voltage signal group responsible for negative-side output control (SC4H, SD4H, and their respective complementary signals), and the HV voltage signal groups between the positive and negative electrodes in synchronized timing.

[0117] Therefore, according to the driver circuit 200_1, which also includes the signal level conversion circuit 100_2 and utilizes transistors with a withstand voltage lower than the output voltage range (VDD2L-VDD2H), drive timing variations within and between polarities are suppressed. High-precision drive timing control is used to alternately switch and output the negative drive voltage signal VNA and the positive drive voltage signal VPA to the capacitive load connected to the output terminal DL1. This suppresses shoot-through current and signal noise caused by drive timing variations, making it possible to cope with high drive frequencies.

[0118] Hereinafter, detailed operations of the positive output SW control unit 112 that performs on-off control of the PMOS output switch 11 and the negative output SW control unit 122 that performs on-off control of the NMOS output switch 21 will be described.

[0119] When the PMOS output switch 11 outputs the positive polarity drive voltage signal VPA having a voltage value relatively close to the power supply voltage VDD2H to the output terminal DL1, the positive polarity output SW control unit 112 supplies the high voltage output control signal GP having the negative polarity of the reference power supply voltage VGND to the gate of the PMOS output switch 11. Furthermore, when the PMOS output switch 11 outputs the positive polarity drive voltage signal VPA having a voltage value relatively close to the reference power supply voltage VGND to the output terminal DL1, the positive polarity output SW control unit 112 supplies the high voltage output control signal GP having a negative polarity, which is an intermediate voltage between the reference power supply voltage VGND and the negative polarity HV power supply voltage VDD2L, to the gate of the PMOS output switch 11. Specifically, the positive output SW control unit 112 switches the voltage value of the negative high-voltage output control signal GP using at least two voltages based on the voltage value of the positive drive voltage signal VPA output to the output terminal DL1, in order to control the gate voltage so that the PMOS output switch 11 can be turned on within a device breakdown voltage lower than the output voltage range (VDD2L-VDD2H). Similarly, the negative output SW control unit 122 switches the voltage value of the positive high-voltage output control signal GN using at least two voltages based on the voltage value of the negative drive voltage signal VNA output to the output terminal DL1, in order to control the gate voltage so that the NMOS output switch 21 can be turned on within a device breakdown voltage lower than the output voltage range.

[0120] In addition, the structure of the driving circuit 200_1 is not limited to Figure 4 The structure shown.

[0121] What is important is that the driving circuit 200_1 only needs to have the following first and second output parts, a first conductivity type transistor switch, a second conductivity type transistor switch, a first control part and a second control part, and a signal level conversion part including a first signal level conversion circuit to a fourth signal level conversion circuit.

[0122] That is, the first output unit (111) receives a high voltage input signal (VP) of a first polarity (positive pole), and outputs a first polarity driving voltage signal (VPA) obtained by amplifying the first polarity high voltage input signal to a first node (Ns11) according to a first high voltage control signal (SA4H, XSA4H) of the first polarity. The first conductive type transistor switch (11) supplies the voltage of the first node to the output terminal (DL1) when in the on state, and blocks the connection between the first node and the output terminal (DL1) when in the off state. The first control unit (112) supplies a second polarity high voltage output control signal (GP) for controlling the on and off of the first conductive type transistor switch to the control terminal (gate) of the first conductive type transistor switch according to a first high voltage control signal (SB4L, XSB4L) of the second polarity. The second output unit (121) receives a high voltage input signal (VN) of the second polarity and outputs a second polarity driving voltage signal (VNA) obtained by amplifying the second polarity high voltage input signal to a second node (Ns21) according to a second high voltage control signal (SC4L, XSC4L) of the second polarity. The second conductive type transistor switch (21) supplies the voltage of the second node to the output terminal (DL1) when in the on state, and blocks the connection between the second node and the output terminal when in the off state. The second control unit (122) supplies a first polarity high voltage output control signal (GN) for controlling the on and off of the second conductive type transistor switch (21) to the control terminal (gate) of the second conductive type transistor switch according to a second high voltage control signal (SD4H, XSD4H) of the first polarity.

[0123] A first signal level conversion circuit (100A) temporarily converts the amplitude of a first control signal (SA1, XSA1) of a low-voltage control signal group (SA1, SB1, SC1, SD1 and their respective complementary signals) into an amplitude between a first power supply voltage (VDD1H) of a first polarity (positive pole) and a second power supply voltage (VDD1L) of a second polarity (negative pole), and then converts the amplitude into an amplitude between a third power supply voltage (VDD2H) of a first polarity having a larger voltage difference with a reference power supply voltage (VGND) than the first power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal (SA4H, XSA4H) of a first polarity to a first output unit (111). The second signal level conversion circuit (100B) temporarily converts the amplitude of the second control signal (SB1, XSB1) of the low-voltage control signal group into an amplitude between a first power supply voltage of the first polarity and a second power supply voltage of the second polarity, and then converts the amplitude into an amplitude between a fourth power supply voltage (VDD2L) of the second polarity having a voltage difference greater than the second power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal (SB4L, XSB4L) of the second polarity to the first control unit (112). The third signal level conversion circuit (100C) temporarily converts the amplitude of the third control signal (SC1, XSC1) of the low-voltage control signal group into an amplitude between a first power supply voltage of the first polarity and a second power supply voltage of the second polarity, and then converts the amplitude into an amplitude between a fourth power supply voltage of the second polarity and the reference power supply voltage, and supplies the generated signal as a second high-voltage control signal (SC4L, XSC4L) of the second polarity to the second output unit (121). A fourth signal level conversion circuit (100D) temporarily converts the amplitude of a fourth control signal (SD1, XSD1) of a low-voltage control signal group into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a third power supply voltage of the first polarity and a reference power supply voltage, and supplies the generated signal as a second high-voltage control signal (SD4H, XSD4H) of the first polarity to the second control unit.

[0124] [Example 4]

[0125] Figure 5 2 is a block diagram showing the structure of a driving circuit 200_2 as a fourth embodiment of the present invention. Figure 5 In the driving circuit 200_2 shown in FIG. Figure 4 The positive signal output unit 111, the negative signal output unit 121, the positive output SW control unit 112, and the negative output SW control unit 122 of the driving circuit 200_1 are shown as an example of the internal circuit configuration. Figure 5 In Figure 4The LV voltage signal SB1 and the LV voltage signal SD1 are set to a common LV voltage signal SE1, Figure 5 The signal level conversion unit 100_3 includes a signal level conversion circuit 100E instead of Figure 4 The signal level conversion circuit 100B and the signal level conversion circuit 100D receive the LV voltage signal SE1 and the LV voltage signal XSE1, and convert them into positive polarity HV voltage signals SE4H and HV voltage signal XSE4H and negative polarity HV voltage signals SE4L and HV voltage signal XSE4L. The signal level conversion circuit 100E can be applied to, for example Figure 1 The signal level conversion circuit 100A, the signal level conversion circuit 100C, the PMOS output switch 11 and the NMOS output switch 21 are connected to the Figure 4 same.

[0126] like Figure 5 As shown, the positive signal output unit 111 includes an amplifier 131, a switch 132, and a switch 133. Amplifier 131 is a voltage follower operational amplifier with its inverting input terminal and output node connected. It outputs a positive drive voltage signal VPA from its output node, which is amplified by a positive high voltage input signal VP received at its non-inverting input terminal. Switch 132, for example, is comprised of a CMOS switch and is set to an on or off state based on the high voltage voltage signal SA4H and high voltage signal XSA4H supplied from the signal level conversion circuit 100A of the signal level conversion unit 100_3. When set to the on state, switch 132 connects the output node of amplifier 131 to the source of the PMOS output switch 11 via node Ns11. When set to the off state, switch 132 blocks the connection between the output node of amplifier 131 and the source of the PMOS output switch 11. The switch 133 is formed of an NMOS switch, for example, and is turned on or off according to the HV voltage signal XSA4H supplied from the signal level conversion circuit 100A. When the switch 133 is turned on, the reference power supply voltage VGND is applied to the source of the PMOS output switch 11.

[0127] The positive output SW control unit 112 includes a selector switch (hereinafter referred to as selector switch 112) that generates a negative high-voltage output control signal GP by switching between a reference power supply voltage VGND and a negative control voltage VGp. Switch 112, for example, has an inverter configuration. It switches between the reference power supply voltage VGND and the negative control voltage VGn based on the HV voltage signal SE4L (XSE4L) supplied from the signal level conversion circuit 100E of the signal level conversion unit 100_3, and supplies the generated negative high-voltage output control signal GP to the gate of the PMOS output switch 11. Alternatively, the negative control voltage VGn can be a control voltage that is supplied to multiple voltage values, including VGND, based on the positive drive voltage signal VPA, to enable the PMOS output switch 11 to be turned on or off within a specified device withstand voltage.

[0128] Figure 5 The negative signal output unit 121 shown includes an amplifier 141, a switch 142, and a switch 143. Amplifier 141 is a voltage follower operational amplifier with its inverting input terminal and output node connected. It outputs a negative drive voltage signal VNA from its output node, amplifying the negative high voltage input signal VN received at its non-inverting input terminal. Switch 142 is set to an on or off state based on the high voltage voltage signal SC4L and the high voltage voltage signal XSC4L supplied from the signal level conversion circuit 100C of the signal level conversion unit 100_3. Switch 142 is, for example, a CMOS switch. When set to the on state, it connects the output node of amplifier 141 to the source of the NMOS output switch 21 via node Ns21. When set to the off state, it blocks the connection between the output node of amplifier 141 and the source of the NMOS output switch 21. The switch 143 is formed of a PMOS switch, for example, and is turned on or off according to the HV voltage signal XS4L supplied from the signal level conversion circuit 100C. When the switch 143 is turned on, the reference power supply voltage VGND is applied to the source of the NMOS output switch 21 .

[0129] The negative output SW control unit 122 includes a switch (hereinafter referred to as switch 122) that generates a positive high-voltage output control signal GN by switching between a reference power supply voltage VGND and a positive control voltage VGp. Switch 122 has, for example, an inverter configuration. Switch 122 switches between the reference power supply voltage VGND and the positive control voltage VGp based on the HV voltage signal SE4H (XSE4H) supplied from the signal level conversion circuit 100E of the signal level conversion unit 100_3, and supplies the generated positive high-voltage output control signal GN to the gate of the NMOS output switch 21. Alternatively, the positive control voltage VGp may be a control voltage that is supplied to the gate of the NMOS output switch 21 at multiple voltage values, including VGND, based on the negative drive voltage signal VNA, allowing the NMOS output switch 21 to be turned on and off within a specified device withstand voltage.

[0130] also, Figure 5 In the positive signal output section 111 shown, the switch 132 may be provided inside the amplifier 131 . Furthermore, in the negative signal output section 112 , the switch 142 may be provided inside the amplifier 141 .

[0131] [Example 5]

[0132] Figure 6 1 is a timing chart showing a control operation of the drive circuit 200_1 or the drive circuit 200_2 according to the fifth embodiment of the present invention.

[0133] also, Figure 6 In, it means Figure 5 The illustrated diagram shows an example of the signals (SA4H, XSA4H, SC4L, XSC4L, SE4H, SE4L, GP, and GN) generated by the signal level conversion unit 100_3, the positive output SW control unit 112, and the negative output SW control unit 122 when the drive circuit 200_2 alternately outputs the positive drive voltage signal VPA and the negative drive voltage signal VNA (performing polarity inversion drive) during predetermined positive drive periods and negative drive periods. The control signals for the CMOS switches represent only the control signals supplied to the gates of the NMOS switches.

[0134] and then, Figure 6 In, it means Figure 5 The voltage V11 of the node Ns11 connected to the source of the PMOS output switch 11, the voltage V21 of the node Ns21 connected to the source of the NMOS output switch 21, and the voltage of the output terminal DL1 are shown. In addition, the positive polarity driving voltage signal VPA and the negative polarity driving voltage signal VNA may also be analog signals such as step signals or sine waves having a single or multiple voltage levels within the voltage range corresponding to each polarity.

[0135] like Figure 6 As shown, the driving period is divided into at least four periods T1 to T4 , and a switching period T1 and a switching period T3 are provided between the positive driving period T2 and the negative driving period T4 . Figure 6 , a timing chart showing the start of a switching period ( T1 ) following the previous negative electrode driving period (not shown).

[0136] Figure 6 In the switching period T1, first, according to the HV voltage signal SA4H and the HV voltage signal SC4L, the switches 132 and 142 are both turned off, and the supply of the driving voltage signal from the positive signal output unit 111 and the negative signal output unit 121 is blocked. Moreover, the switch 133 is turned on according to the HV voltage signal XSA4H having the power supply voltage VDD2H, and the voltage V11 of the node Ns11 becomes the reference power supply voltage VGND. Moreover, the switch 143 is supplied with the HV voltage signal SC4L having the power supply voltage VDD2L of the second polarity (negative), so that the switch 143 is turned on, as shown in FIG. Figure 6 As shown, the voltage V21 at node Ns21 increases from the negative drive voltage signal VNA during the previous negative drive period to the reference power supply voltage VGND. Furthermore, the switching switch 112 sets the negative high-voltage output control signal GP to the reference power supply voltage VGND based on the high-voltage voltage signal SE4L having the power supply voltage VDD2L. As a result, the gate of the PMOS output switch 11 is supplied with the high-voltage output control signal GP having the negative polarity of the reference power supply voltage VGND, turning the PMOS output switch 11 off. Furthermore, the switching switch 122 sets the positive high-voltage output control signal GN to the positive control voltage VGp based on the high-voltage voltage signal SE4H having the reference power supply voltage VGND. As a result, the gate of the NMOS output switch 21 is supplied with the high-voltage output control signal GN having the positive polarity of the control voltage VGp, turning the NMOS output switch 21 on.

[0137] Therefore, during the period T1 , the reference power supply voltage VGND, which is the voltage V21 of the node Ns21 , is applied to the output terminal DL1 via the NMOS output switch 21 .

[0138] At this time, if Figure 6 As shown, in the state of the negative driving voltage signal VNA, the voltage of the output terminal DL1 is increased toward the reference power supply voltage VGND via the NMOS output switch 21 .

[0139] Furthermore, throughout period T1, the terminals of switch 133 and changeover switch 122 are controlled between the reference power supply voltage VGND and the first polarity (positive) power supply voltage VDD2H. The terminals of PMOS output switch 11, switch 143, and changeover switch 112 are controlled between the reference power supply voltage VGND and the second polarity (negative) power supply voltage VDD2L. The drain and source of NMOS output switch 21 are controlled between the reference power supply voltage VGND and the second polarity (negative) power supply voltage VDD2L. The gate of NMOS output switch 21 is supplied with a control voltage VGp within a predetermined voltage difference (withstand voltage) that turns on the NMOS output switch 21 in response to the negative drive voltage signal VNA. The reference power supply voltage VGND supplied to node Ns21 reduces the voltage difference between the terminals of NMOS output switch 21. Therefore, the PMOS output switch 11 , NMOS output switch 21 , switch 133 , switch 143 , changeover switch 112 , and changeover switch 122 are controlled to be within a predetermined device withstand voltage range that is lower than the output voltage range ( VDD2L to VDD2H) of the output terminal DL1 .

[0140] Next, during period T2, switch 133 is supplied with an HV voltage signal XSA4H having a reference power supply voltage VGND, thereby turning switch 133 off. Furthermore, switch 143 continues to be supplied with an HV voltage signal SC4L having a power supply voltage VDD2L, thereby maintaining the on state of switch 143, and the voltage V21 at node Ns21 becomes the reference power supply voltage VGND. Furthermore, based on the HV voltage signals SA4H and SC4L, only switch 132 of switches 132 and 142 is switched on. Thus, the positive drive voltage signal VPA generated by the positive signal output unit 111 is supplied to node Ns11. Furthermore, the switching switch 112 switches the negative high voltage output control signal GP to the negative control voltage VGn based on the HV voltage signal SE4L having the reference power supply voltage VGND. As a result, the PMOS output switch 11 is turned on. Furthermore, the switch 122 switches the positive-polarity high-voltage output control signal GN to the reference power supply voltage VGND according to the HV voltage signal SE4H having the power supply voltage VDD2H. As a result, the NMOS output switch 21 is switched to the OFF state.

[0141] Therefore, during the period T2 , the positive polarity driving voltage signal VPA outputted from the positive polarity signal output unit 111 is outputted to the output terminal DL1 via the node Ns11 and the PMOS output switch 11 .

[0142] At this time, the NMOS output switch 21 is in an off state, and the electrical connection between the node Ns21 and the output terminal DL1 is blocked. Figure 6 As shown in FIG. 1 , the voltage V11 of the node Ns11 and the voltage of the output terminal DL1 are increased from the reference power supply voltage VGND to the positive drive voltage signal VPA. On the other hand, the voltage V21 of the node Ns21 is as shown in FIG. Figure 6 As shown, the state of the reference power supply voltage VGND is maintained.

[0143] Furthermore, throughout period T2, the terminals of switch 133, changeover switch 122, and NMOS output switch 21 are controlled between the reference power supply voltage VGND and the first polarity (positive) power supply voltage VDD2H. The terminals of switch 143 and changeover switch 112 are controlled between the reference power supply voltage VGND and the second polarity (negative) power supply voltage VDD2L. The drain and source of each terminal of the PMOS output switch 11 are controlled by a positive drive voltage signal VPA between the reference power supply voltage VGND and the power supply voltage VDD2H. A negative control voltage VGn within a predetermined voltage difference (withstand voltage) is applied to the gate of the PMOS output switch 11, which turns on the PMOS output switch 11 in response to the positive drive voltage signal VPA. Therefore, the PMOS output switch 11 , NMOS output switch 21 , switch 133 , switch 143 , changeover switch 112 , and changeover switch 122 are controlled to be within a predetermined device withstand voltage range that is lower than the output voltage range ( VDD2L to VDD2H) of the output terminal DL1 .

[0144] Next, in period T3, the switches 132 and 142 are both turned off by the HV voltage signal S4H and the HV voltage signal S4L, and the supply of the driving voltage signal from the positive signal output unit 111 and the negative signal output unit 121 is blocked. In addition, the switch 133 is supplied with the HV voltage signal XS4H having the power supply voltage VDD2H, and thus the switch 133 is turned on. Figure 6 As shown in FIG. 1 , the voltage V11 at the node Ns11 decreases from the positive drive voltage signal VPA to the reference power supply voltage VGND. Furthermore, the HV voltage signal XS4L having the power supply voltage VDD2L is continuously supplied to the switch 143, thereby maintaining the on state. The voltage V21 at the node Ns21 continues to be the reference power supply voltage VGND. Furthermore, the high voltage output control signal GP having the negative polarity of the control voltage VGn is continuously supplied to the gate of the PMOS output switch 11. Figure 6 As shown, the PMOS output switch 11 is kept in the on state. Moreover, according to the HV voltage signal SE4H, the positive polarity high voltage output control signal GN is kept at the reference power supply voltage VGND. As a result, Figure 6 As shown, the NMOS output switch 21 maintains an off state.

[0145] Therefore, during period T3, if Figure 6 As shown, the reference power supply voltage VGND, which is the voltage V11 of the node Ns11 , is output to the output terminal DL1 via the PMOS output switch 11 .

[0146] At this time, if Figure 6 As shown, the voltage of the output terminal DL1 , which is the positive driving voltage signal VPA, drops toward the reference power supply voltage VGND via the PMOS output switch 11 .

[0147] Furthermore, throughout period T3, although switch 133 changes from an off state to an on state, the control voltage range of each switch remains unchanged. Therefore, similarly to period T2, the PMOS output switch 11, NMOS output switch 21, switch 133, switch 143, switch 112, and switch 122 are controlled within a predetermined device withstand voltage range, which is lower than the output voltage range (VDD2L to VDD2H) of output terminal DL1.

[0148] Next, during period T4, the switch 133 continues to be supplied with the HV voltage signal XSA4H having the power supply voltage VDD2H of the first polarity (positive pole), thereby turning on the switch 133 and continuing to supply the voltage V11 of the node Ns11 with the reference power supply voltage VGND. Furthermore, the switch 143 is supplied with the HV voltage signal SC4L having the reference power supply voltage VGND, thereby turning off the switch 143. Furthermore, based on the HV voltage signal SA4H and the HV voltage signal SC4L, only the switch 142 of the switches 132 and 142 is switched to the on state. Thus, the negative polarity drive voltage signal VNA output from the negative polarity signal output unit 121 is supplied to the node Ns21. Furthermore, the switching switch 112 switches the negative polarity high voltage output control signal GP to the reference power supply voltage VGND based on the HV voltage signal SE4L having the power supply voltage VDD2L. As a result, the PMOS output switch 11 is turned off. The switch 122 switches the positive high voltage output control signal GN to the positive control voltage VGp according to the HV voltage signal SE4H having the reference power supply voltage VGND. As a result, the NMOS output switch 21 is turned on.

[0149] Therefore, in the period T4 , the negative polarity driving voltage signal VNA output from the negative polarity signal output unit 121 is output to the output terminal DL1 via the node Ns21 and the NMOS output switch 21 .

[0150] At this time, if Figure 6 As shown in FIG. 1 , the PMOS output switch 11 is in an off state, and the electrical connection between the node Ns11 and the output terminal DL1 is blocked. Figure 6As shown, the voltage V21 of the node Ns21 and the voltage of the output terminal DL1 drop from the reference power supply voltage VGND to the negative drive voltage signal VNA. On the other hand, the voltage V11 of the node Ns11 is as shown in FIG. Figure 6 As shown, the state of the reference power supply voltage VGND is maintained.

[0151] Furthermore, throughout period T4, the terminals of switch 143, changeover switch 112, and PMOS output switch 11 are controlled between the reference power supply voltage VGND and the second polarity (negative) power supply voltage VDD2L. The terminals of switch 133 and changeover switch 122 are controlled between the reference power supply voltage VGND and the first polarity (positive) power supply voltage VDD2H. The drain and source of each terminal of NMOS output switch 21 are controlled by a negative drive voltage signal VNA between the reference power supply voltage VGND and the power supply voltage VDD2L. A positive control voltage VGp within a predetermined voltage difference (withstand voltage) is applied to the gate of NMOS output switch 21, which turns on the NMOS output switch 21 in response to the negative drive voltage signal VNA. Therefore, the PMOS output switch 11 , NMOS output switch 21 , switch 133 , switch 143 , changeover switch 112 , and changeover switch 122 are controlled to be within a predetermined device withstand voltage range that is lower than the output voltage range ( VDD2L to VDD2H) of the output terminal DL1 .

[0152] also, Figure 6 In the drive control, Figure 5 The driving circuit 200_2 switches and outputs a positive polarity driving voltage signal VPA or a negative polarity driving voltage signal VNA to the output terminal DL1 in a predetermined cycle. Figure 5 In the driving circuits of the driving circuit 200_2, the driving circuits 200_2 that output driving voltage signals of different polarities at the same timing may share a portion of the circuit. Specifically, the two driving circuits 200_2 that output driving voltage signals of different polarities at the same timing may share the amplifier 131 of the positive signal output unit 111 and the amplifier 141 of the negative signal output unit 121.

[0153] [Example 6]

[0154] Figure 7 1 is a block diagram showing the structure of a liquid crystal display device 400 as a sixth embodiment of the present invention, which includes a data driver including a signal level conversion unit and a driving circuit of the present invention.

[0155] Figure 7In the figure, the display screen 20 is an active matrix liquid crystal display screen, which is formed with m (m is a natural number greater than 2) horizontal scanning lines S1 to Sm extending in the horizontal direction of the two-dimensional screen, and n (n is a natural number greater than 2) data lines D1 to Dn extending in the vertical direction of the two-dimensional screen. At each intersection of the horizontal scanning lines and the data lines, a display unit responsible for the pixel is formed. The display unit contains at least a switching element and a pixel electrode. When the switching element becomes turned on according to the scanning pulse of the horizontal scanning line, the grayscale voltage signal of the data line is applied to the pixel electrode via the switching element, and the brightness of the liquid crystal display device is controlled according to the grayscale voltage applied to the pixel electrode. In addition, Figure 7 The specific structure of the display unit is omitted.

[0156] The display control unit 65 receives a video signal VD that integrates control signals and the like, generates a timing signal based on a horizontal synchronization signal from the video signal VD, and supplies the generated timing signal to the scan driver 70. Furthermore, based on the video signal VD, the display control unit 65 supplies a polarity inversion signal POL, a start pulse, a group of control signals representing various timing signals including a clock signal CLK, and a video digital signal to the data driver 80. The video digital signal includes a series of pixel data PD indicating the brightness level of each pixel using, for example, 8-bit brightness grayscale.

[0157] The scan driver 70 sequentially applies horizontal scan pulses to the horizontal scan lines S1 to Sm of the display panel 20 at the timing indicated by the control signal supplied from the display control unit 65 .

[0158] The data driver 80 is formed as a semiconductor device such as a large-scale integrated circuit (LSI), for example. The data driver 80 converts the pixel data PD contained in the image digital signal supplied from the display control unit 65 into drive voltage signals G1 to Gn having grayscale voltages corresponding to each pixel data PD, in units of one horizontal scan line, i.e., n. Then, the data driver 80 applies the drive voltage signals G1 to Gn to the data lines D1 to Dn of the display screen 20. In addition, the scan driver 70 or the data driver 80 may be formed integrally with the display screen 20 in part or in whole. Moreover, the data driver 80 may also have the display control unit 65 built in. Furthermore, the data driver 80 may also be composed of multiple LSIs.

[0159] Figure 8 2 is a block diagram showing an example of the internal structure of the data driver 80 .

[0160] like Figure 8As shown, the data driver 80 includes a positive reference voltage generating circuit 50P, a negative reference voltage generating circuit 50N, a shift register 600, a data register latch 700, a level shift circuit group 800, a decoder unit 900, and a driver circuit group 200_4. Driver circuit group 200_4 also includes a signal level conversion unit 100_4. The shift register 600 and the data register latch 700 are each supplied with a reference power supply voltage VGND and a positive LV power supply voltage VDD1H. The decoder unit 900 is also supplied with a reference power supply voltage VGND, a positive HV power supply voltage VDD2H, and a negative HV power supply voltage VDD2L. The level shift circuit group 800 and the driver circuit group 200_4 are also supplied with a reference power supply voltage VGND, positive LV power supply voltages VDD1H and VDD2H, and negative LV power supply voltages VDD1L and VDD2L.

[0161] The shift register 600 generates a plurality of latch timing signals for selecting latches in synchronization with the clock signal CLK in response to a start pulse, and supplies the signals to the data register latch 700 .

[0162] The data register latch 700 receives the digital image signal and a group of LV control signals for controlling various timings, such as the polarity inversion signal POL. Based on the latch timing signals supplied from the shift register 600, the data register latch 700 receives multiple pixel data pieces included in the digital image signal and supplies them to the level shift circuit group 800 at the latch timings. Furthermore, the data register latch 700 alternately supplies the received pixel data pieces to the positive and negative level shift circuits included in the level shift circuit group 800 in accordance with the polarity inversion signal POL.

[0163] The level shift circuit group 800 converts the signal level of each pixel data piece based on the LV power supply voltage (VDD1H, VGND) for the logic circuit into a positive polarity HV digital signal (VGND / VDD2H) and a negative polarity HV digital signal (VDD2L / VGND), and supplies them to the plurality of positive polarity decoders 90P and the plurality of negative polarity decoders 90N included in the decoder unit 900. In addition, the level shift circuit group 800 may also include Figure 1 ( Figure 3 ), Figure 2A 、 Figure 2B Any one or a combination of the signal level conversion circuit 100 , the signal level conversion circuit 100_H, the signal level conversion circuit 100_L, and the signal level conversion circuit 100_1 may include a plurality of circuits.

[0164] The decoder unit 900 is configured, for example, by assigning a pair of positive decoders 90P and negative decoders 90N to each of two output terminals of the data driver 80. Furthermore, the order of arrangement of the positive decoders 90P and negative decoders 90N within the decoder unit 900 can be varied. For example, to reduce layout area, decoders of the same polarity can be arranged in a cluster with multiple outputs.

[0165] The positive reference voltage generating circuit 50P and the negative reference voltage generating circuit 50N generate a plurality of reference voltages having different voltage values ​​and supply them to the positive decoder 90P and the negative decoder 90N provided for the plurality of output terminals of the data driver 80 .

[0166] The positive decoder 90P and the negative decoder 90N select positive reference voltages and negative reference voltages corresponding to the positive HV digital signal and the negative HV digital signal respectively from the multiple reference voltages, and supply them to the driving circuit group 200_4 as positive grayscale voltages and negative grayscale voltages respectively.

[0167] The driving circuit group 200_4 receives the polarity inversion signal POL and the LV control signal group indicating various timings, and uses the signal level converter 100_4 to generate the HV voltage signal group for controlling the timing of each driving circuit of the driving circuit group 200_4. The signal level converter 100_4 includes the following system based on the LV control signal group: Figure 1 ( Figure 3 ), Figure 2A 、 Figure 2B The illustrated signal level conversion circuit 100, signal level conversion circuit 100_H, signal level conversion circuit 100_L, and signal level conversion circuit 100_1 may include any one or a combination of multiple signals. Each driver circuit in the driver circuit group 200_4 receives a positive grayscale voltage and a negative grayscale voltage supplied from the decoder unit 900 as a positive high voltage input signal (VP) and a negative high voltage input signal (VN), and outputs the amplified positive drive voltage signal (VPA) and negative drive voltage signal (VNA), respectively, from the output terminals of the data driver 80. In this case, the driver circuit group 200_4 receives a polarity inversion signal POL and a timing control signal as an LV control signal group in a pair of driver circuits that output drive voltage signals of different polarities (e.g., a pair of driver circuits that drive two adjacent output terminals, respectively). The driver circuit group 200_4 switches the polarity of the drive voltage signals output from each output terminal of the pair of driver circuits at a drive timing corresponding to the LV control signal group.

[0168] For example, in a driving timing corresponding to the polarity reversal signal POL and the timing control signal, the state in which a positive driving voltage signal is output from the output terminal of one of a pair of driving circuits and a negative driving voltage signal is output from the output terminal of the other is switched to a state in which a negative driving voltage signal is output from the output terminal of one of the pair of driving circuits and a positive driving voltage signal is output from the output terminal of the other.

[0169] Furthermore, the level shift circuit group 800, decoder unit 900, and driver circuit group 200_4 can each be composed of transistors with a withstand voltage lower than the positive and negative drive voltage ranges (VDD2L to VDD2H) (e.g., approximately 1 / 2 of the voltage difference |VDD2H - VDD2L|). This can reduce the driver area and achieve cost reduction.

Claims

1. A signal level conversion circuit for level shifting the amplitude of an input voltage signal, characterized in that: include: a first level shifter generating a voltage signal by converting the amplitude of the input voltage signal into an amplitude between a first power supply voltage and a second power supply voltage, wherein the first power supply voltage has a first polarity relative to a predetermined reference power supply voltage, and the second power supply voltage has a second polarity opposite to the first polarity relative to the reference power supply voltage; a second level shifter configured to generate a signal obtained by converting the amplitude of the voltage signal into an amplitude between the reference power supply voltage and the first power supply voltage, as a first polarity voltage signal; as well as a third level shifter, configured to output a signal obtained by converting the amplitude of the first polarity voltage signal to an amplitude between a third power supply voltage and the reference power supply voltage as a high voltage signal of the first polarity, wherein the third power supply voltage is of the first polarity and has a voltage difference with the reference power supply voltage greater than that of the first power supply voltage; a fourth level shifter configured to generate a signal by converting the amplitude of the voltage signal generated by the first level shifter into an amplitude between the reference power supply voltage and the second power supply voltage, as a second polarity voltage signal; as well as The fifth level shifter outputs a signal obtained by converting the amplitude of the second polarity voltage signal into an amplitude between a fourth power supply voltage and the reference power supply voltage as a high voltage signal of the second polarity. The fourth power supply voltage is of the second polarity and has a voltage difference with the reference power supply voltage that is greater than the second power supply voltage.

2. The signal level conversion circuit according to claim 1, wherein: The first level shifter is supplied with the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, receives one or both of the input voltage signal and the complementary signal of the input voltage signal, and generates a first voltage signal and a second voltage signal by converting the input voltage signal or the complementary signal of the input voltage signal to an amplitude between the first power supply voltage and the second power supply voltage. The second level shifter is supplied with the first power supply voltage and the reference power supply voltage, receives one of the first voltage signal and the second voltage signal, and generates a signal by converting the one voltage signal into a signal having an amplitude between the first power supply voltage and the reference power supply voltage as the first polarity voltage signal. The third level shifter is supplied with the third power supply voltage of the first polarity and the reference power supply voltage, receives one or both of the first polarity voltage signal and the complementary signal of the first polarity voltage signal, and generates at least one of two complementary signals that convert the first polarity voltage signal into an amplitude between the third power supply voltage and the reference power supply voltage as a high voltage signal of the first polarity.

3. The signal level conversion circuit according to claim 1, wherein: The first level shifter is supplied with the first power supply voltage of a first polarity and the second power supply voltage of a second polarity, receives one or both of the input voltage signal and the complementary signal of the input voltage signal, and generates a first voltage signal and a second voltage signal by converting the input voltage signal or the complementary signal of the input voltage signal to an amplitude between the first power supply voltage and the second power supply voltage. The second level shifter is supplied with the first power supply voltage and the reference power supply voltage, receives one of the first voltage signal and the second voltage signal, and generates a signal by converting the one voltage signal into a signal having an amplitude between the first power supply voltage and the reference power supply voltage as the first polarity voltage signal. The third level shifter is supplied with the third power supply voltage of the first polarity and the reference power supply voltage, receives one or both of the first polarity voltage signal and the complementary signal of the first polarity voltage signal, and generates at least one of two complementary signals having an amplitude between the third power supply voltage and the reference power supply voltage as the high voltage signal of the first polarity. The fourth level shifter is supplied with the second power supply voltage and the reference power supply voltage, receives the other of the first voltage signal and the second voltage signal, and generates a signal obtained by converting the other voltage signal into a signal having an amplitude between the second power supply voltage and the reference power supply voltage as the second polarity voltage signal. The fifth level shifter is supplied with the fourth power supply voltage of the second polarity and the reference power supply voltage, receives one or both of the second polarity voltage signal and the complementary signal of the second polarity voltage signal, and generates at least one of two signals that are complementary to each other and have an amplitude between the fourth power supply voltage and the reference power supply voltage, as a high voltage signal of the second polarity.

4. The signal level conversion circuit according to claim 1 or 3, characterized in that: The fourth level shifter is configured to change the first power supply voltage of the first polarity supplied to the second level shifter to the second power supply voltage of the second polarity, and to change the conductivity type of the transistors constituting the second level shifter. The fifth level shifter is configured to switch the third power supply voltage of the first polarity supplied to the third level shifter to the fourth power supply voltage of the second polarity and to switch the conductivity type of transistors constituting the third level shifter.

5. The signal level conversion circuit according to any one of claims 1 to 3, characterized in that: The transistor is composed of a transistor having a withstand voltage lower than the voltage difference between the third power supply voltage of the first polarity and the fourth power supply voltage of the second polarity.

6. A drive circuit that controls drive timing based on a low-voltage control signal group and outputs a first-polarity drive voltage signal having a high voltage with a first polarity relative to a predetermined reference power supply voltage from an output terminal when driving a load, wherein the drive circuit is characterized by comprising: an output unit receiving a high voltage input signal of a first polarity and outputting a first polarity driving voltage signal obtained by amplifying the first polarity high voltage input signal to a first node according to a high voltage control signal of a first polarity; a transistor switch of a first conductivity type, which supplies the voltage of the first node to the output terminal when in an on state, and blocks the connection between the first node and the output terminal when in an off state; a control unit that supplies a high voltage output control signal of a second polarity for controlling the on-off of the first conductive type transistor switch to a control terminal of the first conductive type transistor switch in response to a high voltage control signal of a second polarity relative to the reference power supply voltage; as well as The signal level conversion unit includes a first signal level conversion circuit and a second signal level conversion circuit. The first signal level conversion circuit temporarily converts the amplitude of the first control signal of the low-voltage control signal group into an amplitude between a first power supply voltage of a first polarity and a second power supply voltage of a second polarity, and then converts the amplitude into an amplitude between a third power supply voltage of a first polarity having a voltage difference greater than that of the first power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal of the first polarity to the output unit. The second signal level conversion circuit temporarily converts the amplitude of the second control signal of the low-voltage control signal group into an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, and then converts the amplitude into an amplitude between a fourth power supply voltage of the second polarity having a voltage difference greater than that of the second power supply voltage and the reference power supply voltage, and supplies the generated signal as a first high-voltage control signal of the second polarity to the control unit. The fourth control signal is common to the second control signal, Instead of the second signal level conversion circuit and the fourth signal level conversion circuit, the circuit includes: The fifth signal level conversion circuit temporarily converts the amplitude of the second control signal of the low-voltage control signal group into an amplitude between the first power supply voltage of the first polarity and the second power supply voltage of the second polarity, generates a first voltage signal and a second voltage signal, further converts the amplitude of the first voltage signal into an amplitude between the fourth power supply voltage of the second polarity and the reference power supply voltage, outputs the generated signal as a first high-voltage control signal of the second polarity, and converts the amplitude of the second voltage signal into an amplitude between the third power supply voltage of the first polarity and the reference power supply voltage, outputs the generated signal as a second high-voltage control signal of the first polarity.

7. The driving circuit according to claim 6, wherein: The transistor is composed of a transistor having a withstand voltage lower than the voltage difference between the third power supply voltage of the first polarity and the fourth power supply voltage of the second polarity.

8. A display driver, characterized in that: include: a data register latch for importing a series of pixel data slices representing the brightness level of each pixel based on an image signal and outputting the imported plurality of pixel data slices; a plurality of level shift circuit groups, converting the signal levels of the plurality of pixel data pieces output from the data register latch into positive polarity high voltage signals and negative polarity high voltage signals respectively; a decoder unit, configured to convert the positive high-voltage signal and the negative high-voltage signal of each pixel data slice into a positive grayscale voltage signal and a negative grayscale voltage signal, respectively; as well as The driving circuit group, based on a low-voltage control signal group for controlling driving timing, alternately selects the positive polarity grayscale voltage signal and the negative polarity grayscale voltage signal for each output channel as a driving voltage signal and outputs the signal via an output terminal. The drive circuit group includes: a signal level conversion unit, which is supplied with a drive reference power supply voltage, a low-voltage positive power supply voltage and a high-voltage positive power supply voltage with positive polarity relative to the reference power supply voltage, and a low-voltage negative power supply voltage and a high-voltage negative power supply voltage with negative polarity relative to the reference power supply voltage, and converts the voltage amplitude of the low-voltage control signal group to generate a high-voltage control signal group. Furthermore, the drive circuit group is entirely composed of transistors whose element withstand voltage is lower than the voltage difference between the high-voltage positive power supply voltage and the high-voltage negative power supply voltage. Each drive circuit of the drive circuit group includes the drive circuit according to claim 6 or 7.

9. A display device, characterized in that: include: The display driver according to claim 8; as well as A liquid crystal display panel is driven according to the driving voltage signal output from the output terminal of each output channel of the display driver.

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