Semiconductor storage device

Abstract

The present invention provides a semiconductor memory device, which includes a transmission circuit and a control circuit. The transmission circuit is configured to obtain write data according to an external clock signal and transmit it to a memory cell array when a chip selection signal is enabled. The control circuit is configured to maintain the operation of the transmission circuit when the chip selection signal changes from enabled to disabled during the first write data input of the write data according to the external clock signal, so that the first write data is transmitted to the memory cell array. The semiconductor memory device of the present invention can properly write data to the semiconductor memory device even when the semiconductor memory device is deactivated during data writing.

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device operating asynchronously with an external clock signal. Background Art

[0002] Conventional semiconductor memory devices include synchronous dynamic random access memory (SDRAM) and pseudo-static random access memory (pSRAM). For example, the SDRAM disclosed in US Pat. No. 5,594,704 operates synchronously with an external clock signal.

[0003] In addition, pSRAM operates asynchronously with an external clock signal, uses dynamic random access memory (DRAM) as a memory cell array to store data, and has an interface compatible with static random access memory (SRAM). pSRAM uses a double data rate (DDR) method as a data transmission method, and can use an expanded serial peripheral interface (xSPI), HyperBusTM interface, or XccellaTM interface as an access interface.

[0004] Figure 1 (a) and (b) are timing diagrams of various signals in response to the input of a write instruction in an existing semiconductor memory device. Here, a pSRAM using a HyperBusTM interface is taken as an example. In this example, the pSRAM is configured to perform a write operation when the chip select signal CS# is valid (low level); when the chip select signal CS# is invalid (high level), the operation of the input receiver of the external clock signal CK is stopped to stop generating the internal clock signal. In this way, the validity of the chip select signal CS# is asynchronous with the external clock signal CK.

[0005] exist Figure 1In the write instruction sequence of (a), the case where the delay count is 3 and the burst length of the write data is 4 is taken as an example. In this example, after the chip select signal CS# becomes invalid (high level), the time tRWR (the time required for the semiconductor memory device to return to the read / write operation) passes, and then after the delay count of 3 external clock signals CK, the write data is input at the rising edge of the sixth clock of the external clock signal CK. Although the delay count is 3 as an example here, the value of the delay count depends on the frequency of the external clock signal CK. For example, when the frequency of the external clock signal CK is higher, the delay count is larger.

[0006] exist Figure 1 In the example (a), after the chip select signal CS# changes from invalid (high level) to valid (low level), the command (CMD), the row address (Row Address, RA), and the column address (Column Address, CA) are sequentially input according to the first to third clocks of the external clock signal CK. After that, according to the sixth clock of the external clock signal CK, the input write data (DE6, DO6) is written to the specified memory cell. Next, according to the seventh clock of the external clock signal CK, the input write data (DE7, DO7) is written to the specified memory cell.

[0007] Then, when all the write data in the write command are input, the chip select signal CS# changes from valid to invalid to end the write operation.

[0008] However, if Figure 1 As shown in (b), if the chip select signal CS# changes from valid to invalid during the input of write data (DE7, DO7), certain circuits in the semiconductor memory device will immediately terminate the operation, resulting in the input write data (DE7, DO7) being unable to be transmitted to the memory cell array. As a result, it may be difficult to write the write data (DE7, DO7) to the specified memory cell. Summary of the invention

[0009] In view of the above problems, an object of the present invention is to solve the problem that a semiconductor memory device is deactivated during data writing, resulting in data being unable to be completely written into the semiconductor memory device.

[0010] In order to solve the above-mentioned problems, the present invention provides a semiconductor memory device that performs a write operation in response to a chip select signal in an effective state. The semiconductor memory device includes a memory cell array, a transmission circuit, and a control circuit. When the chip select signal is in an effective state, the transmission circuit obtains write data according to an external clock signal and transmits it to the memory cell array. The control circuit maintains the operation of the transmission circuit when the chip select signal changes from an effective state to an invalid state during the first write data period of inputting the write data according to the external clock signal, so that the first write data is transmitted to the memory cell array.

[0011] According to the present invention, during the period when the first write data is input according to the external clock signal, even when the chip selection signal changes from valid to invalid, the first write data can be transmitted to the memory cell array to write the first write data to the memory cell in the memory cell array. Therefore, even when the semiconductor memory device is deactivated during the data writing period, data can be properly written to the semiconductor memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 (a) to (b) are timing diagrams showing time changes of signals in a conventional semiconductor memory device when a write command is input.

[0013] Figure 2 This is a block diagram showing the configuration of an input / output interface (I / O) unit and a control logic unit of a semiconductor memory device according to the first embodiment of the present invention.

[0014] Figure 3 (a) is a diagram showing a configuration example of a portion of a clock (CK) buffer. Figure 3 (b) is Figure 3 (a) is a timing diagram showing time changes of a signal in a portion of the CK buffer.

[0015] Figure 4 This is a timing diagram showing changes in signals in the semiconductor memory device when a write command is input.

[0016] Figure 5 This is a block diagram showing the configuration of an I / O unit and a control logic unit of a semiconductor storage device according to a second embodiment of the present invention.

[0017] Figure 6 (a) is a diagram showing a configuration example of a portion of a clock (CK) buffer. Figure 6 (b) is Figure 6 (a) is a timing diagram showing time changes of a signal in a portion of the CK buffer.

[0018] Figure 7This is a timing diagram showing the temporal changes of signals in the semiconductor memory device when a write command is input.

[0019] Figure 8 This is a block diagram showing the configuration of an I / O unit and a control logic unit of a semiconductor memory device according to a modified example of the present invention.

[0020] Fig. 9 (a) is a diagram showing a configuration example of a portion of an instruction decoder. Fig. 9 (b) is a diagram showing an example configuration of a portion of the CK buffer.

[0021] Fig.10 (a)~(b) are Fig. 9 (a) shows a portion of the instruction decoder and Fig. 9 (b) is a timing diagram showing the temporal changes of a signal in a portion of the CK buffer.

[0022] Fig.11 (a) is a diagram showing an example of the input timing of a chip selection signal based on existing semiconductor memory device specifications. Fig.11 (b) is an explanatory diagram of a case where a fixed frequency clock signal is input to adjust the input timing of a chip selection signal in a conventional semiconductor memory device. Fig.11 (c) is an explanatory diagram of an example of the input timing of a chip selection signal in a semiconductor memory device related to the embodiment and the modification of the present invention.

[0023] Figure Number:

[0024] 10:I / O Department

[0025] 11: Receiver

[0026] 12:DCK buffer

[0027] 13:DFF

[0028] 14: Receiver

[0029] 15:CS buffer

[0030] 16: Receiver

[0031] 17:CK buffer

[0032] 20: Control logic unit

[0033] 21: Instruction decoder

[0034] 22: Memory array control circuit

[0035] 100: P-channel MOSFET

[0036] 101: N-channel MOSFET

[0037] 102: Inverter

[0038] 103: Inverter

[0039] 104: Inverter

[0040] 105: Inverter

[0041] 106: Delay circuit

[0042] 200: Delay circuit

[0043] 201: Inverter

[0044] 202: Inverter

[0045] 203: Inverter

[0046] 204:NAND circuit

[0047] 205: Inverter

[0048] 206: Inverter

[0049] 207: Inverter

[0050] 208:NOR circuit

[0051] 209: Inverter

[0052] 210:NAND circuit

[0053] 211:NAND circuit

[0054] 212: Inverter

[0055] 213: Inverter

[0056] 214: P-channel MOSFET

[0057] 215: N-channel MOSFET

[0058] 216: Inverter

[0059] 217: Inverter

[0060] 218: Inverter

[0061] 300: first counter 300

[0062] 301: Second counter 301

[0063] 302: Comparator

[0064] 303: Inverter

[0065] 304:NAND circuit

[0066] 400: P-channel MOSFET

[0067] 401: N-channel MOSFET

[0068] 402: Inverter

[0069] 403: Inverter

[0070] 404: Inverter

[0071] 405: Inverter

[0072] n01: Node between inverter 104 and delay circuit 106

[0073] ACLKE: Signal input from DCK buffer 12

[0074] ACLKO: Signal input from DCK buffer 12

[0075] ADD: Signal input from DFF 13

[0076] ADQINX: Signal output from receiver 11

[0077] CASP: Bar Control Signal

[0078] CASPFP: signal output from inverter 209

[0079] CK: external clock signal

[0080] CLK1: internal clock signal

[0081] CLK1D: Delay signal

[0082] CLK1DRP: A signal output from the NAND circuit 204

[0083] CLKX: CK buffer 17 inputs the signal from receiver 16

[0084] CMD: Command

[0085] CS#: Chip select signal

[0086] CSACT: Inverted chip select signal

[0087] CSACTB: First control signal

[0088] CSACTC: Second control signal

[0089] CSADQX: Signal for activating receiver 11

[0090] CSCLKX: Signal used to activate receiver 16

[0091] CSINX: internal chip select signal

[0092] DCLK: data clock signal

[0093] DQ: data signal

[0094] ENCADRV: Signal used to activate DCK buffer 12

[0095] ENDQDRV: Signal used to activate DCK buffer 12

[0096] MASK1:MASK2 logical inversion signal

[0097] MASK2: The signal output from the inverter 212 ( Figure 6 ), the signal output from the inverter 402 ( Fig. 9 )

[0098] RA: Column address

[0099] RAS: Column control signal

[0100] CA: Column Address

[0101] DE6, DO6: write data

[0102] DE7, DO7: write data

[0103] PRE: Precharge signal

[0104] WRSTA: Signal indicating the status of the write operation

[0105] WRMTC: signal output from comparator 302

[0106] CNTDIN: Signal indicating the count value of the first counter 300

[0107] CNTWR: signal indicating the count value of the second counter 301 DETAILED DESCRIPTION

[0108] Hereinafter, a semiconductor memory device related to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments. Furthermore, the marks such as "first", "second", and "third" in this specification are used to distinguish a certain element from other elements, and are not limited to the number, order, priority, etc. of the elements.

[0109] Figure 21 is a block diagram of a semiconductor memory device according to Embodiment 1 of the present invention. The semiconductor memory device according to the present embodiment is a semiconductor memory device that performs deactivation of a chip select signal CS# asynchronously with respect to an external clock signal CK: wherein the semiconductor memory device comprises an input / output interface (I / O) unit 10, a control logic unit 20, and a memory cell array (omitted in the drawing) having a plurality of memory cells arranged in a matrix.

[0110] The I / O unit 10 is configured to receive and transmit signals (e.g., chip select signal CS#, data signal DQ, external clock signal CK, etc.) to and from an external device (e.g., a memory controller). In addition, the control logic unit 20 is configured to control operations such as reading or writing data to the memory cell based on instructions received from the external device. Further, the I / O unit 10, the control logic unit 20, and the memory cell array may be configured by dedicated hardware devices or logic circuits.

[0111] The semiconductor memory device related to this embodiment can be any semiconductor memory device (e.g., DRAM, pSRAM, SRAM, etc.) that performs deactivation of the chip select signal CS# asynchronously with respect to the external clock signal CK. In this embodiment, the semiconductor memory device is described by taking the pSRAM of the HyperBusTM interface as an example. Figure 1 The delay count in the write command sequence is 3 and the burst length of the write data is 4. In this embodiment, the delay count in the write command sequence is 3 and the burst length of the write data is 4. Figure 1 The signals shown in (a) and (b) are the same signal.

[0112] The I / O unit 10 includes a receiver 11 connected to a data terminal (DQ terminal), a data clock (DCK) buffer 12, a delay flip-flop (DFF) 13, a receiver 14 connected to a chip select terminal (CS# terminal), a chip select (CS) buffer 15, a receiver 16 connected to an external clock terminal (CK terminal), and a clock (CK) buffer 17. To simplify the description, other known configurations in the I / O unit 10 (e.g., circuits for sending or receiving other signals (data strobe signals, reset signals, etc.)) are not shown here.

[0113] The CS buffer 15 is configured to output a signal CSADQX, and the signal CSADQX is configured to activate (also called enable) the receiver 11 in an effective state. The receiver 11 is configured to receive a data signal DQ from an external device through a DQ terminal when receiving the signal CSADQX in an effective state from the CS buffer 15. Here, the data signal DQ is input according to the external clock signal CK, and includes a command of a specific length (in this embodiment, 8 bits), an address (column address, column address, etc.), and write data. In addition, the receiver 11 outputs the input data signal DQ as a signal ADQINX to the DFF 13.

[0114] The DCK buffer 12 is configured to be activated according to the valid states of the signal ENCADRV and the signal ENDQDRV, wherein the signal ENCADRV and the signal ENDQDRV may be provided by the command decoder 21 (to be described later).

[0115] Furthermore, while the signal ENCADRV is in the active state, in response to each rising edge of the clock of the internal clock signal CLK1 provided by the CK buffer 17, the DCK buffer 12 generates a signal ACLKE for acquiring the input command, address, and write data (including the signal ADQINX) at the rising edge of the external clock signal CK corresponding to the above clock, and outputs it to the DFF 13. In this case, the signal ACLKE may also be a signal having the same phase as the clock of the internal clock signal CLK1.

[0116] Furthermore, while the signal ENCADRV is valid, in response to each falling edge of the clock of the internal clock signal CLK1 input by the CK buffer 17, the DCK buffer 12 generates a signal ACLKO for obtaining the input command, address, and write data (including the signal ADQINX) at the falling edge of the external clock signal CK corresponding to the above clock, and outputs it to the DFF 13. In this case, the signal ACLKO may also be a signal having a phase opposite to that of the clock of the internal clock signal CLK1.

[0117] Furthermore, while the signal ENDQDRV is valid, in response to each falling edge of the clock of the internal clock signal CLK1 inputted from the CK buffer 17, the DCK buffer 12 generates a data clock signal DCLK for inputting write data (including the signal ADQINX) to be transferred to the memory cell array according to the external clock signal CK corresponding to the above clock, and outputs it to the DFF 13. In this case, the clock width of the data clock signal DCLK may be the same as or different from the clock width of the internal clock signal CLK1.

[0118] When the chip select signal CS# is enabled, the DFF 13 obtains the input write data according to the external clock signal CK and transmits it to the memory cell array. In addition, the DFF 13 is configured to operate when the signal ENCADRV or the signal ENDQDRV is enabled even when the chip select signal CS# is disabled (high level). In addition, the DFF 13 is an example of a "transmission circuit" in the present invention.

[0119] Specifically, when the signal ENCADRV is made valid, the DFF 13 obtains the signal ADQINX output from the receiver 11 each time the signal ACLKE and the signal ACLKO are received from the DCK buffer 12. Then, the DFF 13 outputs the signal ADD indicating the command and address included in the signal ADQINX to the command decoder 21 and the memory array control circuit 22 (described later). In addition, when the signal ENDQDRV is made valid, the DFF 13 obtains the signal ADQINX output from the receiver 11 each time the signal ACLKE and the signal ACLKO are received from the DCK buffer 12, and at the same time, the write data including the obtained signal ADQINX is parallelly converted and stored each time the DFF 13 inputs the data clock signal DCLK from the DCK buffer 12. Then, the DFF 13 outputs (transmits) the signal DQ indicating the write data including the signal ADQINX to the memory cell array according to the data clock signal DCLK.

[0120] The receiver 14 outputs a chip select signal CS# input from an external device via a CS# terminal to the CS buffer 15 as an internal chip select signal CSINX.

[0121] The CS buffer 15 operates when the internal chip selection signal CSINX is made valid (low level) or when the first control signal CSACTB provided by the CK buffer 17 is made valid (high level). Specifically, the CS buffer 15 logically inverts the internal chip selection signal CSINX from the receiver 14 and outputs the inverted chip selection signal CSACT to the CK buffer 17. In addition, the CS buffer 15 outputs the signal CSADQX in a valid (high level) state to the receiver 11, and outputs the signal CSCLKX for activating the receiver 16 in a valid (high level) state to the receiver 16.

[0122] When the valid signal CSCLKX is input from the CS buffer 15, the receiver 16 outputs the external clock signal CK input from the external device via the CK terminal as the signal CLKX to the CK buffer 17. In addition, the external clock signal CK may be input at a fixed frequency regardless of whether the chip select signal CS# is enabled.

[0123] When a valid (high level) inverted chip select signal CSACT is input from the CS buffer 15, the CK buffer 17 makes the first control signal CSACTB valid (high level) and outputs it to the CS buffer 15 and the instruction decoder 21. In addition, the CK buffer 17 uses the signal CLKX input from the receiver 16 as the internal clock signal CLK1 and outputs it to the DCK buffer 12 and the instruction decoder 21. The frequency of the internal clock signal CLK1 can be the same as or different from the frequency of the external clock signal CK. In addition, the frequency of the internal clock signal CLK1 can vary over time, for example, to temporarily accelerate data reading or writing operations.

[0124] In addition, according to the external clock signal CK, during the input of the first write data (here, write data (DE7, DO7)), when the chip select signal CS# changes from valid (low level) to invalid (high level), the CK buffer 17 operates the DFF 13 (transmission circuit) to transfer the write data (DE7, DO7) to the memory cell array. Here, the CK buffer 17 is an example of the "control circuit" in the present invention.

[0125] In addition, the first write data may be the last write data in the write instruction (in this embodiment, write data (DE7, DO7)). Thus, according to the external clock signal CK, during the input of the write data (DE7, DO7), even when the chip select signal CS# changes from valid (low level) to invalid (high level), since the write data (DE7, DO7) can be transmitted to the memory cell array, the write data (DE7, DO7) can be written to the memory cell in the memory cell array. Thus, all the write data input in the write instruction can be properly written to the semiconductor memory device.

[0126] In addition, even after the chip select signal CS# becomes invalid (high level), the CK buffer 17 can operate the DFF 13 by maintaining the first control signal CSACTB used to operate the DFF 13 (transmission circuit) in a valid (high level) state. The first control signal CSACTB (control signal) is generated based on the chip select signal CS#. Therefore, even when the chip select signal CS# changes from valid to invalid, since the first control signal CSACTB is valid (high level), the DFF 13 can be operated based on the valid first control signal CSACTB.

[0127] In addition, the internal clock signal CLK1 is generated based on the external clock signal CK, and the CK buffer 17 can maintain the first control signal CSACTB (control signal) in a valid (high level) state during the period when the internal clock signal CLK1 for generating the above-mentioned data clock signal DCLK is valid (high level); the above-mentioned data clock signal DCLK is a signal for transmitting the first write data (here, the write data (DE7, DO7)) to the memory cell array. Therefore, based on the internal clock signal CLK1, when the data clock signal DCLK for transmitting the write data (DE7, DO7) to the memory cell array is generated, the DFF 13 can be operated. According to the generated internal clock signal CLK1, the write data (DE7, DO7) can be transmitted to the memory cell array.

[0128] In addition, during the period from when the chip select signal CS# changes from valid (low level) to invalid (high level) until the next time it is valid, the CK buffer 17 ends the operation of the DFF 13 (transmission circuit). Thus, the DFF 13 can be reset before the chip select signal CS# is valid next time (i.e., the next read or write operation starts).

[0129] Next, the configuration of the control logic unit 20 will be described. The control logic unit 20 includes a command decoder 21 and a memory array control circuit 22. In addition, in order to simplify the description, other known configurations in the control logic unit 20 (for example, a circuit for controlling the refresh operation of the memory cell) are not shown here.

[0130] When the valid (high level) first control signal CSACTB is input from the CK buffer 17, at a specific clock (at the time of the internal clock signal CLK1 input from the CK buffer 17), Figure 4 In the example of the first clock) to the rising edge of the specific clock (in Figure 4 In the example of the third clock), during the falling edge of the third clock), the command decoder 21 outputs the valid (high level) signal ENCADRV to the DCK buffer 12. In addition, when the valid first control signal CSACTB is input from the CK buffer 17, at a specific clock of the internal clock signal CLK1 (at Figure 4 In the example of the sixth clock) to the rising edge of a specific clock (in Figure 4 In the example of FIG. 1 , during the falling edge of the seventh clock), the instruction decoder 21 outputs a valid (high level) signal ENDQDRV to the DCK buffer 12.

[0131] In addition, after all the column addresses input are recognized based on the signal ADD input from the DFF 13, when the clock of the internal clock signal CLK1 is input (at Figure 4In the example, at the third clock, the instruction decoder 21 makes the column control signal RAS for activating the selected word line valid (high level) through the input column address, and outputs it to the memory array control circuit 22.

[0132] In addition, at a specific clock of the internal clock signal CLK1 (at Figure 4 In the example of FIG1 , at the falling edge of the sixth clock and the seventh clock, respectively, the command decoder 21 makes the column control signal CASP for selecting the bit line to which the input write data is written into the memory array valid (high level) according to the external clock signal CK corresponding to the above clocks, and outputs it to the memory array control circuit 22. Here, the bit line of the memory cell is selected based on the column address including the signal ADD input from the DFF 13.

[0133] In addition, when the inactive (low level) first control signal CSACTB is input from the CK buffer 17, the clock of the column control signal CASP (in Figure 4 In the example, at the falling edge of the seventh clock), the command decoder 21 will use the precharge signal PRE to be valid (high level) and output it to the memory array control circuit 22, while making the column control signal RAS invalid (low level). The column control signal CASP is used to select the last write data (in Figure 4 In the example of FIG. 5 , write data (DE7, DO7) is written to the signal of the bit line of the memory cell.

[0134] Furthermore, when a specific pre-charging time has elapsed, the command decoder 21 renders the signal PRE inactive (low level), ends the operation, and shifts to the standby state.

[0135] The memory array control circuit 22 controls the instruction, address, and data to the memory cell array based on the signal ADD input from the DFF 13, the column control signal RAS, the column control signal CASP, and the signal PRE input from the instruction decoder 21. Further, since the details of the control of the instruction, address, and data to the memory cell array are the same as those of the known technology, the description thereof will be omitted in the present embodiment.

[0136] Next, refer to Figure 3 (a) and (b) of FIG. 1 illustrate the configuration and operation of a portion of the CK buffer 17. Figure 3(a) is a configuration example diagram of a portion of a clock (CK) buffer. The CK buffer 17 of one embodiment of the present invention includes a P-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor, MOSFET) 100, an N-channel MOSFET 101, four inverters 102, 103, 104, 105 and a delay circuit 106.

[0137] The source of the P-channel type MOSFET 100 is connected to a high voltage power source, and the drain of the MOSFET 100 is connected to the high voltage power source side of the inverter 103. To the gate of the MOSFET 100, an internal clock signal CLK1 is input.

[0138] The drain of the N-channel type MOSFET 101 is connected to the low voltage power supply side of the inverter 103. The source of the MOSFET 101 is connected to the low voltage power supply. The gate of the MOSFET 101 is connected to the output terminal of the inverter 102.

[0139] The internal clock signal CLK1 is input to an input terminal of the inverter 102. The inverter 102 logically inverts the input internal clock signal CLK1, and outputs the logically inverted signal to the gate of the MOSFET 101.

[0140] The inverted chip selection signal CSACT is input to the input terminal of the inverter 103. The output terminal of the inverter 103 is connected to the input terminal of the inverter 104. When the respective MOSFETs 100 and 101 are in the on state, the inverter 103 is operated. Specifically, the inverter 103 logically inverts the inverted chip selection signal CSACT and outputs the logically inverted signal to the inverter 104.

[0141] An input terminal of the inverter 104 is connected to an output terminal of the inverter 103. An output terminal of the inverter 104 is connected to the delay circuit 106. The inverter 104 logically inverts a signal output from the inverter 103, and outputs the logically inverted signal to the delay circuit 106.

[0142] The input terminal of the inverter 105 is connected to the node n01 between the inverter 104 and the delay circuit 106. In addition, the output terminal of the inverter 105 is connected to the node between the inverter 103 and the inverter 104. The inverter 105 logically inverts the signal output from the inverter 104, and outputs the logically inverted signal to the inverter 104.

[0143] The delay circuit 106 delays the signal output from the inverter 104 by a certain time, and outputs the delayed signal as the first control signal CSACTB to the CS buffer 15 and the instruction decoder 21 .

[0144] Next, refer to Figure 3 (b) Description of Figure 3 The operation of the CK buffer 17 is shown in part (a). In this embodiment, in the case of inputting Figure 4 During the period when the clock (seventh clock) of the external clock signal CK for writing data (DE7, DO7) shown is valid, the chip select signal CS# changes from valid (low level) to invalid (high level). First, when the inverted chip select signal CSACT is valid (high level) and the internal clock signal CLK1 is invalid (low level), the inverted chip select signal CSACT is input to the delay circuit 106 via the inverters 103 and 104. Then, the signal input to the delay circuit 106 is delayed, and the first control signal CSACTB is output from the delay circuit 106 as valid (high level).

[0145] Next, when the seventh clock of the external clock signal CK is made valid (high level), the seventh clock of the internal clock signal CLK1 is made valid (high level) at time t1. In this case, since the respective MOSFETs 100 and 101 become off states, the operation of the inverter 103 stops, and the potential of the output terminal of the inverter 103 is maintained at a low level. Thus, the first control signal CSACTB output from the delay circuit 106 is maintained in a valid (high level) state.

[0146] Then, at time t2, when the chip select signal CS# changes from valid (low level) to invalid (high level) during the period when the seventh clock of the external clock signal CK is valid, the inverted chip select signal CSACT changes from valid to invalid (low level). Here, since the seventh clock of the internal clock signal CLK1 is kept valid (high level), the respective MOSFETs 100 and 101 are kept in the off state. Therefore, the first control signal CSACTB that remains valid is output from the delay circuit 106.

[0147] In this way, the internal clock signal CLK1 is generated based on the external clock signal CK, and during the period when the internal clock signal CLK1 used to generate the data clock signal DCLK is valid, the CK buffer 17 maintains the first control signal CSACTB in a valid state; the above-mentioned data clock signal DCLK is a signal used to transmit write data (DE7, DO7) to the memory cell array.

[0148] Further, the command decoder 21 outputs a valid signal ENDQDRV based on the first control signal CSACTB output from the delay circuit 106. In addition, the DCK buffer 12 generates a data clock signal DCLK for transferring write data (DE7, DO7) to the memory cell array, and outputs it to the DFF 13. In addition, the DFF 13 obtains the signal ADQINX according to the input of the signal ACLKE, the signal ACLKO, and the data clock signal DCLK, and outputs (transmits) the signal DQ indicating the write data including the signal ADQINX to the memory cell array.

[0149] Thus, even if the chip select signal CS# becomes invalid (high level), the CK buffer 17 can still operate the DFF 13 by maintaining the first control signal CSACTB used to operate the DFF 13 in a valid (high level) state. The first control signal CSACTB is generated based on the chip select signal CS#.

[0150] In addition, in this way, according to the external clock signal CK, when the chip select signal CS# changes from valid (low level) to invalid (high level) during the input of write data (DE7, DO7), the CK buffer 17 operates the DFF 13 to transfer the write data (DE7, DO7) to the memory cell array.

[0151] Next, at time t3, when the seventh clock of the internal clock signal CLK1 changes from valid (high level) to invalid (low level), the individual MOSFETs 100 and MOSFETs 101 become conductive. In this case, the inverter 103 logically inverts the invalid (low level) inverted chip selection signal CSACT and outputs the logically inverted signal. Then, the signal output from the inverter 103 is input to the delay circuit 106 via the inverter 104. Then, the signal input by the delay circuit 106 is delayed, and at time t4, the invalid (low level) first control signal CSACTB is output from the delay circuit 106. At this time, based on the first control signal CSACTB output from the delay circuit 106, the instruction decoder 21 outputs the invalid (low level) signal ENDQDRV. Thus, the operation of the DCK buffer 12 is terminated, and further, the operation of the DFF 13 is terminated.

[0152] In one embodiment, the delay time in the delay circuit 106 can be arbitrarily set, for example, it can be set to be less than the invalid duration of the chip select signal CS# between read or write operations in the semiconductor memory device (for example, tCSHI in the HyperBusTM interface specification). In this case, the CK buffer 17 can end the operation of the DFF 13 during the period after the chip select signal CS# changes from valid to invalid and until the next time it becomes valid.

[0153] Figure 4 It is a timing diagram of the change of signals in the semiconductor memory device when a write command is input. First, when the chip select signal CS# changes from invalid (high level) to valid (low level), the CS buffer 15 starts to operate by making the internal chip select signal CSINX valid (low level). At this time, by making the inverted chip select signal CSACT valid (high level), the CK buffer 17 starts to operate (i.e., is enabled or activated). In addition, when the signal CSADQX and the signal CSCLKX are valid (high level), the receiver 11 and the receiver 16 start to operate. In addition, by making the first control signal CSACTB valid (high level), the command decoder 21 starts to operate, and according to the above-mentioned action, the DCK buffer 12, the DFF 13 and the memory array control circuit 22 start to operate.

[0154] Next, the command (CMD), the column address (RA), and the column address (CA) are inputted between the rising edge of the first clock of the external clock signal CK and the falling edge of the third clock. Then, at the falling edge of the second clock of the external clock signal CK, when all the column addresses are inputted, the column control signal RAS is made valid in response to the rising edge of the third clock of the internal clock signal CLK1 generated according to the external clock signal CK. The column control signal RAS is a signal for activating the word line selected by the input column address. Thus, the selected word line is activated by the column address.

[0155] Next, the write data (DE6, DO6) is input in the rising edge and falling edge of the sixth clock of the external clock signal CK. Then, in response to the falling edge of the sixth clock of the internal clock signal CLK1, the clock (sixth clock) of the data clock signal DCLK is enabled, and the data clock signal DCLK is a signal for transmitting the data (DE6, DO6) input by the sixth clock of the external clock signal CK to the memory cell array. According to the clock, the write data (DE6, DO6) is transmitted to the memory cell array.

[0156] Then, after the sixth clock of the internal clock signal CLK1 is invalidated (low level), the clock (sixth clock) of the column control signal CASP is valid (high level), and the column control signal CASP is a signal for selecting the bit line to which the write data (DE6, DO6) is written into the memory cell, and the bit line selected by the column address is activated. Thus, the input write data (DE6, DO6) is written into the memory cell by the sixth clock of the external clock signal CK.

[0157] Next, at the rising edge and falling edge of the seventh clock of the external clock signal CK, the write data (DE7, DO7) is input. Here, during the valid (high level) period of the seventh clock of the external clock signal CK, when the chip select signal CS# changes from valid (low level) to invalid (high level), the internal chip select signal CSINX is invalid (high level), and further, the inverted chip select signal CSACT is invalid (low level).

[0158] On the other hand, Figure 3 As described in (b), after the chip select signal CS# changes from valid (low level) to invalid (high level), the first control signal CSACTB can still be maintained in a valid (high level) state, so that the signal CSADQX and the signal CSCLKX are also maintained in a valid (high level) state. In this case, the receiver 11 and the receiver 16, the DCK buffer 12, the DFF 13, the CS buffer 15, the CK buffer 17, the instruction decoder 21 and the memory array control circuit 22 continue to operate. Thus, at the falling edge of the seventh clock of the internal clock signal CLK1, the clock (seventh clock) of the data clock signal DCLK is made valid (high level), and the above-mentioned data clock signal DCLK is a signal for transmitting the data (DE7, DO7) input by the seventh clock of the external clock signal CK to the memory cell array. Through the above-mentioned valid data clock signal DCLK, the input data (DE7, DO7) is transmitted to the memory cell array.

[0159] Then, after the seventh clock of the internal clock signal CLK1 is invalidated (low level), the clock (seventh clock) of the column control signal CASP is valid (high level), and the column control signal CASP is a signal for selecting the bit line to which the write data (DE7, DO7) is written into the memory cell, and the bit line selected by the column address is activated. Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK is written into the memory cell.

[0160] Furthermore, after a specific time has passed since the seventh clock of the internal clock signal CLK1 is invalid (low level), the first control signal CSACTB is invalid (low level), so that the signal CSADQX and the signal CSCLKX are invalid (low level). Thereby, the receiver 11, the receiver 16, the DCK buffer 12, the DFF 13, the CS buffer 15, and the CK buffer 17 end their operations.

[0161] In addition, at the falling edge of the seventh clock of the column control signal CASP, the precharge signal PRE is enabled (high level), and the column control signal RAS is disabled (low level). Then, when a specific precharge period has passed, the signal PRE is disabled (low level). At this time, the command decoder 21 and the memory array control circuit 22 end their operations.

[0162] In this way, according to the external clock signal CK, during the input of write data (DE7, DO7), when the chip select signal CS# changes from valid (low level) to invalid (high level), the write data (DE7, DO7) can be transmitted to the memory cell array, and the write data (DE7, DO7) can be written to the memory cell in the memory cell array.

[0163] As described above, according to the semiconductor memory device related to the present embodiment, according to the external clock signal CK, during the input of write data (DE7, DO7) (first write data), even when the chip selection signal CS# changes from valid (low level) to invalid (high level), the write data (DE7, DO7) can be transmitted to the memory cell array, and the write data (DE7, DO7) can be written to the memory cell in the memory cell array. Thus, even when the semiconductor memory device is deactivated during the data write operation, data can be properly written to the semiconductor memory device.

[0164] In addition, according to the semiconductor memory device related to the present embodiment, regardless of whether the chip selection signal CS# is made valid (low level), even when the external clock signal CK is input at a fixed frequency, the write data (DE7, DO7) (first write data) can be transmitted to the memory cell array, and the write data (DE7, DO7) can be written to the memory cell in the memory cell array. In addition, according to the semiconductor memory device related to the present embodiment, the supply timing of the external clock signal from the external device to the semiconductor memory device is not limited (for example, the interval between two consecutive clocks of the external clock signal is expanded or reduced, etc.). Since the external clock signal can be provided to the semiconductor memory device at a fixed frequency, a semiconductor memory device with improved operability can be realized.

[0165] Hereinafter, the second embodiment of the present invention will be described. The semiconductor memory device of this embodiment is different from the first embodiment in that the CK buffer 17 (control circuit) operates the DFF 13 (transmission circuit) until the write data (DE7, DO7) (first write data) is written to any memory cell in the memory cell array. Hereinafter, the configuration different from the first embodiment will be described.

[0166] Figure 5 FIG. 2 is a block diagram showing the configuration of the I / O unit and the control logic unit 20 of the semiconductor memory device according to the present embodiment. Figure 5 In the example of FIG. 1 , the second control signal CSACTC (control signal) is generated based on the chip selection signal CS#, and the second control signal CSACTC for operating the DFF 13 is input from the CK buffer 17 to the instruction decoder 21 .

[0167] When a valid (high level) inverted chip select signal CSACT is input from the CS buffer 15, the CK buffer 17 makes the first control signal CSACTB valid (high level) and outputs it to the CS buffer 15 and the instruction decoder 21. In addition, in the present embodiment, when a valid (high level) inverted chip select signal CSACT is input from the CS buffer 15, the CK buffer 17 makes the second control signal CSACTC valid (high level) and outputs it to the instruction decoder 21.

[0168] In addition, in the present embodiment, during the period when the column control signal CASP for selecting the bit line of the write data (DE7, DO7) (first write data) to be written to the memory cell is valid (high level), the CK buffer 17 operates the DFF 13 (transmission circuit). Thus, since the DFF 13 can be operated during the period when the column control signal CASP for selecting the bit line of the write data (DE7, DO7) to be written to the memory cell is valid (high level), the write data (DE7, DO7) can be more accurately transferred to the memory cell array.

[0169] In the present embodiment, when a valid (high level) first control signal CSACTB or a valid (high level) second control signal CSACTC is input from the CK buffer 17, the instruction decoder 21 outputs a valid (high level) signal ENCADRV to the DCK buffer 12 during a period from a rising edge of a specific clock (here, the first clock) of the internal clock signal CLK1 input from the CK buffer 17 to a falling edge of a specific clock (here, the third clock). In addition, when a valid (high level) first control signal CSACTB or a valid (high level) second control signal CSACTC is input from the CK buffer 17, the instruction decoder 21 outputs a valid (high level) signal ENDQDRV to the DCK buffer 12 during a period from a rising edge of a specific clock (here, the sixth clock) of the internal clock signal CLK1 input from the CK buffer 17 to a falling edge of a specific clock (here, the seventh clock).

[0170] Next, refer to Figure 6 (a) is a configuration example diagram of a portion of a clock (CK) buffer, wherein the CK buffer 17 includes a delay circuit 200, connected in series to three inverters 201, 202, and 203, a NAND circuit 204, connected in series to three inverters 205, 206, and 207, a NOR circuit 208, an inverter 209, an RS flip-flop formed by two NAND circuits 210 and 211, two inverters 212 and 213, a P-channel MOSFET 214, an N-channel MOSFET 215, and three inverters 216, 217, and 218.

[0171] The internal clock signal CLK1 is input to the delay circuit 200. The delay circuit 200 delays the input internal clock signal CLK1 by a certain time, and outputs a delay signal CLK1D to the NAND circuit 204 and the inverter 201.

[0172] An input terminal of the inverter 201 is connected to a node between the delay circuit 200 and the NAND circuit 204. In addition, the inverter 203 logically inverts the signal input via the inverters 201 and 202, and outputs the logically inverted signal to the NAND circuit 204.

[0173] The signal CLK1D output from the delay circuit 200 is input to one input terminal of the NAND circuit 204. In addition, the signal output from the inverter 203 is input to the other input terminal of the NAND circuit 204. In addition, the NAND circuit 204 performs NAND calculation based on the input signal, and outputs the signal CLKDRP as the calculation result to the NAND circuit 210.

[0174] The column control signal CASP is input to the input terminal of the inverter 205. In addition, the inverter 207 logically inverts the signal input via the inverters 205 and 206, and outputs the logically inverted signal to the NOR circuit 208.

[0175] The column control signal CASP is input to one input terminal of the NOR circuit 208. In addition, the signal output from the inverter 207 is input to the other input terminal of the NOR circuit 208. In addition, the NOR circuit 208 performs NOR calculation based on the input signal and outputs the calculation result to the inverter 209.

[0176] The inverter 209 logically inverts the signal input from the NOR circuit 208 , and outputs the logically inverted signal as a signal CASPFP to the NAND circuit 211 .

[0177] The signal CLK1DRP output from the NAND circuit 204 is input to one input terminal of the NAND circuit 210 of the RS flip-flop. In addition, the other input terminal of the NAND circuit 210 is connected to the output terminal of the NAND circuit 211. In addition, the output terminal of the NAND circuit 210 is connected to the input terminal of the inverter 212 and one input terminal of the NAND circuit 211. In addition, the signal CASPFP output from the inverter 209 is input to the other input terminal of the NAND circuit 211.

[0178] The inverter 212 logically inverts the signal output from the NAND circuit 210 , and outputs the logically inverted signal as a signal MASK2 to the inverter 213 and the MOSFET 215 .

[0179] The inverter 213 logically inverts the signal MASK2 output from the inverter 212 , and outputs the logically inverted signal as the signal MASK1 to the MOSFET 214 .

[0180] Further, the configuration of the MOSFETs 214, 215 and the three inverters 216, 217, 218 allows the signal MASK1 to be input to the gate of the MOSFET 214 and the signal MASK2 to be input to the gate of the MOSFET 215, except for the following. Figure 6 The signal of the node n01 shown in (a) is input to the inverter 216, and the second control signal CSACTC is output from the inverter 217. Figure 3 The configurations of the MOSFETs 100 and 101 and the three inverters 103, 104, and 105 shown in (a) are the same.

[0181] Reference Figure 6 (b) is Figure 61 is a timing diagram showing the time change of the signal in the CK buffer of a part shown in (a). First, when the inverted chip selection signal CSACT is made valid (high level), the internal clock signal CLK1 is made invalid (low level), and the bar control signal CASP is made invalid (low level), the signal MASK1 becomes low level, and the signal MASK2 becomes high level. Thus, the inverter 216 logically inverts the signal input to the node n01, and outputs the logically inverted signal to the inverter 217. In addition, the inverter 217 logically inverts the input signal, and outputs the logically inverted signal as the valid (high level) second control signal CSACTC.

[0182] Next, when the sixth clock of the external clock signal CK is made valid (high level), at time t11, the sixth clock of the internal clock signal CLK1 is made valid (high level). After that, the signal CLK1D is made valid (high level), and the signal CLK1DRP is changed to a low level. At this time, by setting the RS flip-flop, the signal MASK1 becomes a high level, and the signal MASK2 becomes a low level. In this case, since the individual MOSFETs 214 and 215 become the off state, the operation of the inverter 216 is stopped, and the potential of the output terminal of the inverter 216 is maintained at a low level. As a result, the second control signal CSACTC is maintained in a valid (high level) state.

[0183] Next, after a specific time has passed from the falling edge of the sixth clock of the internal clock signal CLK1, the clock (sixth clock) of the column control signal CASP is made valid (high level). Thus, the write data (DE6, DO6) input by the sixth clock of the external clock signal CK is written to the memory cell. Then, when the clock (sixth clock) of the column control signal CASP is made invalid (low level), at time t12, the signal CASPFP becomes low level. At this time, by resetting the RS flip-flop, the signal MASK1 becomes low level, and the signal MASK2 becomes high level. In this case, the individual MOSFETs 214 and MOSFETs 215 become conductive, and the inverter 216 logically inverts the input signal of the node n01, and outputs the logically inverted signal to the inverter 217. Here, since the logic level of the signal at the node n01 is the same as the logic level of the first control signal CSACTB (high level at this time), the second control signal CSACTC is maintained in a valid (high level) state.

[0184] Next, at time t13, based on the seventh clock of the internal clock signal CLK1 being made valid (high level), the signal CLK1DRP becomes low level. In this case, as described above, based on resetting the RS flip-flop, the respective MOSFETs 214 and 215 become off states. Thus, the second control signal CSACTC is maintained in a valid (high level) state.

[0185] Next, when the inverted chip select signal CSACT changes from valid (high level) to invalid (low level) during the period when the seventh clock of the internal clock signal CLK1 is valid (high level), the first control signal CSACTB is invalid (low level) after a specific time has passed since the seventh clock of the internal clock signal CLK1 is valid (high level).

[0186] Then, after a certain time has passed from the falling edge of the seventh clock of the internal clock signal CLK1, the clock (seventh clock) of the column control signal CASP is made valid (high level). Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK is written to the memory cell. Then, when the clock (seventh clock) of the column control signal CASP is made invalid (low level), at time t14, the signal CASPFP becomes low level. At this time, by resetting the RS flip-flop, the signal MASK1 becomes low level, and the signal MASK2 becomes high level. In this case, the individual MOSFETs 214 and MOSFETs 215 become conductive, and the inverter 216 logically inverts the input signal of the node n01, and outputs the logically inverted signal to the inverter 217. Here, since the logic level of the signal at the node n01 is the same as the logic level of the first control signal CSACTB (low level at this time), the second control signal CSACTC is invalid (low level).

[0187] At this time, since the first control signal CSACTB and the second control signal CSACTC are respectively inactive (low level), the command decoder 21 outputs an inactive (low level) signal ENDQDRV. Thus, the operation of the DCK buffer 12 ends, and further, the operation of the DFF 13 ends.

[0188] In this manner, the CK buffer 17 can operate the DFF 13 during a period in which the column control signal CASP for selecting a bit line to which write data (DE7, DO7) is written to a memory cell is active.

[0189] In addition, according to the external clock signal CK, during the input of write data (DE7, DO7), even if the chip select signal CS# changes from valid (low level) to invalid (high level), the CK buffer 17 can operate the DFF 13 until the write data (DE7, DO7) is written to any memory cell in the memory cell array.

[0190] Further, in the present embodiment, it should be noted that the delay time of the delay circuit 200 must be set so that the RS flip-flop is alternately set and reset (i.e., the clock (e.g., the sixth clock) of the column control signal CASP generated based on the clock (e.g., the sixth clock) of the internal clock signal CLK1 is invalidated (low level) before the clock (e.g., the seventh clock) of the delay signal CLK1D of the next internal clock signal CLK1 is valid (high level)).

[0191] Figure 7 is a timing diagram of the time change of the signal in the semiconductor memory device in this embodiment when a write command is input. Figure 4 The timing diagrams shown are different parts.

[0192] First, when the chip select signal CS# changes from invalid (high level) to valid (low level), the internal chip select signal CSINX is enabled (low level), and the inverted chip select signal CSACT is enabled (high level). Thus, the first control signal CSACTB and the second control signal CSACTC are enabled (high level).

[0193] Here, if Figure 6 As described in (b), the second control signal CSACTC is maintained in a valid (high) state until the clock (seventh clock) of the column control signal CASP for selecting the bit line to write the write data (DE7, DO7) to the memory cell is invalid (low level). In this case, Figure 7 As shown, because the effective (high level) state of the second control signal CSACTC is longer than the effective (high level) state of the first control signal CSACTB, the DCK buffer 12 and the DFF 13 are operated for a long time based on the effective second control signal CSACTC. Thus, compared with Embodiment 1, since the width of the seventh clock of the data clock signal DCLK can be expanded, the write data (DE7, DO7) can be transmitted to the memory cell array more accurately.

[0194] As described above, according to the semiconductor memory device related to the present embodiment, since the DFF 13 (transmission circuit) can be operated until the write data (DE7, DO7) (first write data) is written to the memory cell, the write data (DE7, DO7) (first write data) can be transmitted to the memory cell array more accurately.

[0195] Hereinafter, a modification of the above-mentioned embodiment 2 will be described. In this modification, the difference from the embodiment 2 is that, by writing write data (DE7, DO7) (first write data) to any memory cell, the CK buffer 17 (control circuit) can operate the DFF 13 (transmission circuit) until the number of write data written to any memory cell in the write instruction reaches the number of write data input in the write instruction. Hereinafter, a configuration different from the embodiment 2 will be described.

[0196] Figure 8 FIG. 1 is a configuration diagram of an I / O unit 10 and a control logic unit 20 of a semiconductor memory device according to a modified example of the present invention. Figure 8 In the example of , the CK buffer 17 is configured to output the second control signal CSACTC based on the signal MASK1 input from the instruction decoder 21 .

[0197] Next, refer to Fig. 9 (a) and (b) of FIG. 1 will now explain the configuration of the instruction decoder 21 and the CK buffer 17 in this modification. Fig. 9 (a) is a diagram showing a configuration example of a portion of the instruction decoder. The instruction decoder 21 includes a first counter 300 , a second counter 301 , a comparator 30 , an inverter 303 , and a NAND circuit 304 .

[0198] While the signal WRSTA indicating the write operation state is input in the valid (high level) state, the first counter 300 counts the number of input write data in the write data at each falling edge of the clock corresponding to the above write data among the write data of the clock of the internal clock signal CLK1 input from the CK buffer 17. Then, the first counter 300 outputs a signal CNTDIN indicating the count value to the comparator 302.

[0199] Here, the signal WRSTA may be generated by the command decoder 21. According to the external clock signal CK, when the input command (CMD) indicates a write command, the command decoder 21 may generate a valid (high level) signal WRSTA.

[0200] While the signal WRSTA is input in a valid (high level) state, the second counter 301 counts the number of write data written to any memory cell in the write command at each falling edge of the clock of the column control signal CASP input from the command decoder 21. Then, the second counter 301 outputs a signal CNTWR indicating the count value to the comparator 302.

[0201] The comparator 302 compares the signal CNTDIN input from the first counter 300 with the signal CNTWR input from the second counter 301. Then, when the values ​​indicated by the respective signals CNTDIN and CNTWR match, the comparator 302 outputs a high-level signal WRMTC to the NAND circuit 304. On the other hand, when the values ​​indicated by the respective signals CNTDIN and CNTWR do not match, the comparator 302 outputs a low-level signal WRMTC to the NAND circuit 304.

[0202] The inverter 303 logically inverts the internal clock signal CLK1 input from the CK buffer 17 , and outputs the logically inverted signal to the NAND circuit 304 .

[0203] The signal WRMTC output from the comparator 302 is input to one input terminal of the NAND circuit 304. In addition, the signal output from the inverter 303 is input to the other input terminal of the NAND circuit 304. In addition, the NAND circuit 304 performs NAND calculation based on the input signal and outputs the calculation result signal MASK1 to the CK buffer 17.

[0204] Next, refer to Fig. 9 (b) of FIG. 1 , a configuration of a part of the CK buffer 17 will be described. The CK buffer 17 includes a P channel type MOSFET 400, an N channel type MOSFET 401, and four inverters 402, 403, 404, and 405.

[0205] Further, the configuration of MOSFETs 400, 401 and four inverters 402, 403, 404, 405 is such that, in addition to the input of signal MASK1 to the gate of MOSFET 400, the input of signal MASK2 to the gate of MOSFET 401, and the output of control signal CSACTC from inverter 404, Figure 3 The configurations of the MOSFETs 100 and 101 and the four inverters 102, 103, 104, and 105 shown in (a) are the same.

[0206] Reference Fig.10 (a) to (b) will explain Fig. 9 (a) shows the operation of a portion of the instruction decoder 21, and Fig. 9 (b) shows the operation of a portion of the CK buffer 17. Here, Fig.10 (a) indicates that the clock (e.g., the sixth clock) of the bar control signal CASP generated based on the clock (e.g., the sixth clock) of the internal clock signal CLK1 is invalidated (low level) before the next clock (e.g., the seventh clock) of the internal clock signal CLK1 is valid (high level). In addition, Fig.10 (b) indicates that before the next clock of the internal clock signal CLK1 (for example, the seventh clock) is made valid (high level), the clock of the column control signal CASP (for example, the sixth clock) generated based on the clock of the internal clock signal CLK1 (for example, the sixth clock) is not invalid (low level).

[0207] First, refer to Fig.10 (a), when the inverted chip selection signal CSACT is enabled (high level), the internal clock signal CLK1 is disabled (low level), and the count values ​​of the first counter 300 and the second counter 301 are consistent (that is, the signal WRMTC is high level), the signal MASK1 is low level, and the signal MASK2 is high level. Thus, the inverter 403 performs a logic inversion on the input inverted chip selection signal CSACT, and outputs the logic-inverted signal to the inverter 404. In addition, the inverter 404 performs a logic inversion on the input signal, and outputs the logic-inverted signal as the valid (high level) second control signal CSACTC.

[0208] Next, when the sixth clock of the external clock signal CK is made valid (high level), at time t21, the sixth clock of the internal clock signal CLK1 is made valid (high level). At this time, the signal MASK1 becomes high level, and the signal MASK2 becomes low level. In this case, since the respective MOSFETs 400 and MOSFETs 403 become off states, the operation of the inverter 403 is stopped, and the potential of the output terminal of the inverter 403 is maintained at a low level. As a result, the second control signal CSACTC is maintained in an effective (high level) state.

[0209] Next, at time t22, the sixth clock of the internal clock signal CLK1 is invalid (low level). At this time, the count value of the first counter 300 increases, and since the values ​​of the respective signals CNTDIN and CNTWR are different, the signal WRMTC becomes low level. In this case, since the signal MASK2 is low level, the second control signal CSACTC is maintained in a valid (high level) state.

[0210] Then, after a specific time has passed from the falling edge of the sixth clock of the internal clock signal CLK1, the clock (sixth clock) of the column control signal CASP is made valid (high level). Thus, the write data (DE6, DO6) input by the sixth clock of the external clock signal CK is written to the memory cell. Then, at time t23, when the clock (sixth clock) of the column control signal CASP is made invalid (low level), the count value of the second counter 301 increases. Thus, since the values ​​of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes high level. In addition, when the signal MASK1 becomes low level and the signal MASK2 becomes high level, the inverter 403 starts to operate. Further, at this time, the second control signal CSACTC is maintained in a valid (high level) state.

[0211] In addition, when the chip select signal CS# changes from valid (low level) to invalid (high level) while the seventh clock of the internal clock signal CLK1 is valid (high level), the inverted chip select signal CSACT changes from valid (high level) to invalid (low level).

[0212] Next, at time t24, the seventh clock of the internal clock signal CLK1 is invalid (low level). At this time, the count value of the first counter 300 increases, and since the values ​​of the respective signals CNTDIN and CNTWR are different, the signal WRMTC becomes low level. Here, since the signal MASK2 is low level, the second control signal CSACTC is maintained in a valid (high level) state.

[0213] Then, after a specific time has passed from the falling edge of the seventh clock of the internal clock signal CLK1, the clock (seventh clock) of the column control signal CASP is made valid (high level). Thus, the write data (DE7, DO7) input by the seventh clock of the external clock signal CK is written to the memory cell. Then, at time t25, when the clock (seventh clock) of the column control signal CASP is made invalid (low level), the count value of the second counter 301 increases. Thus, since the values ​​of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes high level. In addition, when the signal MASK1 becomes low level and the signal MASK2 becomes high level, the inverter 403 starts to operate. The inverter 403 logically inverts the input inverted chip select signal CSACT and outputs the logically inverted signal to the inverter 404. Here, since the logic level of the first control signal CSACTB is the same as the logic level of the inverted chip select signal CSACT (low level at this time), the second control signal CSACTC is made invalid (low level).

[0214] At this time, since the first control signal CSACTB and the second control signal CSACTC are respectively inactive (low level), the command decoder 21 outputs an inactive (low level) signal ENDQDRV. Thus, the operation of the DCK buffer 12 ends, and further, the operation of the DFF 13 ends.

[0215] In this way, by writing write data (DE7, DO7) to any memory cell, the CK buffer 17 can operate the DFF 13 until the number of write data written to any memory cell in the write instruction reaches the number of write data input in the above write instruction.

[0216] Next, we will explain about Fig.10 (b) Here, the states of the individual signals at time t31 and time t32 are different from Fig.10 The states of the respective signals at time t21 and time t22 in (a) are the same.

[0217] At time t33, while the clock (seventh clock) of the column control signal CASP is valid (high level), when the seventh clock of the internal clock signal CLK1 is valid (high level), since the values ​​of the respective signals CNTDIN and CNTWR are still different, the signal WRMTC becomes low level. In addition, since the signal MASK2 is low level, the second control signal CSACTC is maintained in a valid (high level) state.

[0218] Next, at time t34, when the clock (sixth clock) of the column control signal CASP is invalidated (low level), the count value of the second counter 301 increases. As a result, since the values ​​of the respective signals CNTDIN and CNTWR are equal, the signal WRMTC becomes high level. Here, since the seventh clock of the internal clock signal CLK1 is valid (high level), the signal MASK2 is still low level. Therefore, the second control signal CSACTC is maintained in the valid (high level) state.

[0219] Then, at time t35, the seventh clock of the internal clock signal CLK1 is invalidated (low level). At this time, due to the increase in the count value of the first counter 300, the signal WRMTC becomes low level because the values ​​of the respective signals CNTDIN and CNTWR are different. In this case, since the signal MASK2 is low level, the second control signal CSACTC is maintained in a valid (high level) state.

[0220] The states of the individual signals at time t36 are Fig.10 The states of the individual signals at time t25 in (a) are the same.

[0221] As described above, according to this variation, it is possible to obtain the same effect as that of the above-described second embodiment without adjusting the effective timing between the internal clock signal CLK1 and the column control signal CASP. Furthermore, since the time variation of the signal in the semiconductor memory device of this variation when a write command is input is the same as that of the above-described second embodiment, the description thereof will be omitted.

[0222] As described above, according to the semiconductor memory device of this variant, until the amount of write data written to the memory cell in the write instruction reaches the amount of write data input in the write instruction (i.e., the write data (DE7, DO7) (first write data) is written to the memory cell), the write data (DE7, DO7) can be more accurately transmitted to the memory cell array because the operation of DFF13 (transmission circuit) is maintained.

[0223] Furthermore, in each of the above-mentioned embodiments and modifications, although the semiconductor memory device is described by taking the case of pSRAM using the HyperBus™ interface as an example, in this case, further effects described below are exerted.

[0224] Fig.11 (a) is an explanatory diagram of an input timing of a chip select signal CS# based on existing semiconductor memory device standards. The HyperBusTM interface standard defines a dynamic characteristic (AC characteristic) of the chip select signal CS#. Fig.11 (a) shows an example of the minimum value of each parameter when the external clock signal CK is 200Mhz. Here, tCSS is the setup time of the chip select signal CS# until the next rising edge of the external clock signal CK, and tCSH is the hold time of the chip select signal CS# after the falling edge of the external clock signal CK. In addition, tCK is the clock cycle, and tCKHP is the half cycle of the clock.

[0225] like Fig.11 As shown in (a), based on individual parameters, when the input timing of the chip selection signal CS# is adjusted, the interval between the zeroth clock and the first clock of the external clock signal CK, and the interval between the seventh clock and the eighth clock are different from the intervals between other clocks, making it difficult to input the external clock signal CK at a fixed frequency.

[0226] Therefore, if Fig.11As shown in (b), regardless of whether the chip select signal CS# is enabled (low level), when the individual parameters are redefined so that the external clock signal CK can be input at a fixed frequency, it is still difficult to input a high-frequency external clock signal CK of, for example, 200 MHz, etc. at a fixed frequency because the range of the timing margin of tCSH is as narrow as about 0.7 ns. In addition, in the conventional semiconductor memory device, when the chip select signal CS# is disabled (high level) during a period when the clock (here, the seventh clock) of the external clock signal CK is enabled (high level), the write data input at the above clock is not transmitted to the memory cell array, and as a result, it may be difficult to write the write data to the memory cells in the memory cell array.

[0227] On the other hand, Fig.11 As shown in (c), according to the semiconductor memory devices of the above-mentioned embodiments and modified examples, during the input of write data, even if the chip select signal CS# changes from valid (low level) to invalid (high level), the above write data can be transmitted to the memory cell array. Furthermore, since the above write data can be written to the memory cells in the memory cell array, the value of tCSH can increase in the negative direction (for example, -1.5ns). Thus, the timing margin range of tCSH can be expanded to about 1.85 (=1.5+0.35)ns. Therefore, according to the semiconductor memory devices of the above-mentioned embodiments and modified examples, while maintaining compatibility with the HyperBusTM interface specification, a high-frequency external clock signal CK of 200Mhz or the like can continue to be input regardless of whether the chip select signal CS# is enabled. Therefore, the performance of a system combining an external device (for example, a memory controller) and a semiconductor memory device can be improved.

[0228] The above-mentioned embodiments and modifications are used to simply understand the present invention and are not described to limit the present invention. Therefore, the various features shown in the above-mentioned embodiments and modifications are intended to include all design changes and equivalents belonging to the technical scope of the present invention.

[0229] For example, in the above-mentioned embodiments and modified examples, although the case of using the HyperBusTM interface is used as an example for explanation, the present invention is not limited thereto. For example, even when using the XccellaTM interface, the same effects as those of the above-mentioned embodiments and modified examples can be obtained.

[0230] In addition, in each of the above-mentioned embodiments and variations, a signal that is effective at a low level can be changed to be effective at a high level. In addition, a signal that is effective at a high level can be changed to be effective at a low level.

[0231] In addition, in the above-mentioned embodiments and modifications, although the case where the CK buffer 17 is a control circuit is described as an example, the present invention is not limited to this. Figure 3 (a), Figure 6 (a), and / or Fig. 9 The other circuit of the configuration shown in (b) serves as a control circuit.

[0232] In addition, in the above-mentioned embodiments and variations, although the instruction decoder 21 has Fig. 9 The configuration shown in (a) is described as an example, but the present invention is not limited to this. For example, Fig. 9 The configuration shown in (a) may be provided in the CK buffer 17, or may be provided in another circuit.

[0233] In addition, in the above-mentioned embodiments and modified examples, although the case where the chip select signal CS# changes from valid to invalid during the input of the last write data (write data (DE7, DO7)) in the write instruction is described as an example, the present invention is not limited to this. For example, even if the chip select signal CS# changes from valid to invalid during the input of other write data (for example, write data (DE6, DO6)), the above-mentioned embodiments and modified examples can also obtain the same functions and effects as described above.

[0234] in addition, Figure 3 (a), Figure 6 (a), Fig. 9 (a) and Fig. 9 The configuration shown in (b) is an example and can be appropriately changed, and various other configurations can be adopted.

[0235] In addition, the configurations of the I / O unit 10 and the control logic unit 20 in the above-mentioned embodiments and modifications are examples, and can be appropriately changed, and various other configurations can be adopted.

Claims

1. A semiconductor storage device, characterized in that: In response to a chip select signal in an active state, a write operation is performed, comprising: a memory cell array comprising a plurality of memory cells; a transmission circuit, which, when the chip selection signal is in the valid state, obtains write data according to an external clock signal and transmits the data to the memory cell array; and a control circuit, according to the external clock signal, during a first write data input period of the write data, after the chip select signal changes from the valid state to the invalid state, maintaining the operation of the transmission circuit so that the first write data is transmitted to the memory cell array; The control circuit is configured to generate a first control signal according to the inverted chip selection signal, and the control circuit is configured to keep the transmission circuit operating by maintaining the first control signal for activating the transmission circuit in a valid state even after the chip selection signal becomes the invalid state.

2. The semiconductor memory device according to claim 1, wherein The first write data is the last write data in the write command.

3. The semiconductor memory device according to claim 1, wherein: The control circuit is also configured to generate an internal clock signal based on the external clock signal, and during the period when the internal clock signal used to generate a data clock signal is in a valid state, the control circuit maintains the first control signal in the valid state, and the data clock signal is a signal for transmitting the first write data to the memory cell array.

4. The semiconductor memory device according to claim 1, wherein: The control circuit operates the transfer circuit until the first write data is written into any memory cell in the memory cell array.

5. The semiconductor memory device according to claim 4, wherein: The control circuit is configured to receive a column control signal, and operate the transmission circuit while the column control signal is in an effective state; the column control signal is a signal for selecting a bit line of a memory cell into which the first write data is written.

6. The semiconductor memory device according to claim 4 or 5, wherein: By writing the first write data to any of the memory cells, the control circuit operates the transmission circuit until the amount of write data written to any of the memory cells in the write command reaches the amount of write data input in the write command.

7. The semiconductor memory device according to claim 1, wherein: After the chip selection signal changes from the valid state to the invalid state, and until the chip selection signal changes to the valid state next time, the control circuit terminates the operation of the transmission circuit.

8. The semiconductor memory device according to claim 1, wherein: The external clock signal is input at a fixed frequency.

9. The semiconductor memory device according to claim 3, wherein: Also includes: a command decoder coupled to the control circuit to receive the internal clock signal and the first control signal and configured to generate a data clock buffer control signal; as well as A data clock buffer is coupled to the transmission circuit and is configured to be activated according to the data clock buffer control signal in a valid state. When the data clock buffer is activated, the data clock buffer generates a signal for obtaining the write data and the data clock signal in response to the internal clock signal.

10. The semiconductor memory device according to claim 9, wherein: Also includes: a chip selection signal receiver configured to generate an internal chip selection signal according to the chip selection signal; a chip select buffer coupled to the chip select signal receiver and configured to output a data receiver control signal and an external clock signal receiver control signal; a data receiver coupled to the transmission circuit and the chip selection buffer, the data receiver being configured to be activated according to the data receiver control signal in a valid state to receive the write data from an external device; as well as The external clock signal receiver is coupled to the control circuit and the chip selection buffer and is configured to be activated according to the external clock signal receiver control signal to output the external clock signal to the control circuit.

11. The semiconductor memory device according to claim 10, wherein: When the data clock buffer control signal is in the valid state, each time the signal for obtaining the write data is received from the data clock buffer, the transmission circuit obtains the write data from the data receiver and then outputs the address signal in the obtained write data to the command decoder.

12. The semiconductor memory device according to claim 10, wherein: While the transmission circuit obtains the write data from the data receiver, each time the data clock signal is received from the data clock buffer, the write data is converted and stored in parallel, and then the write data is transmitted to the memory cell array according to the data clock signal.

13. The semiconductor memory device according to claim 9, wherein: The control circuit generates a second control signal in a valid state according to the inverted chip selection signal, and outputs the second control signal to the instruction decoder. When either the first control signal or the second control signal received by the instruction decoder is in the valid state, the instruction decoder generates the data clock buffer control signal in the valid state.

14. The semiconductor memory device according to claim 1, wherein: The control circuit includes a delay circuit, to which the chip selection signal is provided according to an internal clock signal. The delay circuit is configured to delay the received chip selection signal to generate a first control signal, and since the chip selection signal changes from the valid state to the invalid state, the delay circuit maintains the first control signal in a valid state while the internal clock signal remains in a valid state, thereby allowing the transmission circuit to maintain operation.

15. The semiconductor memory device according to claim 14, wherein: After the chip selection signal and the internal clock signal become the invalid state, during the delay period of the delay circuit, the delay circuit maintains the first control signal in the valid state, so that the transmission circuit maintains operation.

16. The semiconductor memory device according to claim 9, wherein: The instruction decoder is also configured to generate a calculation result signal based on the internal clock signal and the column control signal, and the control circuit is configured to generate a second control signal based on the calculation result signal, wherein the control circuit is configured to maintain the second control signal in the valid state for a period greater than the first control signal.

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