Previewing adjacent storage devices and methods for data recovery

Abstract

The present invention, entitled "Advance Look-Up for Data Recovery," discloses a storage device. The storage device is configured to: determine the data states of a first group of memory cells and a second group of memory cells of a first adjacent word line and a second adjacent word line, the first and second adjacent word lines being adjacent to a selected word line; identify one of a plurality of regions for each combination of data states, each combination including the data states of memory cells in the first group and the second group, each region corresponding to a data retention compensation scheme; and perform a read operation on the selected word line, including applying each data retention compensation scheme corresponding to any identified region.

Description

Technical Field

[0001] This application relates to the operation of non-volatile memory devices. Background Technology

[0002] This section provides background information related to the technology associated with this disclosure, and is not necessarily prior art.

[0003] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0004] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers. Summary of the Invention

[0005] This section provides a general overview of the disclosure and is not a full disclosure of its entire scope or all its features and advantages.

[0006] The purpose of this disclosure is to provide a memory device and a method for operating the memory device that resolve and overcome the disadvantages described herein.

[0007] Therefore, one aspect of this disclosure is to provide a storage device. The storage device includes: a non-volatile memory including control circuitry and a memory cell array formed using a set of word lines and a set of bit lines; and a controller coupled to the non-volatile memory. The controller is configured to: determine the data states of a first set of memory cells of a first adjacent word line and a second set of memory cells of a second adjacent word line in the set of word lines, each data state being any one of a plurality of data states configured to be stored by the first and second sets of memory cells, the first and second adjacent word lines being adjacent to a selected word line in the set of word lines; identify a region from a plurality of regions for each combination of data states, each combination including the data states of memory cells in the first and second sets of memory cells, the memory cells in the first and second sets of memory cells being adjacent to memory cells in a third set of memory cells of the selected word line, and wherein each region from the plurality of regions corresponds to a data retention compensation scheme; and perform a read operation on the selected word line, including applying each data retention compensation scheme corresponding to any region from the plurality of regions identified for the third set of memory cells of the selected word line.

[0008] Further applicable fields will become apparent from the description provided herein. The descriptions and specific examples in this invention are intended for illustrative purposes only and are not intended to limit the scope of the invention. Attached Figure Description

[0009] For a detailed description of the exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0010] Figure 1A This is a block diagram of an exemplary memory device;

[0011] Figure 1B It is a block diagram of an exemplary control circuit that includes a programming circuit, a counting circuit, and a determining circuit;

[0012] Figure 2 Depicting Figure 1A A block of memory cells in an exemplary two-dimensional configuration of a memory array;

[0013] Figure 3A A cross-sectional view of an exemplary floating-gate memory cell in a NAND string is depicted;

[0014] Figure 3B It depicts the section taken along line 329. Figure 3A A sectional view of the structure;

[0015] Figure 4A A cross-sectional view of an exemplary charge-trapping memory cell in a NAND string is depicted;

[0016] Figure 4B It depicts the section taken along line 429. Figure 4A A sectional view of the structure;

[0017] Figure 5A Depicting Figure 1A An exemplary block diagram of the sensing block SB1;

[0018] Figure 5B Depicting Figure 1A Another exemplary block diagram of the sensing block SB1;

[0019] Figure 6A yes Figure 1A A perspective view of a set of blocks in an exemplary three-dimensional configuration of a memory array;

[0020] Figure 6B Depicting Figure 6A An exemplary cross-sectional view of a portion of a block;

[0021] Figure 6C Depicting Figure 6B A diagram showing the diameter of memory holes in a stack;

[0022] Figure 6D Depicting Figure 6B A close-up view of the stacked area 622;

[0023] Figure 7A Depicting Figure 6B A top view of an exemplary stacked word line layer WLL0;

[0024] Figure 7B Depicting Figure 6B A top view of an exemplary top dielectric layer DL19 of the stack;

[0025] Figure 8A Depicting Figure 7A An example NAND string in sub-blocks SBa to SBd;

[0026] Figure 8B Another exemplary view depicting the NAND string in the sub-block;

[0027] Figure 8C A top view depicting an exemplary stacked layer of letter lines;

[0028] Figure 9 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with four data states;

[0029] Figure 10 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with eight data states;

[0030] Figure 11 The distribution of Vth of memory cells is depicted in an exemplary one-pass programming operation with eight data states;

[0031] Figure 12A and Figure 12B Exemplary representations of regions for one- and two-digit read recognition are provided;

[0032] Figures 13A and 13B show exemplary graphical representations of the overall Vth distribution and four regions identified within the overall Vth distribution;

[0033] Figure 14 This is a flowchart for performing a method to preview adjacent reads;

[0034] Figures 15 to 18 An exemplary table is provided that maps zones to combinations of data states; and

[0035] Figures 19 to 21 It provides an opportunity to preview another exemplary implementation waveform in an adjacent location. Detailed Implementation

[0036] In the following description, details are set forth to provide an understanding of this disclosure. In some instances, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure this disclosure.

[0037] Generally, this disclosure relates to a type of nonvolatile memory device that is well-suited to many applications. The nonvolatile memory device and associated methods of its formation will be described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are merely intended to clearly describe the concepts, features, advantages, and objects of the invention, allowing those skilled in the art to understand and practice this disclosure. Specifically, exemplary embodiments are provided so that this disclosure will be comprehensive and will fully convey the scope to those skilled in the art. Numerous specific details, such as examples of specific components, apparatus, and methods, are set forth to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that specific details are not required, exemplary embodiments may be embodied in many different forms, and none should be construed as limiting the scope of this disclosure. In some exemplary embodiments, well-known processes, well-known apparatus structures, and well-known techniques are not described in detail.

[0038] Various terms are used to refer to specific system components. Different companies may refer to components by different names—this document does not intend to distinguish between components with different names but the same function. In the following discussion and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be understood as meaning "including but not limited to...". Furthermore, the terms "couple" or "couples" are intended to indicate indirect or direct connections. Thus, if a first device is coupled to a second device, the connection can be made either directly or indirectly via other devices and connections.

[0039] Additionally, when a layer or element is referred to as being "on" another layer or substrate, it may be directly on another layer of the substrate, or an intermediary layer may also be present. Furthermore, it should be understood that when a layer is referred to as being "below" another layer, it may be located directly below the other layer, and one or more intermediary layers may also be present. Moreover, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intermediary layers may also be present.

[0040] Programming a set of memory cells in a memory device typically involves applying a series of programming voltages to these cells after they have been provided in an erased state. Each programming voltage is applied in a programming cycle (also known as a program-verify iteration). For example, the programming voltage may be applied to a word line connected to the control gate of the memory cell. In one approach, incremental step-pulse programming is performed, where the programming voltage increases by a step size in each programming cycle. A verification operation can be performed after each programming voltage to determine whether the memory cell has been successfully programmed. When programming of a memory cell is complete, that memory cell can be locked to prevent further programming while programming of other memory cells continues in subsequent programming cycles.

[0041] Each memory cell can be associated with a data state based on the data written in the program commands. Based on the data state of the memory cell, the memory cell will remain in an erased state or be programmed to a data state different from the erased state (programmed data state). For example, in a one-bit memory device per cell (Single Level Cell (SLC)), there are two data states, including an erased state and a higher data state. In a two-bit memory device per cell (Multi-Level Cell (MLC)), there are four data states, including an erased state and three higher data states, referred to as A, B, and C data states (see See...). Figure 9 In a three-bit memory device (three-level cell (TLC)), there are eight data states, including the erase state and seven higher data states, referred to as A, B, C, D, E, F, and G data states (see also...). Figure 10In a four-bit memory device per cell (quad-level cell (QLC)), there are sixteen data states, including the erase state and fifteen higher data states, referred to as Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see also...). Figure 11 Each memory cell can store a data state (e.g., a binary value) and is programmed with a threshold voltage state corresponding to the data state. Each state represents a different value and is assigned a voltage window that includes a range of possible threshold voltages.

[0042] When a program command is issued, the written data is stored in a latch associated with the memory cell. During programming, the latch of the memory cell can be read to determine the data state to which the cell will be programmed. Each programming data state is associated with a verification voltage, such that a memory cell with a given data state is considered programmed when a sensing operation determines that its threshold voltage (Vth) is higher than the associated verification voltage. The sensing operation determines whether the memory cell has a Vth higher than the associated verification voltage by applying the associated verification voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, such that Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, such that Vth is higher than the control gate voltage.

[0043] The verification voltage used to determine that a memory cell has completed programming may be called the final verification voltage or the latch verification voltage. In some cases, an additional verification voltage may be used to determine that the memory cell is nearing programming completion. This additional verification voltage may be called an offset verification voltage and may be lower than the final verification voltage. When a memory cell is nearing programming completion, the programming speed of the memory cell can be reduced, for example, by increasing the voltage of the corresponding bit line during one or more subsequent programming voltages. Figure 9 In this process, the memory cell to be programmed into data state A can undergo verification tests under VvAL (offset verification voltage of data state A) and VvA (final verification voltage of data state A).

[0044] However, technological advancements have reduced the size of memory circuitry and related hardware, making efficient programming of memory cells more difficult. For example, by reducing the size of memory circuitry and related hardware, more memory cells can be placed within the memory architecture. The shrinking of silicon oxide and silicon nitride (“ON”) pitch reduces the amount of physical space between word lines. Therefore, when a memory cell is programmed, adjacent word line interference (NWI) from adjacent memory cells can affect the program-verify operation, requiring additional program-verify iterations to complete the programming of the memory cell.

[0045] More specifically, the trend of ON-pitch shrinkage from generation to generation of BiCS NAND has led to a reduction in the effective gate length and word-to-word distance of the cells. Consequently, NWI has deteriorated and Vth margin has worsened. Using conventional full-sequence programming schemes, memory cells with adjacent word lines in a high state (i.e., WLn+1) exhibit higher Vth due to the NWI effect, and this effect is stronger in memory cells with narrower ON-pitch. Furthermore, during High Temperature Data Retention (HTDR), the Vth of memory cells with low Vth adjacent word lines shifts downward more than that of memory cells with high Vth adjacent word lines. Therefore, the Vth distribution widens further after data retention, and this effect (due to lateral charge movement) is worse in memory cells with narrower ON-pitch.

[0046] To maintain valid data information and minimize FBC, common methods used to compensate for DR loss during read operations include applying different read pass voltage (VREADK) values ​​at WLn+1 or different read voltage (VCG) values ​​at WLn (selected word line). Different VREADK or VCG values ​​can be applied to each of multiple "regions" to modulate the Vth distribution location of WLn. These regions are formed based on the data states of adjacent memory cells at WLn+1. WLn+1 can be read before performing a read operation on WLn to obtain WLn+1 state information. This helps tighten the Vth distribution. VREADK can also be used to compensate for device variations with different WL-WL distances.

[0047] The grouping techniques used in the conventional methods cited above are not optimal. Specifically, these methods only consider WLn+1 in the identified region. To address this issue, the implementation described herein involves Look-Ahead Adjacency (LNA) prefetching, which groups the most similar memory cells into a region, resulting in a more compact distribution of Vth after alignment. The Look-Ahead Adjacency (LNA) prefetching method involves reading the state information of both WLn+1 and WLn-1 before reading WLn, and classifying combinations of the data states of the memory cells of WLn+1 and WLn-1 into different regions. Each region may correspond to a data retention compensation scheme, and a read operation may be performed on WLn, including applying each data retention compensation scheme corresponding to any identified region. According to the implementation described herein, LNA prefetching may include reading logical WLn+1 first and then logical WLn-1 for any read bit, or reading logical WLn-1 first and then logical WLn+1 for any read bit. In some implementations, LNA prefetching may include reading logic WLn+1 and logic WLn-1 simultaneously for any read bit.

[0048] To further illustrate the foregoing, the following description will now be provided. Figure 1A . Figure 1A This is a block diagram of an exemplary memory device. Memory device 100 may include one or more memory dies 108. Memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines via row decoder 124 and via bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sense blocks SB1, sense blocks SB2, ..., SBp (sensor circuitry system) and allows for parallel reading or programming of pages of memory cells. Typically, controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one of the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0049] The memory structure can be a 2D memory structure or a 3D memory structure. A memory structure may include one or more memory cell arrays, including 3D arrays. A memory structure may include a monolithic three-dimensional memory structure in which multiple memory stages are formed on (but not in) a single substrate, such as a wafer, without an intervening substrate. A memory structure may include any type of non-volatile memory, monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. A memory structure may be in a non-volatile memory device having circuitry associated with the operation of memory cells, whether the associated circuitry is on or within the substrate.

[0050] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes state machine 112, on-chip address decoder 114, and power control module 116. State machine 112 provides chip-level control of memory operations. Storage area 113 may be provided, for example, for verifying the parameters described herein.

[0051] On-chip address decoder 114 provides an address interface between the address interface used by the host or memory controller and the hardware address used by decoders 124 and 132. Power control module 116 controls the power and voltage supplied to word lines and bit lines during memory operation. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, a sensing block may include bit line drivers. The SGS transistor is a select-gate transistor at the source terminal of the NAND string, and the SGD transistor is a select-gate transistor at the drain terminal of the NAND string.

[0052] In some specific implementations, some of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoder 114 / 132, power control module 116, sensing block SBb, sensing block SB2, ..., SBp, read / write circuit 128, controller 122, etc.

[0053] The control circuitry may include programming circuitry configured to program and verify the memory cells of the word lines of the block. The control circuitry may also include counting circuitry configured to determine the number of memory cells verified to be in a data state. The control circuitry may further include determining circuitry configured to determine, based on the number, whether the block is faulty.

[0054] For example, Figure 1B This is a block diagram of an exemplary control circuit 150 including a programming circuit 151, a counting circuit 152, and a determining circuit 153. The programming circuit may include software, firmware, and / or hardware. The counting circuit may include software, firmware, and / or hardware. The determining circuit may include software, firmware, and / or hardware.

[0055] The off-chip controller 122 may include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, in some cases, uncorrectable errors may occur. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0056] The storage device includes code such as a set of instructions, and a processor can operate to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor can access the code from the storage device 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0057] For example, controller 122 can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122c fetches boot code from ROM 122a or storage device 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0058] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0059] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0060] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices; non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0061] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0062] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0063] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0064] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0065] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0066] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0067] A three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., x, y and z directions, where the z direction is substantially perpendicular and the x and y directions are substantially parallel to the main surface of the substrate).

[0068] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., along the y-direction), each column having multiple memory elements. The columns can be arranged in a two-dimensional configuration, for example, in the xy-plane, resulting in a three-dimensional arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0069] By way of non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0070] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0071] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0072] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0073] Those skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described herein, but covers all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0074] Figure 2 Depicting Figure 1A The memory array 126 is a block of memory cells in an exemplary two-dimensional configuration. The memory array may include multiple blocks. Each exemplary block 200, 210 includes multiple NAND strings and corresponding bit lines, such as BL0, BL1... shared between blocks. Each NAND string is connected at one end to a drain-select gate (SGD), and the control gate of the drain-select gate is connected via a common SGD line. The NAND string is connected at its other end to a source-select gate, which is then connected to a common source line 220. Sixteen word lines, such as WL0 to WL15, extend between the source-select gate and the drain-select gate. In some cases, dummy word lines that do not contain user data may also be used in memory arrays adjacent to select-gate transistors. Such dummy word lines can shield edge data word lines from certain edge effects.

[0075] One type of non-volatile memory that can be provided in a memory array is floating-gate memory. See also Figure 3A and Figure 3B Other types of non-volatile memory can also be used. For example, charge-trapping memory cells use non-conductive dielectric materials instead of conductive floating gates to store charge in a non-volatile manner. See also Figure 4A and Figure 4B A three-layer dielectric composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is sandwiched between a conductive control gate and the surface of a semiconducting substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where electrons are captured and stored in a limited area. This stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided with a split-gate configuration, where a doped polysilicon gate extends above a portion of the memory cell channel to form a separate selection transistor.

[0076] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over a channel between the source and drain diffusion regions. The charge for one data bit is located in the dielectric layer adjacent to the drain, and the charge for the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0077] Figure 3A A cross-sectional view of an exemplary floating-gate memory cell in a NAND string is depicted. Bit lines or NAND string directions enter the page, and word lines direction is from left to right. For example, word line 324 extends across a NAND string that includes corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell is in a different corresponding NAND string. A polysilicon interlayer dielectric (IPD) layer 328 is also depicted. The control gate is a portion of the word line. Figure 3B The document provides a sectional view taken along line 329.

[0078] The control gate is wrapped around the floating gate, increasing the surface contact area between the control gate and the floating gate. This results in a higher IPD capacitance, leading to a higher coupling ratio, which makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells becomes smaller, leaving little space for the control gate and IPD between two adjacent floating gates. As an alternative, such as Figure 4A and Figure 4B As shown, planar or flat memory cells have been developed in which the control gate is flat or planar; that is, the control gate is not enclosed on a floating gate, and the only contact between the control gate and the charge storage layer is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is fabricated to be thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This method avoids the ballistic electron transport problem, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0079] Figure 3B It depicts the section taken along line 329. Figure 3AA cross-sectional view of the structure. The NAND string 330 includes an SGS transistor 331, exemplary memory cells 300, 333...334 and 335, and an SGD transistor 336. As an example of each memory cell, memory cell 300 includes a control gate 302, an IPD layer 328, a floating gate 304, and a tunnel oxide layer 305, and... Figure 3A Consistent. The pathways in the IPD layer of SGS and SGD transistors allow the control gate layer and floating gate layer to communicate. For example, the control gate layer and floating gate layer can be polysilicon, and the tunnel oxide layer can be silicon oxide. The IPD layer can be a stack of nitride (N) and oxide (O), such as in a NONON configuration.

[0080] NAND strings can be formed on a substrate including a p-type substrate region 355, an n-type well 356, and a p-type well 357. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type wells. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0081] Figure 4A A cross-sectional view of an exemplary charge-trapping memory cell in a NAND string is depicted. This view is taken in the word-line direction of the memory cell, which includes a planar control gate and a charge-trapping region, as... Figure 1A A 2D example of a memory cell in the memory cell array 126. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator such as a SiN film to store electrons, compared to floating-gate MOSFET technology which uses conductors such as doped polysilicon to store electrons. For example, a word line (WL) 424 extends across a NAND string, which includes corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. An IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layers 409, 407, and 408 are located below the word line. Each charge-trapping layer extends continuously within the corresponding NAND string.

[0082] Memory cell 400 includes a control gate 402, a charge trapping layer 404, a polysilicon layer 405, and a portion of a channel region 406. Memory cell 410 includes a control gate 412, a charge trapping layer 414, a polysilicon layer 415, and a portion of a channel region 416. Memory cell 420 includes a control gate 422, a charge trapping layer 421, a polysilicon layer 425, and a portion of a channel region 426.

[0083] A planar control gate is used here, instead of a control gate wrapped around a floating gate. One advantage is that the charge trapping layer can be made thinner than the floating gate. Additionally, memory cells can be placed closer together.

[0084] 4B depicts the section intercepted along line 429. Figure 4A A cross-sectional view of the structure. This view shows a NAND string 430 with a planar control gate and a charge trapping layer. The NAND string 430 includes an SGS transistor 431, exemplary memory cells 400, 433...434 and 435, and an SGD transistor 435.

[0085] NAND strings can be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well 457. A channel voltage Vch can be directly applied to the channel region of the substrate. The memory cell 400 includes a control gate 402 and an IPD layer 428, a polysilicon layer 405, a tunnel layer 409, and a channel region 406 above a charge trapping layer 404.

[0086] For example, the control gate layer can be polysilicon, and the tunnel layer can be silicon oxide. The IPD layer can be a stack of high-k dielectrics (such as AlOx or HfOx) that helps increase the coupling ratio between the control gate layer and the charge trapping layer or charge storage layer. The charge trapping layer can be, for example, a mixture of silicon nitride and silicon oxide.

[0087] SGD and SGS transistors have the same configuration as memory cells, but with a longer channel length to ensure that current is cut off in the suppressed NAND string.

[0088] In this example, layers 404, 405, and 409 extend continuously within the NAND string. In another approach, portions of layers 404, 405, and 409 located between control gates 402, 412, and 422 may be removed, thereby exposing the top surface of channel 406.

[0089] Figure 5A Depicting Figure 1AAn exemplary block diagram of a sensing block SB1 is provided. In one method, the sensing block includes multiple sensing circuits. Each sensing circuit is associated with a data latch. For example, exemplary sensing circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one method, different corresponding sensing blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sensing circuits to be partitioned and processed by a corresponding processor in each sensing block. For example, a sensing circuit controller 560 in SB1 can communicate with the group of sensing circuits and latches. The sensing circuit controller may include a precharge circuit 561 that provides a voltage to each sensing circuit for setting a precharge voltage. In one possible method, for example via a database 503 and a local bus such as Figure 5B LBUS1 or LBUS2 in the circuit independently provides voltage to each sensing circuit. In another possible method, for example via... Figure 5B Line 505 in the middle simultaneously provides a common voltage to each sensing circuit. The sensing circuit controller may also include a memory 562 and a processor 563. Furthermore, it can be combined with... Figure 2 The memory 562 may store code that can be executed by a processor to perform the functions described herein. These functions may include reading latches associated with the sensing circuitry, setting bit values ​​in the latches, and providing voltages for setting pre-charge levels in the sensing nodes of the sensing circuitry. Further exemplary details of the sensing circuitry controller and sensing circuits 550a and 551a are provided below.

[0090] Figure 5B Depicting Figure 1A Another exemplary block diagram of the sensing block SB1. The sensing circuit controller 560 is also present. Figure 5AThe diagram illustrates communication between multiple sensing circuits, including exemplary sensing circuits 550a and 551a. Sensing circuit 550a includes latch 550b, which includes a trip latch 526, an offset verification latch 527, and a data status latch 528. The sensing circuit also includes a voltage clamping structure 521, such as a transistor, which sets a pre-charge voltage at sensing node 522. A sensing node-to-bit line (BL) switch 523 selectively allows the sensing node to communicate with bit line 525, for example, the sensing node is electrically connected to the bit line such that the sensing node voltage can decay. Bit line 525 is connected to one or more memory cells, such as memory cell MC1. The voltage clamping structure 524 can set a voltage on the bit line, for example, during sensing operation or during programming voltage. A local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as, in some cases, with latch 550b and the voltage clamping structure. To communicate with sensing circuit 550a, the sensing circuit controller provides voltage to transistor 504 via line 502 to connect LBUS1 to data bus DBUS 503. Communication may include sending data to and / or receiving data from the sensing circuit.

[0091] For example, the sensing circuit controller can communicate with different sensing circuits in a time-multiplexed manner. In one approach, line 505 can be connected to a voltage clamping structure in each sensing circuit.

[0092] Sensing circuit 551a includes latches 551b, including a trip latch 546, an offset verification latch 547, and a data status latch 548. A voltage clamping structure 541 is used to set a pre-charge voltage at sensing node 542. A sensing node-to-bit line (BL) switch 543 selectively allows the sensing node to communicate with bit line 545, and a voltage clamping structure 544 can set a voltage on the bit line. Bit line 545 is connected to one or more memory cells, such as memory cell MC2. Local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as latches 551b and the voltage clamping structure in some cases. To communicate with sensing circuit 551a, the sensing circuit controller provides voltage to transistor 506 via line 501 to connect LBUS2 to DBUS.

[0093] The sensing circuit 550a may be a first sensing circuit including a first trip latch 526, and the sensing circuit 551a may be a second sensing circuit including a second trip latch 546.

[0094] Sensing circuit 550a is an example of a first sensing circuit including a first sensing node 522, wherein the first sensing circuit is associated with a first memory cell MC1 and a first bit line 525. Sensing circuit 551a is an example of a second sensing circuit including a second sensing node 542, wherein the second sensing circuit is associated with a second memory cell MC2 and a second bit line 545.

[0095] Figure 6A yes Figure 1A This is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of a memory array 126. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements), and a peripheral region 604 having circuitry for use by the blocks. For example, the circuitry may include a voltage driver 605 connectable to a control gate layer of the block. In one approach, control gate layers at a common height within the blocks are commonly driven. The substrate 601 may also carry circuitry beneath the blocks, along with one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry. Each block includes a stacked region of memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to the upper metal layers to form connections with conductive paths. Although four blocks are depicted as an example, two or more blocks extending in the x and / or y directions can be used.

[0096] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device.

[0097] Figure 6B Depicting Figure 6A An exemplary cross-sectional view of a portion of a block. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, in addition to data word line layers (word lines) WLL0 to WLL10, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL19. Furthermore, regions comprising NAND strings NS1 and NS2 are depicted in the stack. Each NAND string encompasses a memory via 618 or 619, which is filled with material forming memory cells adjacent to the word lines. Figure 6DThe stacked region 622 is shown in more detail below.

[0098] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack, such as to connect the source line to a line above the stack. The slots may be used during word line formation and subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0099] Figure 6C Depicting Figure 6B A diagram showing the diameter of memory holes in a stack. The vertical axis is perpendicular to... Figure 6B The stacking alignment is shown, and the widths (wMH), such as diameters, of memory holes 618 and 619 are depicted. Figure 6A Word line layers WLL0 to WLL10 are repeated as examples, and are located at corresponding heights z0 to z10 in the stack. In such memory devices, the memory vias etched through the stack have very high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory via can vary along the length of the via. Typically, the diameter of the memory via gradually decreases from its top to its bottom. That is, the memory via is tapered, narrowing at the bottom of the stack. In some cases, it narrows slightly at the top of the hole near the select gate, so that the diameter of the memory via slightly widens before gradually decreasing from its top to its bottom.

[0100] Due to the non-uniformity of memory via width, the programming speed, including the programming slope and erase speed of the memory cell, can vary based on the location of the memory cell along the memory via (e.g., based on the height of the memory cell in the stack). For smaller diameter memory vias, the electric field across the tunnel oxide is relatively strong, resulting in relatively high programming and erase speeds. One approach is to define a group of adjacent word lines with a diameter similar to the memory via (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line in the group. Different groups can have different optimized verification schemes.

[0101] Figure 6D Depicting Figure 6BA close-up view of the stacked region 622. Memory cells are formed at different levels of the stack at the intersection of word line layers and memory vias. In this example, SGD transistors 680 and 681 are disposed above dummy memory cells 682 and 683 and data memory cell MC. Multiple layers may be deposited along the sidewalls (SW) of memory via 630 and / or within each word line layer (e.g., using atomic layer deposition). For example, each column (e.g., pillars formed by material within the memory via) may include a charge trapping layer or film 663 (such as SiN or other nitrides), a tunnel layer 664, a polysilicon bulk or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / bulk high-k material 660, a metal blocking layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided within the memory via. In other methods, some layers within the layer can be in the control gate layer. Additional pillars are similarly formed in different memory vias. These pillars can form pillared active regions (AA) of the NAND string.

[0102] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0103] Each memory via may be filled with multiple annular layers, including a barrier oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each memory via is filled with the host material, and the multiple annular layers are located between the core region and the word line in each memory via.

[0104] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate. Furthermore, NAND strings are provided by multiple word line layers stacked one on top of the other and separated from each other by dielectric layers.

[0105] Figure 7A Depicting Figure 6B A top view of an exemplary word line layer WLL0 of a stack. As mentioned, a 3D memory device may include a stack of alternating conductive and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layer for the SG transistors is the SG layer, and the layer for the memory cells is the word line layer. Furthermore, memory vias are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0106] In a 3D memory device, a block (BLK) can be divided into sub-blocks, each of which includes a set of NAND strings sharing a common SGD control line. See, for example, the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Sub-blocks SBa, SBb, SBc, and SBd may also be referred to herein as strings of memory cells for word lines. As described, a string of memory cells for word lines may include multiple memory cells belonging to the same sub-block and multiple memory cells also disposed in the same word line layer and / or configured to have their control gates biased by the same word line and / or utilizing the same word line voltage.

[0107] Furthermore, the word line layer within a block can be divided into regions. Each region in a corresponding sub-block can extend between slits periodically formed in the stack to process the word line layer during the fabrication process of the memory device. This processing may include replacing the sacrificial material of the word line layer with metal. Generally, the distance between the slits should be relatively small to account for the limitations on the distance that the etchant can travel laterally to remove the sacrificial material and the distance that the metal can travel to fill the voids created by removing the sacrificial material. For example, the distance between the slits may allow for several rows of memory vias between adjacent slits. The layout of the memory vias and slits should also consider the limitations on the number of bit lines that can extend across regions when each bit line is connected to a different memory cell. After processing the word line layer, the slits may optionally be filled with metal to provide interconnects through the stack.

[0108] This diagram, like others, may not be drawn to scale. In practice, the area may be longer in the x-direction than depicted to accommodate additional memory holes, relative to the y-direction.

[0109] In this example, four rows of memory holes exist between adjacent slits. A row here is a set of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are arranged in an interlaced pattern to increase the density of the memory holes. The word line layer, or word line, is divided into regions WLL0a, WLL0b, WLL0c, and WLL0d, each connected via connector 713. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. The connector is then connected to a voltage driver for the word line layer. Region WLL0a has exemplary memory holes 710 and 711 along line 712. Region WLL0b has exemplary memory holes 714 and 715. Region WLL0c has exemplary memory holes 716 and 717. Region WLL0d has exemplary memory holes 718 and 719. Memory holes are also... Figure 7BAs shown in the diagram. Each memory hole can be part of a corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, respectively.

[0110] Each circle represents a cross-section of a memory aperture at a word line layer or SG layer. Exemplary circles shown in dashed lines represent memory cells provided by material in the memory aperture and adjacent word line layers. For example, memory cells 720 and 721 are in WLL0a, memory cells 724 and 725 are in WLL0b, memory cells 726 and 727 are in WLL0c, and memory cells 728 and 729 are in WLL0d. These memory cells are at a common height in the stack.

[0111] Metal-filled slots 701, 702, 703, and 704 (e.g., metal interconnects) may be located between and adjacent to the edges of regions WLL0a to WLL0d. The metal-filled slots provide a conductive path from the bottom to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductor above the stack, which in turn connects to a voltage driver in a peripheral region of the memory device. See also... Figure 8A learn Figure 7A More details on the sub-blocks SBa to SBd.

[0112] Figure 7B Depicting Figure 6B A top view of an exemplary top dielectric layer DL19 of the stack. The dielectric layer is divided into regions DL19 a, DL19 b, DL19 c, and DL19 d. Each region can be connected to a corresponding voltage driver. This allows simultaneous programming of a group of memory cells in a region of the word line layer, where each memory cell is located in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to enable or disable programming during each programming voltage.

[0113] Region DL19a has exemplary memory holes 710 and 711 along line 712a coinciding with bit line BL0. A plurality of bit lines extend above and connect to the memory holes, as indicated by the “X” symbol. BL0 connects to a set of memory holes including memory holes 711, 715, 717, and 719. Another exemplary bit line BL1 connects to a set of memory holes including memory holes 710, 714, 716, and 718. Also depicted... Figure 7A Metal-filled slits 701, 702, 703, and 704 extend vertically through the stack. The position lines can be numbered sequentially from BL0 to BL23 across the DL19 layers in the x-direction.

[0114] Different subsets of the bit lines are connected to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to cells in the first row at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to cells in the adjacent row of cells next to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to cells in the first row at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to cells in the adjacent row of cells next to the first row at the left edge.

[0115] Figure 8A Depicting Figure 7A The example NAND string in sub-blocks SBa to SBd. Sub-blocks with Figure 6B The structure is consistent. The conductive layers in the stack are depicted for reference on the left-hand side. Each sub-block includes multiple NAND strings, with one example NAND string depicted. For example, SBa includes the exemplary NAND string NS0_SBa, SBb includes the exemplary NAND string NS0_SBb, SBc includes the exemplary NAND string NS0_SBc, and SBd includes the exemplary NAND string NS0_SBd.

[0116] Additionally, NS0_SBa includes SGS transistors 800 and 801, dummy memory cells 802 and 803, data memory cells 804, 805, 806, 807, 808, 809, 810, 811, 812, 813 and 814, dummy memory cells 815 and 816, and SGD transistors 817 and 818.

[0117] NS0_SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833 and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0118] NS0_SBc includes SGS transistors 840 and 841, dummy memory cells 842 and 843, data memory cells 844, 845, 846, 847, 848, 849, 850, 851, 852, 853 and 854, dummy memory cells 855 and 856, and SGD transistors 857 and 858.

[0119] NS0_SBd includes SGS transistors 860 and 861, dummy memory cells 862 and 863, data memory cells 864, 865, 866, 867, 868, 869, 870, 871, 872, 873 and 874, dummy memory cells 875 and 876, and SGD transistors 877 and 878.

[0120] At a given height within a block, a set of memory cells in each sub-block is located at a common height. For example, a set of memory cells (including memory cell 804) is located in multiple memory cells formed by tapered memory holes along a stack of alternating conductive and dielectric layers. This set of memory cells is located at a specific height z0 in the stack. Another set of memory cells (including memory cell 824) connected to a word line (WLL0) is also located at a specific height. In another approach, a set of memory cells (e.g., including memory cell 812) connected to another word line (e.g., WLL8) is located at another height (z8) in the stack.

[0121] Figure 8B Another exemplary view of NAND strings within a sub-block is depicted. The NAND strings include NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, which have 48 word lines WL0 to WL47 in this example. Each sub-block includes a set of NAND strings extending along the x-direction and having a common SGD line, such as SGD0, SGD1, SGD2, or SGD3. In this simplified example, each NAND string contains only one SGD transistor and one SGS transistor. The NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd are located in sub-blocks SBa, SBb, SBc, and SBd, respectively. Furthermore, an exemplary group of word lines G0, G1, and G2 is depicted.

[0122] Figure 8C A schematic diagram of three types of interleaved string architectures 101, 103, and 105 for BiCS memories (e.g., NAND) is shown in general. Referring to string architecture 101, strings are shown in rows 107-0 to 107-7 of architecture 101. Each row is shown with four ends of a string. Strings may be connected to adjacent strings at the ends (not visible below this view). The first set of rows 107-0 to 107-3 is shown to the left of dummy row 108. The second set of rows 107-4 to 107-7 is shown to the right of dummy row 108. Dummy row 108 separates the two sets of rows in eight interleaved rows. Source line 109 is located at the edge of the first set and away from dummy row 108. Source line 109-2 is located at the edge of the second set and away from dummy row 108 and source line 109.

[0123] The interleaved string architectures 103 and 105 of the BiCS memory are similar to the interleaved string architecture 101, except that the former adds additional groups. Architecture 103 is twice the size of architecture 101 and consists of sixteen strings, with each group of four strings separated by dummy lines. Architecture 105 is larger than both architectures 101 and 103. Architecture 105 consists of twenty strings, with each group of four strings separated by dummy lines 108.

[0124] These architectures 101, 103, and 105 may include chips beneath an array structure, for example, control circuitry beneath a memory array that may include groups of memory strings. Utilizing the chips beneath the array structure, the strings may include direct strap contacts for source lines for read and erase operations.

[0125] When programming memory cells, NWIs from adjacent memory cells can cause a shift and widening of the Vth distribution. For example, using conventional full-sequence programming, after PD, NWIs will result in memory cells with adjacent word lines in a high state (e.g., WLn+1) having a higher Vth and memory cells with adjacent word lines in a low state having a lower Vth, thus widening the Vth distribution of the data state. After HTDR, the Vth is shifted even further downwards for memory cells with adjacent word lines in a low state (e.g., WLn+1 or WLn-1) compared to memory cells with adjacent word lines in a high state due to lateral DR.

[0126] As previously mentioned, to maintain valid data information and minimize FBC, conventional methods for compensating for DR loss during read operations include applying different read pass voltage (VREADK) values ​​at WLn+1 or different read voltage (VCG) values ​​at WLn (selected word line). Different VREADK or VCG values ​​can be applied to each of multiple "regions" to modulate the Vth distribution location of WLn. These regions are formed based on the data states of adjacent memory cells at WLn+1. WLn+1 can be read before performing a read operation on WLn to obtain WLn+1 state information. This helps tighten the Vth distribution. VREADK can also be used to compensate for device variations with different WL-WL distances.

[0127] During a read operation, the bias conditions for the word lines may include the selected word line WLn receiving a read voltage VCGR, which may be applied at one of the read compare levels. Additionally, word lines WLn-1 and WLn+1 adjacent to the selected word line WLn receive a read pass voltage VREADK, and the remaining word lines receive a read pass voltage VREAD. VREAD is a read pass voltage applied at a level sufficient to turn on a cell in any programming state. For example, VREAD may be applied at a level higher than the highest expected threshold voltage of the memory cell in the highest programming state. VREADK is also a read pass voltage applied to turn on a memory cell in any programming state. VREADK may be applied at a level higher than VREAD to compensate for lower voltages at adjacent word lines due to the lower VCGR voltage applied to the selected word line. The remaining word lines are each adjacent to another word line that receives a VREAD voltage. In some cases, VREADK may be equal to VREAD.

[0128] The grouping techniques used in the specific implementations of the conventional methods cited above are not optimal. Specifically, these methods only consider WLn+1 in the identification region. For example, Figure 12A and Figure 12B Exemplary representations of regions for one- and two-digit read recognition are provided; Figure 12A and Figure 12B The regions depicted are identified based on the WLn+1 data state and do not consider the data state of the WLn-1 memory cells. For example, in Figure 12A In this context, data states 'Er' to 'D' of WLn+1 are defined as region one, encompassing all data states of WLn-1. Additionally, in... Figure 12A In this context, data states 'E' to 'G' of WLn+1 are defined as zone two, encompassing all data states of WLn-1. However, the data state combinations 'Er' / X / 'Er' and 'G' / X / 'G' of WLn+1 / WLn / WLn-1 should not be grouped within the same zone because WLn+1 / WLn / WLn-1 as 'Er' / X / 'Er' will possess a strong lateral electric field to extract charge from states far from the object being disturbed (where 'Er' / X / 'Er' can constitute the lower tail); while WLn+1 / WLn / WLn-1 as 'G' / X / 'G' can constitute the upper tail and contribute charge to the object being disturbed. For example, as... Figure 12A It is evident that relying solely on the WLn+1 data state to identify regions allows data state combinations such as 'Er' / 'Er' of WLn+1 / WLn-1 to reside in the same region as 'D' / 'G' of WLn+1 / WLn-1. Similarly, as Figure 12B It can be seen that data state combinations such as 'Er' / 'Er' of WLn+1 / WLn-1 can be located in the same position as... Figure 12BThe 'A' / 'G' of WLn+1 / WLn-1 in the four depicted regions are the same. By including such combinations of data states in the same regions, the Vth distribution can be widened and the minimum VREADK that can be imposed can be limited.

[0129] Figure 13A shows an exemplary graphical representation of the overall Vth distribution 1302 and four regions identified within the overall Vth distribution based on the data states of memory cells based on adjacent word lines (e.g., WLn+1). As shown in Figure 13B, during a read of WLn, these regions can be aligned with the center by applying different read pass voltage (VREADK) values ​​at WLn+1 or different read voltage (VCG) values ​​at WLn (selected word line). Different VREADK or VCG values ​​can be applied to each of the multiple regions to modulate the WLn Vth distribution position. Grouping certain data state combinations (e.g., 'Er' / 'Er' and 'G' / 'G') into the same region may result in a wider region distribution, leading to a wider overall Vth distribution when region alignment is used to compensate for NWI and lateral DR effects.

[0130] To address the aforementioned issues, the embodiments described herein involve Look-Ahead Adjacency (LNA) prefetching, which groups the most similar memory cells into a region, resulting in a more compact final Vth distribution after alignment. The Look-Ahead Adjacency (LNA) prefetching method involves reading the state information of both WLn+1 and WLn-1 before reading WLn, and classifying combinations of the data states of the memory cells in WLn+1 and WLn-1 into different regions. Each region may correspond to a data retention compensation scheme, and a read operation may be performed on WLn, including applying each data retention compensation scheme corresponding to any identified region. According to the embodiments described herein, LNA prefetching may include reading logical WLn+1 first and then logical WLn-1 for any read bit, or reading logical WLn-1 first and then logical WLn+1 for any read bit. In some embodiments, LNA prefetching may include reading logical WLn+1 and logical WLn-1 simultaneously for any read bit.

[0131] To explore the foregoing in more detail, the following will now be described. Figure 14 . Figure 14 This is a flowchart of a method 1400 for performing an advance look-up of adjacent data. In some implementations, method 1400 may be implemented by a controller, control circuitry, a processor, etc., as described elsewhere in this document. Figure 14As shown, method 1400 begins at step 1402. At step 1402, data states of a first set of memory cells for a first adjacent word line in a set of word lines and a second set of memory cells for a second adjacent word line in the same set of word lines are determined, wherein each data state is any one of a plurality of data states that the first and second sets of memory cells are configured to store. The first and second adjacent word lines are adjacent to selected word lines in the set of word lines. For example, for illustrative purposes, assume... Figure 8A WLL1 in the text is the selected word line, then the controller (such as...) Figure 4A The sensing circuit controller 560 described herein or Figure 1A The controller 122 described herein can determine the data status of memory cells 806, 826, 846, and 866 (of word line WLL2) that are adjacent to memory cells 805, 825, 845, and 865 of the selected word line WLL1, and determine the data status of memory cells 804, 824, 844, and 864 (of word line WLL0) that are adjacent to memory cells 805, 825, 845, and 865 of the selected word line WLL1.

[0132] More specifically, the controller can identify the data state of memory cells included in each corresponding adjacent word line by performing one or more read operations (sometimes referred to as sensing operations). The controller can perform read operations, for example, by referring to a data structure supported by a data state latch (e.g., data state latch 548) to identify the data state of memory cells in physically adjacent word lines (e.g., WLn-1, WLn+1, etc.) of the word line (e.g., WLn). The data structure can be used to store the data state values ​​of bits of adjacent memory cells (e.g., memory cells in physically adjacent word lines). Data states can include an erased data state indicating that one or more bits of the memory cell have not been programmed, or a programmed data state indicating that one or more bits have been programmed (e.g., programmed to a value of zero or one). Using a 3-bit memory cell architecture as an example, one data state may remain among the erased data state ER and seven higher (or programmed) data states (represented by data state A, data state B, ..., data state G).

[0133] In some embodiments, performing a read operation may include identifying one or more data states of memory cells on physically adjacent word lines. In some embodiments, performing a read operation may include identifying the data states of multiple memory cells on physically adjacent word lines. In some embodiments, performing a read operation may include identifying the data states of multiple memory cells on multiple adjacent word lines (e.g., physically adjacent WLn-1, second adjacent word line WLn+1, etc.).

[0134] In some implementations, determining the data state of the first set of memory cells on the first adjacent word line and the second set of memory cells on the second adjacent word line includes reading the state information of both WLn+1 and WLn-1 before reading WLn. In some implementations, determining the data state of the first set of memory cells on the first adjacent word line and the second set of memory cells on the second adjacent word line may include reading logic WLn+1 first and then logic WLn-1 for any read bit, or reading logic WLn-1 first and then logic WLn+1 for any read bit. For example, a prefetch can be performed on WLn+1 at the verification level BR / DR / FR, and the read result can be stored in a two-bit data latch. Then, a prefetch can be performed on WLn-1 at the verification level BR / DR / FR, and the read result can be stored in a two-bit data latch. Arbitrary CMOS data latch operations can be performed to compress a four-bit DL into a two-bit DL for use in a four-zone definition. As another example, in the case of eight states, a prefetch can be performed, including continuing to read WLn+1 seven times, and then continuing to read WLn-1 seven times. The read information can be collected and stored in a data rack. The read information may include seven bits of information, WLn+1 and WLn-1. CMOS logic can be used to combine the information into a single area.

[0135] In some embodiments, determining the data state of a first set of memory cells on a first adjacent word line and a second set of memory cells on a second adjacent word line may include simultaneously reading logic WLn+1 and logic WLn-1 for any read bit. For example, embodiments described herein include simultaneously reading the states of multiple word lines (e.g., WLn+1 and WLn-1) to group them into different regions. This may include simultaneously applying the same verification level on WLn+1 and WLn-1, and applying VREAD on all other word lines. Simultaneously sensing multiple word lines helps save read time. According to embodiments described herein, simultaneously sensing multiple word lines includes applying different read levels to different word lines (e.g., two word lines, three word lines, or any number of word lines) during the read process. In some embodiments, during the read process, a sensor amplifier detects bit line currents that are turned on only when all word lines are on. That is, the threshold voltage of each word line is lower than each of the applied read levels.

[0136] In some implementations, simultaneous sensing of multiple word lines may include dual-word-line sensing. For example, this could include dual-word-line sensing that simultaneously prefetches logic WLn+1 / WLn-1 at verification levels CR / ER / GR. Note that due to the weaker on / off state of dual WL sensing, the verification levels of WLn+1 / WLn-1 may include some offset compared to a single WL read. The prefetch results are stored in a two-bit data latch that can be used for a four-zone definition. Each zone may contain threshold voltage information for WLn+1 and WLn-1 (in an L-shape) (e.g., ...). Figure 16 (As shown). To further illustrate, WLn+1 and WLn-1 can be grouped together as a single cell for reading, and all other memory cells along the bit line are biased to VREADK. According to NAND logic, the bit line is only turned on when both cells are above the read level (e.g., 30nA).

[0137] In some implementations, when the NWI effect is negligible, such as for reverse sequential programming and fuzzy fine programming, the WLn+1 and WLn-1 read levels can be the same and symmetrical. In contrast, when the NWI effect is present along the WLn+1 direction, the WLn+1 and WLn-1 read levels can be different to define the boundaries between regions forming asymmetrical region shapes (e.g., ...). Figure 17 and Figure 18 (As depicted). According to the embodiments disclosed herein, forming an asymmetric region may include applying a verification level CR / DR / FR at WLn+1, and a verification level ER / VREAD / VREAD at WLn-1, and the same VREAD at all other word lines. In this case, the bit line has a chance to turn on only when both WLn+1 and WLn-1 pass the specific verification level.

[0138] exist Figure 14 In this method 1400, step 1404 is further included. In step 1404, for each combination of data states, one of a plurality of regions is identified, wherein each combination of data states includes the data states of memory cells in a first group of memory cells and the data states of memory cells in a second group of memory cells, and the memory cell in the first group of memory cells and the memory cell in the second group of memory cells are adjacent to memory cells in a third group of memory cells of a selected word line. Each of the plurality of regions corresponds to a data retention compensation scheme.

[0139] For example, for illustrative purposes, let's assume... Figure 8A WLL1 in the text is the selected word line, then the controller (such as...) Figure 4A The sensing circuit controller 560 described herein or Figure 1AThe controller 122 described herein can identify regions of data state combinations determined for memory cells 806, 826, 846, and 866 of word line WLL2 and for memory cells 804, 824, 844, and 864 of word line WLL0. Each of the plurality of regions corresponds to a data retention compensation scheme. The data retention compensation scheme can be applied during one or more read operations to be performed on a selected word line WLL1, such that the data retention compensation scheme corresponding to each of the plurality of regions can be used to counteract interference that memory cells 806, 826, 846, and 866 of word lines WLL2 and 804, 824, 844, and 864 of word lines WLL0 would otherwise have on memory cells 805, 825, 845, and 865 of the selected word line WLL1. In some implementations, for example, WLn+1 / WLn-1 is treated as a single current readout, and when the current is above or below a certain level, the corresponding combination of WLn+1 and WLn-1 is classified into a zone.

[0140] Figure 15 and Figure 16 An example table of zone mappings is provided. For example... Figure 15 As shown in the table, for example, the data states 'Er', 'A', 'B', and 'C' of adjacent memory cells of WLn+1 and the data states 'Er', 'A', 'B', and 'C' of adjacent memory cells of WLn-1 are mapped to the first region, and the data states 'D', 'E', 'F', and 'G' of adjacent memory cells of WLn+1 and the data states 'D', 'E', 'F', and 'G' of adjacent memory cells of WLn-1 are mapped to the second region. The boundary shape can be any shape (e.g., diagonal, L-shaped, etc.).

[0141] For example, Figure 16 The table depicts the data states 'Er' and 'A' of adjacent memory cells of WLn+1 and WLn-1 mapped to the first region. The data states 'B' and 'C' of adjacent memory cells of WLn+1 and WLn-1 are mapped to the second region. The data states 'D' and 'E' of adjacent memory cells of WLn+1 and WLn-1 are mapped to the third region. The data states 'F' and 'G' of adjacent memory cells of WLn+1 and WLn-1 are mapped to the fourth region. (The table is repeated in the original text.) Figure 16 As shown, boundary 1602 separates two adjacent zones (i.e., the third zone and the fourth zone).

[0142] In some implementations, when the NWI effect is negligible, such as for reverse sequential programming and fuzzy fine programming, the WLn+1 and WLn-1 read levels can be identical and symmetrical. For example, as Figure 16 The described method allows for a prefetch of WLn+1 at verification levels BR / DR / FR, with the read result stored in a two-bit data latch. Similarly, a prefetch of WLn-1 at verification levels BR / DR / FR can be performed, with the read result also stored in a two-bit data latch. Arbitrary CMOS data latch operations can be performed to compress a four-bit DL into a two-bit DL for use in four-zone definitions.

[0143] In contrast, when there is an NWI effect along the WLn+1 direction and a lateral DR effect along the diagonal direction, the WLn+1 and WLn-1 read levels can be different to define the boundaries between regions forming asymmetrical region shapes (e.g., Figure 17 and Figure 18 (As depicted). For example, Figure 17 The table depicts the diagonal grouping of data state combinations mapped to the four zones. For example... Figure 17 As described, different combinations of the data states of adjacent memory cells in WLn+1 and WLn-1 are mapped to four different regions. For example, a combination of the data states 'Er' of adjacent memory cells in WLn+1 and WLn-1 is mapped to the first region. Similarly, a combination of the data states 'D' of adjacent memory cells in WLn+1 and WLn-1 is mapped to the second region.

[0144] For example, Figure 17 The table depicts the horizontal and L-shaped groupings of data state combinations mapped to the four regions. These asymmetric regions can be identified by applying a verification level CR / DR / FR at WLn+1 and a verification level ER / VREAD / VREAD at WLn-1, with the same VREAD applied at all other word lines. In this case, the bit line has a chance to turn on only when both WLn+1 and WLn-1 pass the specific verification level.

[0145] like Figure 14 As further shown, method 1400 includes step 1406. In step 1406, a read operation is performed on the selected word line, including applying a data retention compensation scheme for each of a plurality of regions corresponding to any region identified in the third set of memory cells for the selected word line. For example, for illustrative purposes, assume... Figure 8A WLL1 in the text is the selected word line, then the controller (such as...) Figure 4A The sensing circuit controller 560 described herein or Figure 1AThe controller 122 described herein can perform a read operation on a selected word line WLL1, which applies a data retention compensation scheme for each of a plurality of areas identified when a read process is performed on memory cells 805, 825, 845, 865 of WLL1.

[0146] In some implementations, the data retention compensation scheme may include applying a different read pass voltage (VREADK) value at WLn+1 for each zone during the read process of WLn (e.g., applying VREADK 8.1V for zone 1, VREADK 8.7V for zone 2, VREADK 9.1V for zone 3, and VREADK 9.7V for zone 4). For example, Figure 19 Exemplary diagrams are provided illustrating how VREADK can be used to preview adjacent reads for one- and two-bit reads. For example... Figure 19 As described, WLn+1 and WLn-1 are read together by simultaneously applying VCG read levels, and different VREADK values ​​are applied at WLn+1 during the WLn read.

[0147] In some implementations, the data retention compensation scheme may include applying a different read voltage (VCG) value at WLn for each zone during the read process for WLn. For example, Figure 20 Exemplary illustrations are provided for using VCG to preview adjacent reads for one- and two-bit reads. For example... Figure 20 As described, WLn+1 and WLn-1 are read together by simultaneously applying VCG read levels, and different VCG values ​​are applied at WLn during the WLn read.

[0148] Figure 21 Another exemplary implementation waveform for previewing adjacent data for two-bit reads is provided. Figure 21 In the process, VCG_GR is applied on WLn+1 / n-1, while VREAD is applied on all other WLs. The timing control parameters T_BR, T_DR, and T_FR in CLKSA are used to read when the S / A flips (meaning high current). For example, if the read time is less than T_BR, the S / A flips. The identified zone is closer to... Figure 18 The upper left of the table. If the read time is greater than T_FR, the S / A does not flip, which means the current is very small, making the state closer. Figure 18 The lower right part of the table shows how all bit lines are grouped into four regions, with a different VREADK applied to each region, and even a different VREADK for each WLn state. This results in improved HTDR.

[0149] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A storage device, the storage device comprising: A non-volatile memory, the non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines; as well as A controller, coupled to the non-volatile memory, is configured to: Determine the data states of the first group of memory cells of the first word line and the second group of memory cells of the second word line in the set of word lines, wherein each data state is any one of a plurality of data states that the first group of memory cells and the second group of memory cells are configured to store, and the first word line and the second word line are adjacent to a selected word line in the set of word lines; For each combination of data states, one of multiple regions is identified. Each combination of data states includes the data states of memory cells in the first group of memory cells and the data states of memory cells in the second group of memory cells. The memory cells in the first group of memory cells and the memory cells in the second group of memory cells are adjacent to the memory cells in the third group of memory cells of the selected word line. Each of the multiple regions corresponds to a data retention compensation scheme. as well as Performing a read operation on the selected word line includes applying a data retention compensation scheme for each of the plurality of areas identified for the third set of memory cells for the selected word line.

2. The storage device of claim 1, wherein determining the data state of the first set of memory cells of the first word line and the second set of memory cells of the second word line includes performing read operations on the first word line and the second word line at substantially similar times.

3. The storage device according to claim 1, wherein determining the data state of the first group of memory cells of the first word line and the second group of memory cells of the second word line includes sequentially performing read operations on the first word line and the second word line.

4. The storage device of claim 1, wherein applying each data retention compensation scheme comprises: A first read-through voltage value is applied at the first word line for the first of the plurality of zones; as well as A second read pass voltage value is applied at the first word line for the second of the plurality of regions, wherein the first read pass voltage value is different from the second read pass voltage value.

5. The storage device of claim 1, wherein applying each data retention compensation scheme includes applying a different read voltage value at the selected word line for each of the plurality of regions, each region being identified for the third set of memory cells of the selected word line.

6. The storage device of claim 1, wherein each data state combination of the first region of the plurality of regions includes data states of memory cells in the first group of memory cells from a first set of data states and data states of memory cells in the second group of memory cells from a second set of data states, wherein the first set of data states includes the same data states as the second set of data states.

7. The storage device of claim 6, wherein each data state combination of the second region of the plurality of regions includes data states of memory cells in the first group of memory cells from a third group of data states and data states of memory cells in the second group of memory cells from a fourth group of data states, wherein the third group of data states includes at least one data state not included in the fourth group of data states.

8. A method of operating a memory device comprising a plurality of memory cells, the method comprising the steps of: Determine the data states of a first group of memory cells of a first word line in a set of word lines and a second group of memory cells of a second word line in the set of word lines, wherein each data state is any one of a plurality of data states that the first group of memory cells and the second group of memory cells are configured to store, and the first word line and the second word line are adjacent to a selected word line in the set of word lines. For each combination of data states, one of multiple regions is identified. Each combination of data states includes the data states of memory cells in the first group of memory cells and the data states of memory cells in the second group of memory cells. The memory cells in the first group of memory cells and the memory cells in the second group of memory cells are adjacent to the memory cells in the third group of memory cells of the selected word line. Each of the multiple regions corresponds to a data retention compensation scheme. as well as Performing a read operation on the selected word line includes applying a data retention compensation scheme for each of the plurality of areas identified for the third set of memory cells for the selected word line.

9. The method of claim 8, wherein determining the data state of the first set of memory cells of the first word line and the second set of memory cells of the second word line comprises performing read operations on the first word line and the second word line at substantially similar times.

10. The method of claim 8, wherein determining the data state of the first set of memory cells of the first word line and the second set of memory cells of the second word line comprises sequentially performing read operations on the first word line and the second word line.

11. The method of claim 8, wherein applying each data retention compensation scheme comprises: A first read-through voltage value is applied at the first word line for the first of the plurality of zones; as well as A second read pass voltage value is applied at the first word line for the second of the plurality of regions, wherein the first read pass voltage value is different from the second read pass voltage value.

12. The method of claim 8, wherein applying each data retention compensation scheme comprises applying a different read voltage value at the selected word line for each of the plurality of regions, each region being identified for the third set of memory cells of the selected word line.

13. The method of claim 8, wherein each data state combination of the first region of the plurality of regions includes data states of memory cells in the first group of memory cells from a first group of data states and data states of memory cells in the second group of memory cells from a second group of data states, wherein the first group of data states includes the same data states as the second group of data states.

14. The method of claim 13, wherein each data state combination of the second region of the plurality of regions includes data states of memory cells in the first group of memory cells from a third group of data states and data states of memory cells in the second group of memory cells from a fourth group of data states, wherein the third group of data states includes at least one data state not included in the fourth group of data states.

15. A controller that communicates with a plurality of memory cells of a memory device, the controller being configured to: Determine the data states of a first group of memory cells of a first word line in a set of word lines and a second group of memory cells of a second word line in the set of word lines, wherein each data state is any one of a plurality of data states that the first group of memory cells and the second group of memory cells are configured to store, and the first word line and the second word line are adjacent to a selected word line in the set of word lines. For each combination of data states, one of multiple regions is identified. Each combination of data states includes the data states of memory cells in the first group of memory cells and the data states of memory cells in the second group of memory cells. The memory cells in the first group of memory cells and the memory cells in the second group of memory cells are adjacent to the memory cells in the third group of memory cells of the selected word line. Each of the multiple regions corresponds to a data retention compensation scheme. as well as Performing a read operation on the selected word line includes applying a data retention compensation scheme for each of the plurality of areas identified for the third set of memory cells for the selected word line.

16. The controller of claim 15, wherein determining the data state of the first set of memory cells of the first word line and the second set of memory cells of the second word line includes performing read operations on the first word line and the second word line at substantially similar times.

17. The controller of claim 15, wherein determining the data state of the first set of memory cells of the first word line and the second set of memory cells of the second word line comprises sequentially performing read operations on the first word line and the second word line.

18. The controller of claim 15, wherein applying each data retention compensation scheme comprises: A first read-through voltage value is applied at the first word line for the first of the plurality of zones; as well as A second read pass voltage value is applied at the first word line for the second of the plurality of regions, wherein the first read pass voltage value is different from the second read pass voltage value.

19. The controller of claim 15, wherein applying each data retention compensation scheme includes applying a different read voltage value at the selected word line for each of the plurality of zones, each zone being identified for the third set of memory cells of the selected word line.

20. The controller of claim 15, wherein each data state combination of the first region of the plurality of regions includes data states of memory cells in the first group of memory cells from a first group of data states and data states of memory cells in the second group of memory cells from a second group of data states, wherein the first group of data states includes the same data states as the second group of data states.

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