A method for reducing storage module fault injection sets

Abstract

The present invention discloses a method for reducing a storage module fault injection set, which relates to the field of radiation effect simulation. A preset simulation test program is used to test the storage module of a target integrated circuit to obtain a read-write information file; a preset read-write information analysis algorithm is used to analyze the read-write information file to determine the invalid injection time interval of the storage module during the test; a fault injection validity analysis is performed on the fault injection set, and the injected faults in the invalid injection time interval and invalid circuit nodes in the fault injection set are removed to obtain a reduced fault injection set. The invalid injection time interval is determined by the read-write information file of the storage module, and the injected faults in the invalid injection time interval and invalid circuit nodes in the fault injection set are removed. The fault injection set is reduced from two dimensions, time and space, thereby reducing the simulation time cost and improving the simulation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of radiation effect simulation, and in particular to a method for reducing a fault injection set for a storage module. Background Art

[0002] Single-particle effects (SPEs) are the most significant radiation-induced factor affecting integrated circuits (ICs) and are one of the greatest reliability issues facing electronic devices today. As transistor feature sizes shrink and threshold voltages decrease, integrated circuits become more sensitive to SPEs. Memory modules (e.g., SRAM memory modules, register stacks, etc.) within an IC have a higher probability of experiencing soft errors than other circuit modules, necessitating an evaluation and reinforcement of their SPE resistance. Prior art methods analyze the soft error rate of integrated circuits in space radiation environments by injecting a large number of single-particle faults into the circuit for simulation evaluation. This method randomly generates a large number of single-particle faults, then injects faults into the target IC and observes whether the IC's response is abnormal. Finally, the number of IC faults is counted to calculate the IC's soft error rate.

[0003] Although large-scale single-event fault injection simulations have been proven to be an effective method for evaluating single-event effect resistance, some injected single-event faults can be masked by factors such as logic masking and timing masking, preventing abnormal circuit response results. This portion of fault injection is therefore ineffective and completely unnecessary, leading to high simulation time costs. Summary of the Invention

[0004] The purpose of the present invention is to solve the above-mentioned problems in the background technology and to propose a method for reducing the storage module fault injection set.

[0005] An embodiment of the present invention provides a method for reducing a storage module fault injection set, the method comprising:

[0006] Using a preset simulation test program to test the memory module of the target integrated circuit to obtain a read-write information file of the memory module;

[0007] Analyzing the read-write information file using a preset read-write information analysis algorithm to determine an invalid injection time interval of the storage module during the test;

[0008] Randomly generating injected faults at different times and different circuit nodes for the storage module as a fault injection set;

[0009] A fault injection validity analysis is performed on the fault injection set, and injected faults in the fault injection set that are in the invalid injection time interval and invalid circuit nodes are removed to obtain a reduced fault injection set; the invalid circuit nodes are circuit nodes that are not used by the simulation test program in the target integrated circuit.

[0010] Optionally, using a preset simulation test program to test the memory module of the target integrated circuit to obtain a read-write information file of the memory module includes:

[0011] The memory module of the target integrated circuit is tested using a preset simulation test program, and the read and write enable, read and write data, and read and write address changes of the memory module are recorded through the Verilog system function $fmonitor to obtain the read and write information file of the memory module.

[0012] Optionally, analyzing the read-write information file using a preset read-write information analysis algorithm to determine an invalid injection time interval of the storage module during the test includes:

[0013] Analyzing the read-write information file using a preset read-write information analysis algorithm, obtaining a time interval of a read operation and a write operation of each storage address in the storage module as an operation time interval, and using a time interval other than the operation time interval during the test as an interval time interval;

[0014] For each storage address, determining an adjacent interval time interval before the write operation as an invalid injection time interval;

[0015] An invalid hash array is generated using each storage address of the storage module as a key and the invalid injection time interval of the storage address as a value.

[0016] Optionally, performing a fault injection effectiveness analysis on the fault injection set, removing injected faults in the fault injection set that are in the invalid injection time interval and invalid circuit nodes, and obtaining a reduced fault injection set, including:

[0017] Performing fault injection validity analysis on the fault injection set, removing injected faults located at invalid circuit nodes in the fault injection set, and obtaining a first fault injection set;

[0018] Injection faults in the invalid injection time interval are removed from the first fault injection set according to the invalid hash array to obtain a reduced fault injection set.

[0019] Optionally, the value of the invalid hash array records the start time and end time of the invalid injection time interval.

[0020] Optionally, the storage module is an SRAM and / or a register file.

[0021] Based on an embodiment of the present invention, a method for reducing a storage module fault injection set is provided. The method uses a preset simulation test program to test the storage module of a target integrated circuit to obtain a read-write information file of the storage module; uses a preset read-write information analysis algorithm to analyze the read-write information file to determine the invalid injection time interval of the storage module during the test; randomly generates injection faults at different times and different circuit nodes for the storage module as a fault injection set; performs fault injection validity analysis on the fault injection set, removes the injection faults in the invalid injection time interval and invalid circuit nodes in the fault injection set, and obtains a reduced fault injection set; the invalid circuit nodes are circuit nodes not used by the simulation test program in the target integrated circuit. The invalid injection time interval is determined by the read-write information file of the storage module, and the injection faults in the invalid injection time interval and invalid circuit nodes in the fault injection set are removed, thereby reducing the fault injection set from both time and space dimensions, reducing simulation time cost, and improving simulation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below with reference to the accompanying drawings.

[0023] Figure 1 A flowchart of a method for reducing a storage module fault injection set provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of an invalid injection time interval provided by an embodiment of the present invention;

[0025] Figure 3 A schematic diagram of storing an invalid hash array provided by an embodiment of the present invention;

[0026] Figure 4 This is a flowchart of the fault injection effectiveness analysis provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] The embodiment of the present invention provides a method for reducing the storage module fault injection set. Figure 1 , Figure 1 A flowchart of a method for reducing a storage module fault injection set is provided in an embodiment of the present invention. The method includes:

[0029] S101, using a preset simulation test program to test a memory module of a target integrated circuit to obtain a read-write information file of the memory module.

[0030] S102: Analyze the read-write information file using a preset read-write information analysis algorithm to determine an invalid injection time interval of the storage module during the test.

[0031] S103: Randomly generate injected faults at different times and at different circuit nodes for the storage module as a fault injection set.

[0032] S104 , performing fault injection effectiveness analysis on the fault injection set, removing injected faults in invalid injection time intervals and invalid circuit nodes in the fault injection set, and obtaining a reduced fault injection set.

[0033] Invalid circuit nodes are circuit nodes in the target integrated circuit that are not used by the simulation test program.

[0034] A method for reducing a storage module fault injection set provided by an embodiment of the present invention determines invalid injection time intervals through a read-write information file of the storage module, removes injected faults in the invalid injection time intervals and invalid circuit nodes from the fault injection set, reduces the fault injection set in both time and space dimensions, reduces simulation time costs, and improves simulation efficiency.

[0035] In one implementation, invalid fault injection can be defined temporally and spatially. Temporally, the time interval during which no read or write operations are performed on the same address in the memory module can be defined as an invalid injection time interval. Spatially, circuit nodes not used by the test program can be defined as invalid circuit nodes.

[0036] In one implementation, the storage unit at the storage address is composed of circuit nodes. For example, the storage unit at the storage address 0xff contains 32 bits of data. The circuit of each bit is composed of some MOS transistors, and the source and drain ends of the MOS transistors are circuit nodes.

[0037] Based on whether the simulation test program execution process performs a read operation or a write operation on the data at the storage address, circuit nodes that are not related to program execution are determined to be invalid circuit nodes. Invalid circuit nodes are irrelevant to program execution and will not cause program execution errors.

[0038] In one implementation, the preset reading and writing information analysis algorithm can be written in Perl language.

[0039] In one implementation, the fault injection set is randomly generated for the storage module at different circuit nodes and different fault injection times.

[0040] In one embodiment, the storage module is an SRAM and / or a register file.

[0041] In one embodiment, S101 specifically includes:

[0042] The memory module of the target integrated circuit is tested using a preset simulation test program. The read and write enable, read and write data, and read and write address changes of the memory module are recorded through the Verilog system function $fmonitor to obtain the read and write information file of the memory module.

[0043] In one implementation, the read and write information file can be used to view the read and write operations of the storage module during the test, specifically the storage address of the read and write operations, the start and end times of the operations, and the type of operation, whether it is a read operation or a write operation.

[0044] In one embodiment, step S102 includes:

[0045] Step 1: Use a preset read-write information analysis algorithm to analyze the read-write information file, obtain the time interval of the read operation and write operation of each storage address in the storage module as the operation time interval, and use the time interval other than the operation time interval during the test as the interval time interval.

[0046] Step 2: For each storage address, determine the adjacent interval time interval before the write operation as the invalid injection time interval.

[0047] Step three: Generate an invalid hash array using each storage address of the storage module as a key and the invalid injection time interval of the storage address as a value.

[0048] In one implementation, see Table 1, which is a preset read-write information analysis algorithm. The input of the algorithm is the read-write information file of the storage module, and the output is an invalid hash array. The algorithm can be divided into two steps. The first step is to determine the operation time interval of the read operation and the write operation of each storage address, that is, to determine the start time and end time of the operation time interval; and then the interval time interval can be determined. The second step is to determine the adjacent interval time interval before the write operation as the invalid injection time interval. For example, the invalid injection time interval can be from the end time of the read operation to the start time of the adjacent write operation, or, the invalid injection time interval can be from the end time of the write operation to the start time of the adjacent write operation, or, if the first operation during the test is a write operation, the invalid injection time interval can be from the start time of the test to the start time of the first operation.

[0049] Since write operations can overwrite old data with new data, if a fault is injected during the invalid injection time interval, the fault will not be read by the program and will not affect program execution. Furthermore, the write operation will overwrite the fault with new data. Therefore, this type of fault injection fails to achieve the testing purpose. This type of fault can be removed from the fault injection set to reduce the size of the fault injection set.

[0050] The code in Table 1 uses only two examples: the end time of a read operation to the start time of an adjacent write operation, and the end time of a write operation to the start time of an adjacent write operation. Actual situations are not limited to these examples. Each line of the read / write information file records the time of the operation change. The time interval of the operation can be determined based on the information in the current line and the information in the next adjacent line. For example, line i records the start time of a read operation, and line i+1 records the end time of the read operation. Based on these two times, the time interval of the corresponding operation can be determined.

[0051] Table 1

[0052]

[0053]

[0054] In one implementation, see Figure 2 , Figure 2 A schematic diagram of an invalid injection time interval provided by an embodiment of the present invention. Figure 2 In this example, we only use the interval between the end of a read operation and the start of an adjacent write operation, and the interval between the end of a write operation and the start of an adjacent write operation. This is not the only practical example. The interval before the read operation is the non-invalid injection interval, meaning that injecting a fault within this interval can serve as a test.

[0055] In one implementation, the invalid injection time interval is stored in the form of a hash array, which facilitates quick query of whether the fault injection point is within the invalid injection time interval.

[0056] In one embodiment, step S104 includes:

[0057] Step 1: Perform fault injection validity analysis on the fault injection set, remove injected faults located at invalid circuit nodes in the fault injection set, and obtain a first fault injection set.

[0058] Step 2: Remove the injected faults in the invalid injection time interval from the first fault injection set according to the invalid hash array to obtain a reduced fault injection set.

[0059] In one implementation, removing injected faults in invalid circuit nodes from the fault injection set can reduce the fault injection set from a spatial dimension. Removing injected faults in invalid injection time intervals from the first fault injection set can reduce the fault injection set from a temporal dimension.

[0060] In one embodiment, the value of the invalid hash array records the start time and the end time of the invalid injection time interval.

[0061] In one implementation, see Figure 3 , Figure 3 A schematic diagram of the storage of an invalid hash array provided by an embodiment of the present invention. Taking the storage statement in the box in the figure as an example, the left side of the arrow is the storage address, the right side of the arrow is the three invalid injection time intervals, and T is used as the separation point between each two invalid injection time intervals. The first number of each invalid injection time interval is the start time of the invalid injection time interval, and the second number is the end time of the invalid injection time interval. The meaning of this storage statement is that the storage address is 0x046, and the invalid injection time intervals of 340ns-590ns, 610ns-880ns, and 910ns-950ns in this storage address are invalid injection time intervals.

[0062] See also Figure 4 , Figure 4 This is a flowchart of the fault injection effectiveness analysis provided by an embodiment of the present invention.

[0063] The above is a detailed description of an embodiment of the present invention. However, the content described is only a preferred embodiment of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A method for reducing a storage module fault injection set, characterized in that: The method comprises: Using a preset simulation test program to test the memory module of the target integrated circuit to obtain a read-write information file of the memory module; Analyzing the read-write information file using a preset read-write information analysis algorithm to determine an invalid injection time interval of the storage module during the test; Randomly generating injected faults at different times and different circuit nodes for the storage module as a fault injection set; performing a fault injection validity analysis on the fault injection set, removing injected faults in the fault injection set that are in the invalid injection time interval and invalid circuit nodes, to obtain a reduced fault injection set; the invalid circuit nodes are circuit nodes that are not used by the simulation test program in the target integrated circuit; Analyzing the read-write information file using a preset read-write information analysis algorithm to determine an invalid injection time interval of the storage module during the test, including: Analyzing the read-write information file using a preset read-write information analysis algorithm, obtaining a time interval of a read operation and a write operation of each storage address in the storage module as an operation time interval, and using a time interval other than the operation time interval during the test as an interval time interval; For each storage address, determining an adjacent interval time interval before the write operation as an invalid injection time interval; An invalid hash array is generated using each storage address of the storage module as a key and the invalid injection time interval of the storage address as a value.

2. A method for reducing a storage module fault injection set according to claim 1, characterized in that: Using a preset simulation test program to test the memory module of the target integrated circuit to obtain a read-write information file of the memory module, including: The memory module of the target integrated circuit is tested using a preset simulation test program, and the read and write enable, read and write data, and read and write address changes of the memory module are recorded through the Verilog system function $fmonitor to obtain the read and write information file of the memory module.

3. The method for reducing a storage module fault injection set according to claim 1, wherein: Performing a fault injection effectiveness analysis on the fault injection set, removing the injected faults in the invalid injection time interval and invalid circuit nodes in the fault injection set, and obtaining a reduced fault injection set, including: Performing fault injection validity analysis on the fault injection set, removing injected faults located at invalid circuit nodes in the fault injection set, and obtaining a first fault injection set; Injection faults in the invalid injection time interval are removed from the first fault injection set according to the invalid hash array to obtain a reduced fault injection set.

4. The method for reducing a storage module fault injection set according to claim 1, wherein: The value of the invalid hash array records the start time and end time of the invalid injection time interval.

5. The method for reducing a storage module fault injection set according to claim 1, wherein: The storage module is an SRAM and / or a register file.

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