A well ion implantation method

Abstract

The present invention provides a well ion implantation method, comprising the following steps: providing a semiconductor substrate; forming a bottom anti-reflection layer on the semiconductor substrate; coating a photoresist on the bottom anti-reflection layer; forming a top anti-reflection layer on the photoresist; patterning the top anti-reflection layer and the photoresist to form a mask having an implantation window; performing plasma treatment on the mask to increase the roughness of the sidewall of the implantation window and make the sidewall of the implantation window tilt outward; performing ion implantation through the implantation window to form a well region in the semiconductor substrate. Before well ion implantation, the present invention uses plasma to treat the mask, making the sidewall of the implantation window rough, hardened and in an inclined shape, so that the ions implanted at the sidewall are not easily fallen into the semiconductor substrate, and the scattered ions entering the edge of the semiconductor well region can be reduced, thereby effectively suppressing the well proximity effect and improving the doping uniformity of the well region.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and particularly to a well ion implantation method. Background Art

[0002] In the well ion implantation process of semiconductor devices, a photoresist is usually used as a mask to enable ions to be implanted into the required regions. During ion implantation, ions will scatter on the photoresist, and the scattered ions at the edge of the photoresist enter the semiconductor surface, which will affect the doping concentration in the edge region. The well edge-proximity effect (WPE) refers to that when a transistor is located near the edge of the well mask photoresist, due to the scattering of doping ions on the photoresist and entering the edge of the well region, the doping dose in the nearby region increases, resulting in the change of the threshold voltage (Vt) of the transistor and other transistor characteristics with the position and shape of the adjacent well. The closer the device is to the well boundary region, the higher the threshold voltage (Vt) of the device. When the distance from the device channel to the well region edge is less than 3 μm, the change of the device threshold voltage (Vt) is more sensitive.

[0003] With the development of integrated circuits, the critical dimensions of semiconductor devices are getting smaller and smaller. After the critical dimensions of semiconductor devices are less than 90 nm, the problems caused by the well proximity effect become more and more serious with the continuous reduction of the critical dimensions of semiconductor devices. Especially for small-sized semiconductor devices, the influence of the well proximity effect is increasing. Therefore, how to effectively suppress the well proximity effect has become an urgent technical problem in this field. Summary of the Invention

[0004] In view of the above-mentioned prior art, the purpose of the present invention is to provide a well ion implantation method to solve various problems in the prior art.

[0005] To achieve the above purpose and other related purposes, the present invention provides a well ion implantation method, including the following steps:

[0006] Provide a semiconductor substrate;

[0007] Form a bottom anti-reflection layer on the semiconductor substrate;

[0008] Coat a photoresist on the bottom anti-reflection layer;

[0009] Form a top anti-reflection layer on the photoresist;

[0010] Pattern the top anti-reflection layer and the photoresist to form a mask with an implantation window;

[0011] Perform plasma treatment on the mask to increase the roughness of the sidewall of the implantation window and make the sidewall of the implantation window tilt outwards;

[0012] Ion implantation is performed through the injection window to form a well region in the semiconductor substrate.

[0013] Optionally, a shallow trench isolation (STI) structure is formed in the semiconductor substrate before the ion implantation.

[0014] Optionally, the thickness of the bottom anti-reflection layer is less than 250 nm.

[0015] Optionally, the thickness of the top anti-reflection layer is less than 100 nm.

[0016] Optionally, the plasma treatment uses one or more plasmas including Ar, H, C, N, O, F, Cl.

[0017] Optionally, the mask is baked during the plasma treatment. Further optionally, when baking, the heating temperature is 100 - 150 °C and the heating time is less than 120 s.

[0018] Optionally, the sidewall of the injection window is inclined outward at an angle of 5 - 15° by the plasma treatment.

[0019] Optionally, a sacrificial layer is formed on the semiconductor substrate before forming the bottom anti-reflection layer on the semiconductor substrate; the bottom anti-reflection layer is formed on the sacrificial layer. Further optionally, the sacrificial layer is formed by thermal oxidation.

[0020] Optionally, when performing the ion implantation, the semiconductor substrate is rotated so that ions are implanted into the semiconductor substrate from multiple angles. Further optionally, when performing the ion implantation, the semiconductor substrate is rotated continuously or intermittently at an angle less than 2°.

[0021] As described above, the well ion implantation method of the present invention has the following beneficial effects:

[0022] The well ion implantation method of the present invention uses plasma to treat the mask, making the sidewalls of the implantation window rough, hardened and in an inclined shape, so that the ions implanted at the sidewalls are not easily dropped into the semiconductor substrate, and the scattered ions entering the edge of the semiconductor well region can be reduced; at the same time, in addition to the photoresist (PR), the mask also uses a top anti-reflective coating (TARC), which can further reduce the light and ion scattering at the sidewall corners; the semiconductor surface uses a bottom anti-reflective coating (BARC) to shield the scattered ions during implantation; the stacked BARC / PR / TARC also increases the total stack height, thereby further reducing the WPE; during ion implantation, the semiconductor substrate is rotated laterally at a small angle, so that the ions are implanted from multiple angles, and thus the doping uniformity can be improved. Description of the Drawings

[0023] Figure 1 It shows a schematic diagram of the well ion implantation method provided by an embodiment of the present invention.

[0024] Figures 2a - 2f It shows a schematic diagram of the preparation process of the well ion implantation method provided by an embodiment of the present invention; wherein, Figure 2a It shows a schematic diagram of the provided semiconductor substrate, Figure 2b It shows a schematic diagram of forming the bottom anti-reflective layer, Figure 2c It shows a schematic diagram of forming the photoresist and the top anti-reflective layer, Figure 2d It shows a schematic diagram of forming the mask, Figure 2e It shows a schematic diagram after plasma treatment, Figure 2f It shows a schematic diagram of performing ion implantation.

[0025] Description of Component Labels

[0026] 100 Semiconductor Substrate

[0027] 200 Bottom Anti-Reflective Layer

[0028] 300 Photoresist

[0029] 400 Top Anti-Reflective Layer

[0030] 500 Mask

[0031] 501 Implantation Window

[0032] 101 Shallow Trench Isolation Structure

[0033] 102 Sacrificial Layer

[0034] Steps S1 to S7 Detailed Embodiments

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0036] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0037] In order to suppress the well proximity effect and improve the doping uniformity of the well region, this embodiment will provide a well ion implantation method. By performing plasma treatment, the sidewalls of the implantation window are roughened, hardened, and presented in an inclined shape, so that the ions implanted at the sidewalls are not easily trapped in the semiconductor substrate, suppressing the WPE.

[0038] Please refer to Figure 1 , a well ion implantation method provided in this embodiment specifically includes:

[0039] S1 Provide a semiconductor substrate;

[0040] S2 Form a bottom anti-reflection layer on the semiconductor substrate;

[0041] S3 Coat a photoresist on the bottom anti-reflection layer;

[0042] S4 Form a top anti-reflection layer on the photoresist;

[0043] S5 Pattern the top anti-reflection layer and the photoresist to form a mask with an implantation window;

[0044] S6 Perform plasma treatment on the mask to increase the roughness of the sidewalls of the implantation window and make the sidewalls of the implantation window tilt outwards;

[0045] S7 Perform ion implantation through the implantation window to form a well region in the semiconductor substrate.

[0046] Among them, plasma treatment refers to treating the surface of a material by using plasma formed from a gas. The plasma generated by different gases can combine or split ions, thereby achieving the purpose of cleaning and activating the surface. Usually, plasma treatment is used to clean or activate the surface of a material layer. For example, after photoresist removal in lithography, plasma treatment is performed to remove residual photoresist, thereby cleaning the surface of the material layer or activating the surface of the material layer to increase the surface adhesion of the material layer. However, the inventors have found through research that by controlling the gas type, flow rate, radio frequency, and pressure, the shape of the sidewall of the implantation window can be changed by plasma treatment. After the implantation window is treated, the doping uniformity of the implantation region has been significantly improved. In this embodiment, by utilizing the characteristics of plasma treatment that can increase the surface roughness, harden, and change the shape of the material, the TARC and PR have inclined sidewalls and a rougher and harder surface. Due to the significant increase in sidewall roughness and slope, ions are not easily trapped in the semiconductor substrate when reflected by the sidewall, greatly reducing the well proximity effect.

[0047] The well ion implantation method provided by this embodiment will be further described in detail below with reference to the accompanying drawings.

[0048] Please refer to Figures 2a - 2f , this embodiment provides a well ion implantation method, including the following steps:

[0049] First, as Figure 2a shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 can be any suitable semiconductor material, such as a silicon substrate.

[0050] As an optional implementation manner, before ion implantation, a shallow trench isolation structure 101 can be formed in the semiconductor substrate 100 first. The shallow trench isolation structure 101 can be used to separate multiple device regions in the semiconductor substrate 100, and the implantation window can be set above the device region to form a well region in the device region.

[0051] Then, as Figure 2b shown, a bottom anti-reflection layer 200 is formed on the semiconductor substrate 100. The bottom anti-reflection layer 200 can be used as a sacrificial and blocking layer for ion implantation to shield scattered ions during implantation. Its thickness should not only allow ions to penetrate into the substrate but also let unevenly distributed ions stay on this layer. Specifically, the maximum thickness of the bottom anti-reflection layer 200 can be controlled within 250 nm, that is, the thickness of the bottom anti-reflection layer 200 is less than 250 nm.

[0052] As an alternative implementation, before forming the bottom anti-reflection layer 200 on the semiconductor substrate 100, a sacrificial layer 102 may be first formed on the semiconductor substrate 100; the bottom anti-reflection layer 200 is formed on top of the sacrificial layer 102. Specifically, the sacrificial layer 102 may be formed by thermal oxidation. The sacrificial layer 102 can further protect the semiconductor substrate 100.

[0053] As Figure 2c shown, a photoresist 300 is coated on the bottom anti-reflection layer 200; a top anti-reflection layer 400 is then formed on the photoresist 300. Again, as Figure 2d shown, the top anti-reflection layer 400 and the photoresist 300 are patterned to form a mask 500 having an implantation window 501. In addition to the photoresist 300, the mask 500 also uses the top anti-reflection layer 400, which can reduce the light and ion scattering at the sidewall corners. When the exposure wavelength is 365 nm, the thickness of the top anti-reflection layer 400 can be 72 nm, and when the wavelength is 248 nm, the thickness of the top anti-reflection layer 400 can be 48 nm. Therefore, the thickness of the top anti-reflection layer 400 can be controlled within 100 nm, that is, the thickness of the top anti-reflection layer 400 is less than 100 nm.

[0054] Since subsequent processes will use plasma treatment and ion implantation, the PR (including BARC and TARC) will cause the H and OH groups in it to detach due to high-energy ion implantation, forming a hard and high-density carbonized layer on the outer layer of the PR, resulting in the outer layer of the PR being very difficult to remove. After forming the well region, it is necessary to open the BARC at the implantation window, and the opening of the BARC needs to be completed in reactive ion etching (RIE). The TARC can be directly dissolved in the developer and can be removed with the developer. In this embodiment, since there is a TARC covering the upper surface of the PR during subsequent ion implantation, the TARC with a hardened surface can be directly removed with the developer after ion implantation, thus reducing the difficulty of removing the PR. In addition, the addition of the TARC layer also improves the aspect ratio of the mask and makes the ion implantation more uniform.

[0055] Then, as Figure 2eAs shown, the mask 500 is subjected to plasma treatment to increase the roughness of the sidewalls of the implantation window 501 and make the sidewalls of the implantation window 501 tilt outward. Specifically, the angle a at which the sidewalls of the implantation window 501 tilt outward due to the plasma treatment can be 5 to 15°. After the treatment, during ion implantation, some ions at the sidewalls will be reflected instead of being scattered into the edge of the semiconductor well region. Specifically, the plasma treatment can use one or more plasmas including Ar, H, C, N, O, F, Cl. Optionally, the mask 500 can be baked during the plasma treatment. High-temperature plasma treatment can harden the surfaces of the PR and the organic BARC / TARC and make them have more plasticity and inclination. Specifically, when baking, the heating temperature can be 100 to 150°C and the heating time can be less than 120 s.

[0056] Finally, ion implantation is performed through the implantation window 501 to form a well region in the semiconductor substrate 100. As an alternative implementation, when performing the ion implantation, the semiconductor substrate 100 is rotated at a small angle so that ions are implanted into the semiconductor substrate 100 from multiple angles. Specifically, when performing the ion implantation, the semiconductor substrate 100 can be rotated continuously or intermittently at an angle less than 2°, as Figure 2f shown. When rotating the semiconductor substrate 100, it can be rotated in multiple directions and at multiple angles so that ions are implanted from more angles, thereby improving the doping uniformity.

[0057] In summary, in the well ion implantation method of the present invention, the mask is treated with plasma to make the sidewalls of the implantation window rough, hardened and in an inclined shape, so that the ions implanted at the sidewalls are not easily dropped into the semiconductor substrate, and the scattered ions entering the edge of the semiconductor well region can be reduced; at the same time, in addition to the photoresist, the mask also uses a top anti-reflection layer, which can further reduce the light and ion scattering at the sidewall corners; the semiconductor surface uses a bottom anti-reflection layer to shield the scattered ions during implantation; the stacked BARC / PR / TARC also increases the total stack height, thereby further reducing the WPE; during ion implantation, by laterally rotating the semiconductor substrate at a small angle, the ions are implanted from multiple angles, thereby improving the doping uniformity. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0058] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A well ion implantation method, characterized in that, Including the following steps: Providing a semiconductor substrate; Forming a bottom anti-reflection layer on the semiconductor substrate; Coating a photoresist on the bottom anti-reflection layer; Forming a top anti-reflection layer on the photoresist; Patterning the top anti-reflection layer and the photoresist to form a mask with an implantation window; Performing plasma treatment on the mask to increase the roughness of the sidewall of the implantation window and make the sidewall of the implantation window tilt outward, so that the ions implanted at the sidewall are not easily dropped into the semiconductor substrate, suppressing the well proximity effect; Performing ion implantation through the implantation window to form a well region in the semiconductor substrate.

2. The well ion implantation method according to claim 1, characterized in that: Before performing the ion implantation, a shallow trench isolation structure is formed in the semiconductor substrate.

3. The well ion implantation method according to claim 1, characterized in that: The thickness of the bottom anti-reflection layer is less than 250 nm.

4. The well ion implantation method according to claim 1, characterized in that: The thickness of the top anti-reflection layer is less than 100 nm.

5. The well ion implantation method according to claim 1, characterized in that: The plasma treatment uses one or more plasmas including Ar, H, C, N, O, F, Cl.

6. The well ion implantation method according to claim 1, characterized in that: Baking the mask during the plasma treatment.

7. The well ion implantation method according to claim 6, characterized in that: When performing the baking, the heating temperature is 100 - 150 °C and the heating time is less than 120 s.

8. The well ion implantation method according to claim 1, wherein: The plasma treatment makes the sidewall of the implantation window tilt outward at an angle of 5 - 15°.

9. The well ion implantation method according to claim 1, characterized in that: Before forming the bottom anti-reflection layer on the semiconductor substrate, a sacrificial layer is formed on the semiconductor substrate; the bottom anti-reflection layer is formed on the sacrificial layer.

10. The well ion implantation method according to claim 9, wherein: The sacrificial layer is formed by thermal oxidation.

11. The well ion implantation method according to claim 1, wherein: When performing the ion implantation, rotating the semiconductor substrate so that ions are implanted into the semiconductor substrate from multiple angles.

12. The well ion implantation method according to claim 11, wherein: When performing the ion implantation, rotating the semiconductor substrate continuously or intermittently at an angle less than 2°.

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