Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, which relates to the field of semiconductor manufacturing technology and aims to solve the problem that the titanium nitride layer in the current work function adjustment layer is easily oxidized, resulting in an increase in the interlayer resistance value, which affects the performance of the semiconductor structure. The method for manufacturing the semiconductor structure includes providing a substrate; forming a stack layer on the substrate; wherein the stack layer includes an interface layer, a high dielectric constant layer and a work function composite layer stacked in sequence; forming a transition layer on the stack layer; and forming a metal gate layer on the transition layer. The work function composite layer is prepared by physical vapor deposition. The present invention can effectively alleviate the problem that some materials in the work function adjustment layer used in the work function adjustment process are easily oxidized, thereby reducing the interlayer resistance value in the semiconductor structure, and helping to complete the work function adjustment process to improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] Transistors are important devices in dynamic random access memory (DRAM), and the performance of transistors affects the access performance of DRAM devices.

[0003] As the size of transistors continues to shrink, HKMG (High-k and Metal Gate) technology has become a common method for preparing transistor devices with feature sizes less than 45nm. It can increase the switching speed of transistors and reduce gate leakage current, thereby optimizing the access performance of DRAM devices. The transistor structure of HKMG includes a substrate, a silicon oxide layer, a high-k dielectric layer, a work function adjustment layer, and a metal gate stacked in sequence. The work function adjustment layer is La x O y (Al x O y ) layer and a TiN layer. The TiN layer is generally made by a PVD method (Physical Vapor Deposition), while the LaO (AlO) layer is generally made by an ALD method (Atomic layer deposition) to control the thickness of the LaO (AlO) layer.

[0004] However, the current processes in different PVD and ALD equipment easily lead to oxidation of the TiN layer in the work function adjustment layer, making it more difficult for Al or La elements to diffuse into the dielectric layer. It also leads to an increase in interlayer resistance, affecting the performance of transistors and thus the access performance of DRAM devices. Summary of the invention

[0005] In order to solve at least one of the problems mentioned in the background technology, the present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure, which can effectively alleviate the problem that some materials in the work function adjustment layer used in the work function adjustment process are prone to oxidation, thereby reducing the interlayer resistance value in the semiconductor structure, helping to complete the work function adjustment process, and improving the performance of the semiconductor structure.

[0006] In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0007] A substrate is provided, wherein the substrate includes an active region, and the active region includes a source region, a drain region, and a channel region.

[0008] A stacked layer is formed on a substrate, wherein the stacked layer includes an interface layer, a high dielectric constant layer and a work function composite layer which are stacked in sequence.

[0009] A transition layer is formed on the stacked layer.

[0010] A metal gate layer is formed on the transition layer.

[0011] Wherein, the work function composite layer is prepared by physical vapor deposition.

[0012] The manufacturing method of the semiconductor structure provided by the present invention forms a stack layer on a substrate, and uses the work function composite layer in the stack layer to adjust the work function between the interface layer and the high dielectric constant layer to ensure that the work function of the interface layer changes, so as to facilitate the formation of an electron or hole conduction structure in the channel region, and optimize the performance of the semiconductor structure. By forming a high dielectric constant layer in the stack layer, the quantum tunneling effect between the substrate and the metal gate can be reduced, thereby reducing the problem of metal gate leakage current. By setting a transition layer, the difficulty of setting the metal gate layer can be reduced. By setting a metal gate layer, the performance of the gate structure can be optimized. By preparing the work function composite layer by physical vapor deposition, the problem that some materials in the work function composite layer are easily oxidized can be reduced, thereby effectively reducing the interlayer resistance value in the semiconductor structure and improving the performance of the manufactured semiconductor structure.

[0013] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the work function recombination layer includes a first barrier layer, a work function layer, and a second barrier layer which are stacked in sequence.

[0014] The first barrier layer is located on a side of the work function layer close to the high dielectric constant layer.

[0015] The second barrier layer is located on a side of the work function layer away from the high dielectric constant layer.

[0016] Such a configuration can ensure the stability of the work function layer structure and reduce the mutual interference between the work function layer and the high dielectric constant layer. In addition, the first barrier layer and the second barrier layer can prevent the metal materials in the other structural layers in the semiconductor structure from penetrating and diffusing into the substrate, thereby improving the stability of the transistor structure formed in the semiconductor structure.

[0017] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the doping type of the substrate is N-type, and the doping types of the source region, the drain region and the channel region are P-type.

[0018] The work function layer is a metal aluminum layer.

[0019] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the doping type of the substrate is P-type, and the doping types of the source region, the drain region and the channel region are N-type.

[0020] The work function layer is a metal lanthanum layer.

[0021] The above configuration can facilitate the user to adjust the material of the work function layer according to the type of transistor formed in the semiconductor structure, so as to achieve the purpose of improving the performance of the semiconductor structure.

[0022] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the first barrier layer is a titanium nitride layer or a tantalum nitride layer.

[0023] And / or, the second barrier layer is a titanium nitride layer or a tantalum nitride layer.

[0024] Such a configuration can ensure the protective effect of the first barrier layer and the second barrier layer on the work function layer.

[0025] In the above-mentioned method for manufacturing a semiconductor structure, optionally, after the step of forming a stack layer on the substrate and before the step of forming a transition layer on the stack layer, the method further includes:

[0026] The stack layer is subjected to thermal annealing so that the work function adjustment particles in the work function recombination layer in the stack layer diffuse to the interface between the interface layer and the high dielectric constant layer through thermal movement.

[0027] The work function regulating particles are located in the work function layer.

[0028] The work function composite layer in the stack layer is removed, and the interface layer and the high dielectric constant layer in the stack layer are retained.

[0029] Such a configuration can reduce the difficulty of adjusting the work function of the interface layer, and facilitate the formation of a conduction structure in the channel region of the transistor in the semiconductor structure.

[0030] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the work function regulating particles include aluminum ions, or the work function regulating particles include lanthanum ions.

[0031] Such a setting can facilitate the user to adjust the type of work function regulating particles according to the type of transistor formed in the semiconductor structure, so as to achieve the purpose of improving the performance of the semiconductor structure.

[0032] In the above-mentioned method for manufacturing a semiconductor structure, optionally, in the step of thermally annealing the stack layer so that the work function adjustment particles in the work function recombination layer in the stack layer diffuse to the interface between the interface layer and the high dielectric constant layer through thermal motion:

[0033] The temperature range of the thermal annealing treatment is 700° C. to 1100° C., and the time range of the thermal annealing treatment is 5 seconds to 3 hours.

[0034] Such a configuration can ensure that the work function adjustment particles have sufficient thermal budget to diffuse to the interface between the interface layer and the high dielectric constant layer.

[0035] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the thickness range of the work function layer is

[0036] Such a configuration can reduce the difficulty of preparing the work function layer and help reduce the overall thickness of the semiconductor structure.

[0037] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the thickness of the first barrier layer is in the range of

[0038] Such a configuration can reduce the possibility of the first barrier layer being oxidized, thereby reducing the resistance value in the first barrier layer and optimizing the performance of the semiconductor structure.

[0039] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the high dielectric constant layer material includes hafnium silicate, the interface layer material includes silicon oxide, and a hafnium silicate / silicon oxide interface is formed between the substrate and the interface layer.

[0040] Such a setting can facilitate the formation of a stable hafnium silicate / silicon oxide interface, which is beneficial for the work function adjustment particles to diffuse there, thereby completing the work function adjustment process of the interface layer.

[0041] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the material of the high dielectric constant layer includes a mixture of one or more of magnesium oxide, aluminum oxide, calcium oxide, yttrium oxide, hafnium silicate, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, barium oxide, strontium oxide and zirconium silicate.

[0042] Such a setting can ensure the richness of the high dielectric constant layer material and reduce the difficulty of preparing the high dielectric constant layer.

[0043] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the material of the transition layer includes polysilicon.

[0044] Such a configuration can facilitate the formation of a metal gate layer on the transition layer, increase the connection stability between the metal gate layer and the transition layer, and optimize the interlayer performance between the metal gate layer and the transition layer.

[0045] In the above-mentioned method for manufacturing a semiconductor structure, optionally, the material of the metal gate layer includes aluminum or tungsten.

[0046] Such a configuration can reduce the difficulty of preparing the metal gate layer and optimize the performance of the metal gate layer.

[0047] In a second aspect, the present invention provides a semiconductor structure, comprising:

[0048] The substrate comprises a semiconductor layer, the semiconductor layer comprises a source region and a drain region, and a channel region is arranged between the source region and the drain region.

[0049] The interface layer is arranged on the substrate.

[0050] The high dielectric constant layer is disposed on the interface layer; wherein work function regulating particles are gathered at the interface between the interface layer and the high dielectric constant layer.

[0051] The transition layer is arranged on the high dielectric constant layer.

[0052] The metal gate layer is arranged on the transition layer.

[0053] The semiconductor structure provided by the present invention forms an interface layer on the substrate, so as to form a stable interlayer structure layer between the substrate and the interface layer, thereby optimizing the connection stability between the two. By forming a high dielectric constant layer on the interface layer, the quantum tunneling effect between the substrate and the metal gate can be reduced, thereby reducing the problem of metal gate leakage current. By setting a transition layer, the difficulty of setting a metal gate layer can be reduced. By setting a metal gate layer, the performance of the gate structure can be optimized. During the preparation process of the semiconductor structure of this embodiment, the problem of oxidation of materials in some layers can be effectively reduced, so the interlayer resistance value can be reduced, which helps to improve the performance of the semiconductor structure.

[0054] The construction of the present invention and other objects and advantageous effects thereof will become more apparent through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0057] Figure 2 A schematic flow chart of a work function adjustment process of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0058] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present invention;

[0059] Figure 4 A front view of a semiconductor structure provided by an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of a portion of a semiconductor structure provided by an embodiment of the present invention;

[0061] Figure 6 A schematic diagram of a structure of a first work function-adjusted particle diffusion of a semiconductor structure provided by an embodiment of the present invention;

[0062] Figure 7 A schematic diagram of a structure of a first work function regulating particle adjusting a channel region of a semiconductor structure provided by an embodiment of the present invention;

[0063] Figure 8 A schematic diagram of a structure of a second work function-adjusted particle diffusion of a semiconductor structure provided by an embodiment of the present invention;

[0064] Fig. 9 A schematic diagram of the structure of the second work function regulating particle adjusting the channel region of the semiconductor structure provided by an embodiment of the present invention;

[0065] Fig.10 A schematic structural diagram of a substrate, an interface layer and a high dielectric constant layer of a semiconductor structure provided by an embodiment of the present invention;

[0066] Fig.11 A schematic diagram of the structure of a substrate, an interface layer, a high dielectric layer and a transition layer of a semiconductor structure provided by an embodiment of the present invention;

[0067] Fig.12 A schematic structural diagram of a substrate, an interface layer, a high dielectric constant layer, a transition layer and a metal gate layer of a semiconductor structure provided in an embodiment of the present invention.

[0068] Description of reference numerals:

[0069] 10-substrate; 11-source region;

[0070] 12-drain region; 13-channel region;

[0071] 20-interface layer; 30-high dielectric constant layer;

[0072] 40-work function composite layer; 41-first barrier layer;

[0073] 42-work function layer; 43-second barrier layer;

[0074] 50-transition layer; 60-metal gate layer;

[0075] 80- additional layer; 81- side wall;

[0076] 82-metal silicon compound layer; 83-strained silicon layer. DETAILED DESCRIPTION

[0077] The inventor of the present application found in the actual research process that the current HKMG transistor structure includes a substrate, a silicon oxide layer, a high dielectric constant dielectric layer, a work function adjustment layer and a metal gate stacked in sequence. x O y (Al x O y ) layer and a composite layer of a TiN layer. The TiN layer is generally made by a PVD method (Physical Vapor Deposition), while the LaO (AlO) layer is generally made by an ALD method (Atomic layer deposition) to control the thickness of the LaO (AlO) layer. However, the current PVD and ALD processes in different equipment easily lead to the oxygen atoms in the LaO (AlO) prepared by ALD to diffuse into the TiN layer, resulting in the formation of oxide TiO in the TiN layer, making it more difficult for the Al element or the La element to diffuse into the dielectric layer. In addition, in the ALD preparation method, the TiN layer is also easily affected by oxygen atoms, which increases the resistance value in the TiN layer, affects the performance of the transistor formed in the semiconductor structure, and thus affects the access performance of the DRAM device.

[0078] In view of this, the manufacturing method and semiconductor structure of the semiconductor structure provided by the embodiment of the present invention form a stack layer on the substrate, and use the work function composite layer in the stack layer to adjust the work function between the interface layer and the high dielectric constant layer to ensure that the work function of the interface layer changes, so as to facilitate the formation of an electron or hole conduction structure in the channel region, and optimize the performance of the semiconductor structure. By forming a high dielectric constant layer in the stack layer, the quantum tunneling effect between the substrate and the metal gate can be reduced, thereby reducing the problem of metal gate leakage current. By setting a transition layer, the difficulty of setting the metal gate layer can be reduced. By setting a metal gate layer, the performance of the gate structure can be optimized. By using physical vapor deposition to prepare the work function composite layer, the problem that some materials in the work function composite layer are easily oxidized can be reduced, thereby effectively reducing the interlayer resistance value in the semiconductor structure and improving the performance of the manufactured semiconductor structure.

[0079] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present invention will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present invention. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present invention, not all of them. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limitations on the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. The embodiments of the present invention are described in detail below in conjunction with the drawings.

[0080] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present invention. Figure 2 A schematic flow chart of a work function adjustment process of a method for manufacturing a semiconductor structure provided in an embodiment of the present invention. Figure 3 A schematic structural diagram of a semiconductor structure provided by an embodiment of the present invention. Figure 4 A front view of a semiconductor structure provided by an embodiment of the present invention. Figure 5 A partial structural schematic diagram of a semiconductor structure provided by an embodiment of the present invention. Figure 6 A schematic diagram of the structure of the first work function-regulated particle diffusion of the semiconductor structure provided by an embodiment of the present invention. Figure 7 A schematic structural diagram of a first work function regulating particle adjusting channel region of a semiconductor structure provided by an embodiment of the present invention. Figure 8 A schematic diagram of the structure of the second work function-regulated particle diffusion of the semiconductor structure provided by an embodiment of the present invention. Fig. 9 A schematic structural diagram of a second work function regulating particle adjusting channel region of a semiconductor structure provided by an embodiment of the present invention. Fig.10 A schematic structural diagram of a substrate, an interface layer and a high dielectric constant layer of a semiconductor structure provided in an embodiment of the present invention. Fig.11 A schematic structural diagram of a substrate, an interface layer, a high dielectric layer and a transition layer of a semiconductor structure provided in an embodiment of the present invention. Fig.12 A schematic structural diagram of a substrate, an interface layer, a high dielectric constant layer, a transition layer and a metal gate layer of a semiconductor structure provided in an embodiment of the present invention.

[0081] Reference Figure 1 and Figure 2 As shown, combined with Figures 3 to 12 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising:

[0082] S1: providing a substrate, the substrate comprising an active region, the active region comprising a source region, a drain region and a channel region.

[0083] It should be noted that the material of the substrate 10 may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon-on-insulator (SOI), etc., or other materials known to those skilled in the art, and the substrate 10 may provide a support basis for the structural layer on the substrate 10. In the present embodiment, the substrate 10 is a Si substrate. The substrate 10 may have a semiconductor layer, which forms an active region of the substrate 10, and the active region includes a source region 11 and a drain region 12, and a channel region 13 is formed between the source region 11 and the drain region 12.

[0084] S2: forming a stacked layer on the substrate, wherein the stacked layer comprises an interface layer 20, a high dielectric constant layer 30 and a work function composite layer 40 which are stacked in sequence.

[0085] It should be noted that the interface layer 20 in the stack layer is located on the substrate 10, the high dielectric constant layer 30 is located on the side of the interface layer 20 away from the substrate 10, and the work function composite layer 40 is located on the side of the high dielectric constant layer 30 away from the interface layer 20. The interface layer 20 can be a SiO2 layer, and a Si / SiO2 interface is formed between the substrate 10 and the interface layer 20. The Si / SiO2 interface has high stability and can ensure the stable setting of subsequent structural layers.

[0086] Furthermore, based on the fact that the characteristic dimensions of current semiconductors are constantly decreasing, in order to improve the resulting short channel effect and the quantum tunneling effect between the substrate 10 and the gate structure, a high dielectric constant layer 30 is used as a gate dielectric layer. The high dielectric constant layer 30 can effectively reduce the quantum tunneling effect between the substrate 10 and the gate, reduce the problem of gate leakage current, and the problem of high power consumption caused by the gate leakage current.

[0087] Furthermore, in the transistor formed by the semiconductor structure, the channel region 13 of the transistor will form a conductive structure, and the work function composite layer 40 can adjust the work function of the interface layer 20 in the semiconductor structure, thereby reducing the difficulty of forming a conductive structure in the channel region 13, which helps to improve the switching speed of the transistor formed in the semiconductor structure.

[0088] S3: forming a transition layer on the stack layer.

[0089] It should be noted that a transition layer 50 is further arranged on the stack layer, and the transition layer 50 can facilitate the subsequent arrangement of the metal gate layer 60, reduce the difficulty of arranging the metal gate layer 60, and at the same time, the contact interface stability between the metal gate layer 60 and the transition layer 50 is relatively high. Fig.11 Shown in.

[0090] S4: forming a metal gate layer on the transition layer. The structure can be Fig.12 As shown in .

[0091] It should be noted that, compared with the traditional gate made of polysilicon material, the metal gate layer 60 of this embodiment replaces the polysilicon gate to solve the problems of threshold drift, polysilicon gate depletion effect, excessive gate resistance and Fermi level pinning, so as to optimize the stability and performance of the semiconductor structure.

[0092] As a feasible implementation, the material of the metal gate layer 60 includes aluminum or tungsten. Such a configuration can not only reduce the difficulty of preparing the metal gate layer 60 , but also optimize the performance of the metal gate layer 60 and the semiconductor structure.

[0093] It should be particularly pointed out that in this embodiment, the work function composite layer 40 is prepared by physical vapor deposition. Physical vapor deposition is a method of vaporizing the material to be coated in a vacuum preparation environment and depositing it on the surface of the substrate by evaporation or sputtering. Therefore, compared with the atomic layer deposition method used in the related art, the vacuum environment used in the physical vapor deposition method can avoid oxidation of the material of some layers in the semiconductor structure and prevent the generated oxides from increasing the interlayer resistance value of the semiconductor structure.

[0094] Specifically, refer to Figure 5 As shown, the work function composite layer 40 includes a first barrier layer 41 , a work function layer 42 and a second barrier layer 43 which are stacked in sequence.

[0095] The first barrier layer 41 is located on a side of the work function layer 42 close to the high dielectric constant layer 30 .

[0096] The second barrier layer 43 is located on a side of the work function layer 42 away from the high dielectric constant layer 30 .

[0097] It should be noted that the first barrier layer 41 can prevent the work function layer 42 from directly contacting the high dielectric constant layer 30, and the second barrier layer 43 can prevent the work function layer 42 from directly contacting the transition layer 50, thereby reducing the influence of the adjacent layer structure on the work function layer 42 and ensuring the stability of the work function layer 42 structure.

[0098] Furthermore, the first barrier layer 41 and the second barrier layer 43 can prevent the metal materials in the remaining structural layers in the semiconductor structure, mainly the metal gate layer 60 formed subsequently, from penetrating and diffusing into the substrate 10, affecting the formation of the conductive structure in the substrate 10, as well as the conduction and shutdown process of the conductive structure, thereby improving the stability of the transistor structure formed in the semiconductor structure.

[0099] As a feasible implementation, the first barrier layer 41 is a titanium nitride layer or a tantalum nitride layer. The second barrier layer 43 is a titanium nitride layer or a tantalum nitride layer. Since the first barrier layer 41 and the second barrier layer 43 are respectively attached to different surfaces of the work function layer 42, the formation process of the work function layer 42 will affect the structure of the first barrier layer 41 and the second barrier layer 43, and since the first barrier layer 41 is prepared before the work function layer 42 is formed, the impact on the first barrier layer 41 is particularly obvious. If the work function layer 42 is prepared in a non-vacuum environment, or there is oxygen in the work function layer 42, the first barrier layer 41 and the second barrier layer 43 will be oxidized and oxides will be generated, and the interlayer resistance value of the two will increase. Therefore, the physical vapor deposition method used in this embodiment can effectively avoid the presence of a large amount of oxygen in the preparation process of the work function layer 42, and avoid the oxidation of the first barrier layer 41 and the second barrier layer 43.

[0100] Among them, based on the subsequent work function adjustment process, the work function adjustment particles need to move from the work function layer 42 through the first barrier layer 41 to the interface between the interface layer 20 and the high dielectric constant layer 30 through thermal diffusion. The low resistance value of the first barrier layer 41 in this embodiment helps the diffusion of the work function adjustment particles and avoids affecting the work function adjustment process.

[0101] Specifically, refer to Figure 2 As shown, after the step of forming a stack layer on the substrate and before the step of forming a transition layer on the stack layer, that is, after S2 and before S3, the method further includes:

[0102] S21: thermally annealing the stack layer so that the work function adjustment particles in the work function composite layer in the stack layer diffuse to the interface between the interface layer and the high dielectric constant layer through thermal movement.

[0103] The work function regulating particles are located in the work function layer 42 .

[0104] S22: removing the work function composite layer in the stack layer, and retaining the interface layer and the high dielectric constant layer in the stack layer.

[0105] It should be noted that the thermal annealing process can cause the work function adjustment particles in the work function composite layer 40 to diffuse to the interface between the interface layer 20 and the high dielectric constant layer 30 through thermal diffusion movement. In the semiconductor structure after the work function is adjusted, the work function of the interface layer 20 changes, which helps to form a conductive structure in the channel region 13 of the substrate 10.

[0106] As a feasible implementation, the material of the high dielectric constant layer 30 includes hafnium silicate, the material of the interface layer 20 includes silicon oxide, and a hafnium silicate / silicon oxide interface is formed between the substrate 10 and the interface layer 20 .

[0107] Among them, the temperature range of thermal annealing treatment is 700℃~1100℃, and the time range of thermal annealing treatment is 5s~3h. The above-mentioned process parameters of thermal annealing treatment can ensure that the work function adjustment particles have sufficient thermal budget to diffuse to the interface between the interface layer 20 and the high dielectric constant layer 30. When the thermal annealing treatment is too low, or the time of thermal annealing treatment is too short, it will cause the thermal budget of the work function adjustment particles in the thermal diffusion movement to be too small, and the thermal diffusion movement cannot be completed, or the work function adjustment particles cannot diffuse to the predetermined position, affecting the work function adjustment result. When the thermal annealing treatment is too high, or the time of thermal annealing treatment is too long, it will cause more energy loss in the preparation process of the semiconductor structure, increase the preparation cost, and the high temperature environment will affect the remaining layer structures in the semiconductor structure, reducing the stability of the semiconductor structure. Therefore, in actual use, the user can adjust the temperature and time of thermal annealing treatment within the above range as needed, and this embodiment does not limit the specific values ​​of the two.

[0108] The work function regulating particles include aluminum ions, or the work function regulating particles include lanthanum ions. In actual use, the user can adjust the type of work function regulating particles according to the type of transistors formed in the semiconductor structure to achieve the purpose of improving the performance of the semiconductor structure, and this embodiment does not limit this.

[0109] Further, after the work function adjustment is completed, the work function composite layer 40 can be removed to facilitate the subsequent formation of a metal gate layer 60 on the transition layer 50. Therefore, the transition layer 50 in this embodiment is formed on the high dielectric constant layer 30 in the stack layer.

[0110] In this embodiment, the work function adjustment process mainly includes the following two processes:

[0111] As a feasible implementation method, refer to Figure 6 and Figure 7 As shown, the doping type of the substrate 10 is N-type, and the doping types of the source region 11, the drain region 12 and the channel region 13 are P-type. The work function layer 42 is a metal aluminum layer.

[0112] It should be noted that the work function regulating particles are aluminum ions in the metal aluminum layer, which diffuse to the interface between the interface layer 20 and the high dielectric constant layer 30, and can increase the work function of the interface layer 20 adjacent to the interface, thereby improving the ability of the interface layer 20 to attract electrons. When the gate of the transistor is turned on in the subsequent semiconductor structure, electrons will be enriched in the interface layer 20 and repel excess electrons in the substrate 10, so that the channel region 13 of the substrate 10 near the interface layer 20 forms a hole conduction structure.

[0113] It should be pointed out that the metal aluminum layer selected in this embodiment can effectively reduce the content of oxygen in the work function layer 42 compared to the aluminum oxide layer selected for the work function layer 42 in the related art, thereby avoiding the first barrier layer 41 and the oxygen in the aluminum oxide layer reacting in a high temperature environment to generate oxides during the thermal annealing process, thereby reducing the resistance value of the work function regulating particles diffusing to the predetermined position. Figure 6 Shown in FIG. 1 is a schematic diagram of the diffusion process of aluminum ions.

[0114] As a feasible implementation method, refer to Figure 8 and Fig. 9 As shown, the doping type of the substrate 10 is P type, and the doping types of the source region 11, the drain region 12 and the channel region 13 are N type. The work function layer 42 is a metal lanthanum layer.

[0115] It should be noted that the work function regulating particles are lanthanum particles in the metal lanthanum layer, which diffuse to the interface between the interface layer 20 and the high dielectric constant layer 30, and can reduce the work function of the interface layer 20 adjacent to the interface, thereby improving the ability of the interface layer 20 to attract holes. When the gate of the transistor is turned on in the subsequent semiconductor structure, the holes will be enriched in the interface layer 20 and repel the excess holes in the substrate 10, so that the channel region 13 of the substrate 10 close to the interface layer 20 forms an electronic conduction structure.

[0116] It should be pointed out that, similar to the above-mentioned metal aluminum layer, the metal lanthanum layer selected in this embodiment can effectively reduce the content of oxygen in the work function layer 42, compared with the lanthanum oxide layer selected for the work function layer 42 in the related art, thereby avoiding the first barrier layer 41 and the oxygen elements in the lanthanum oxide layer from reacting in a high temperature environment to generate oxides during the thermal annealing process, thereby reducing the resistance value of the work function regulating particles diffusing to the predetermined position. Figure 8 Shown in FIG. 1 is a schematic diagram of the diffusion process of lanthanum ions.

[0117] The thickness range of the work function layer 42 is Since the work function layer 42 is made of pure metal material, the content of the work function regulating particles is relatively rich, so the thickness of the work function layer 42 can be appropriately reduced. In the related art, if an aluminum oxide layer or a lanthanum oxide layer is selected, its thickness is generally about Therefore, the configuration of this embodiment reduces the thickness of the work function layer 42 , which not only reduces the difficulty of preparing the work function layer 42 , but also helps to reduce the thickness of the entire semiconductor structure.

[0118] The thickness range of the first barrier layer 41 is It should be noted that, based on the possibility of oxidation of the first barrier layer 41 , the possibility of oxidation of the first barrier layer 41 can be reduced by properly adjusting the thickness value, thereby reducing its resistance value and optimizing the performance of the semiconductor structure.

[0119] As a feasible implementation, the material of the high dielectric constant layer 30 includes a mixture of one or more of magnesium oxide, aluminum oxide, calcium oxide, yttrium oxide, hafnium silicate, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, barium oxide, strontium oxide and zirconium silicate. Such a setting can ensure the richness of the material of the high dielectric constant layer 30 and reduce the difficulty of preparing the high dielectric constant layer 30. In actual use, the user can select the above materials to prepare the high dielectric constant layer 30 as needed, and this embodiment does not limit the specific materials.

[0120] The material of the transition layer 50 includes polysilicon. Such a configuration can facilitate the formation of the metal gate layer 60 on the transition layer 50, increase the connection stability between the metal gate layer 60 and the transition layer 50, and optimize the interlayer performance between the metal gate layer 60 and the transition layer 50.

[0121] Based on the above-mentioned method for manufacturing a semiconductor structure, an embodiment of the present invention further provides a semiconductor structure, including:

[0122] The substrate 10 includes an active region, the active region includes a source region 11 and a drain region 12 , and a channel region 13 is disposed between the source region 11 and the drain region 12 .

[0123] The interface layer 20 is disposed on the substrate 10 .

[0124] The high dielectric constant layer 30 is disposed on the interface layer 20 ; wherein work function adjustment particles are gathered at the interface between the interface layer 20 and the high dielectric constant layer 30 .

[0125] The transition layer 50 is disposed on the high dielectric constant layer 30 .

[0126] The metal gate layer 60 is disposed on the transition layer 50 .

[0127] It should be noted that the semiconductor structure of this embodiment can be a DRAM device, and the substrate 10, interface layer 20, high dielectric constant layer 30, transition layer 50 and metal gate layer 60 are partial layer structures in the DRAM device, which can form a transistor structure in the DRAM device. In addition, the transistor structure can also include an additional layer 80, such as a sidewall 81 arranged on the sidewall of the metal gate layer 60, a strained silicon layer 83 located on the substrate 10, and a metal silicon compound layer 82 located on the strained silicon layer 83. Among them, the sidewall 81 can protect the structural stability of the metal gate layer 60. The strained silicon layer 83 is located on the substrate 10 and is respectively located on both sides of the active area, which can cause the channel area 13 to be strained and improve the carrier mobility. The metal silicon compound layer 82 is located above the strained silicon layer 83, which can prevent the strained silicon layer 83 from reacting with the remaining layer structures on the metal silicon compound layer 82, thereby ensuring the stability of the structure of the strained silicon layer 83.

[0128] Among them, an interface layer 20 is provided on the substrate 10, and the interface layer 20 is a structural layer after work function adjustment, and work function adjustment particles diffused therein exist between the interface layer 20 and the high dielectric constant layer 30. The interface layer 20 after work function adjustment helps to form a channel region 13 in a conductive state between the source region 11 and the drain region 12 of the substrate 10, and by adjusting the magnitude of the threshold voltage, the switching speed of the transistor formed in the semiconductor structure is improved.

[0129] The high dielectric constant layer 30 reduces the quantum tunneling effect of the gate dielectric layer, thereby reducing the gate leakage current of the transistor formed in the semiconductor structure and the high power consumption caused by it. In addition, the metal gate layer 60 of metal material is stacked on the high dielectric constant layer 30 to produce a smaller equivalent oxide thickness. At the same time, the metal gate layer 60 can reduce the threshold voltage drift of the existing polysilicon gate, the polysilicon depletion effect, the excessive gate resistance and the pinning of the Fermi level. Therefore, the above-mentioned setting can improve the stability of the semiconductor structure and enhance the performance of the transistor formed in the semiconductor structure.

[0130] Furthermore, the DRAM device may also include an array of multiple memory cells formed on a substrate 10, each memory cell including a capacitor and the above-mentioned transistor. The capacitor is used to store data, and the transistor can control the access of the capacitor to the data, the metal gate layer 60 of the transistor is connected to the word line, the drain region 12 is connected to the bit line, and the source region 11 is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage, so as to realize the data access of the DRAM device. Therefore, when the above-mentioned transistor of this embodiment is applied to the DRAM device, the access performance of the DRAM device can be improved.

[0131] In the description, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0132] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an active region, the active region comprising a source region, a drain region and a channel region; Forming a stacked layer on the substrate; wherein the stacked layer comprises an interface layer, a high dielectric constant layer and a work function composite layer stacked in sequence, the work function composite layer comprises a first barrier layer, a work function layer and a second barrier layer stacked in sequence, the first barrier layer is located on a side of the work function layer close to the high dielectric constant layer, and the second barrier layer is located on a side of the work function layer away from the high dielectric constant layer; forming a transition layer on the stack layer, wherein the material of the transition layer comprises polysilicon; forming a metal gate layer on the transition layer, wherein the material of the metal gate layer comprises aluminum or tungsten; Wherein, the work function composite layer is prepared by physical vapor deposition.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The doping type of the substrate is N-type, and the doping types of the source region, the drain region and the channel region are P-type; The work function layer is a metal aluminum layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The doping type of the substrate is P type, and the doping types of the source region, the drain region and the channel region are N type; The work function layer is a metal lanthanum layer.

4. The method for manufacturing a semiconductor structure according to any one of claims 2 to 3, characterized in that: The first barrier layer is a titanium nitride layer or a tantalum nitride layer; And / or, the second barrier layer is a titanium nitride layer or a tantalum nitride layer.

5. The method for manufacturing a semiconductor structure according to any one of claims 2 to 3, characterized in that: After the step of forming a stack layer on the substrate and before the step of forming a transition layer on the stack layer, the method further includes: Thermally annealing the stacked layer so that the work function adjustment particles in the work function composite layer in the stacked layer diffuse to the interface between the interface layer and the high dielectric constant layer through thermal movement; Wherein, the work function regulating particles are located in the work function layer; The work function composite layer in the stacked layer is removed, and the interface layer and the high dielectric constant layer in the stacked layer are retained.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The work function adjustment particles include aluminum ions; Alternatively, the work function adjustment particles include lanthanum ions.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: In the step of thermally annealing the stacked layer so that the work function adjustment particles in the work function composite layer in the stacked layer diffuse to the interface between the interface layer and the high dielectric constant layer through thermal motion: The temperature range of thermal annealing treatment is 700℃~1100℃; The time range of thermal annealing treatment is 5s~3h.

8. The method for manufacturing a semiconductor structure according to any one of claims 2 to 3, characterized in that: The thickness of the work function layer ranges from 3Å to 7Å.

9. The method for manufacturing a semiconductor structure according to any one of claims 2 to 3, characterized in that: The thickness of the first barrier layer ranges from 30Å to 90Å.

10. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The high dielectric constant layer material includes hafnium silicate, the interface layer material includes silicon oxide, and a hafnium silicate / silicon oxide interface is formed between the substrate and the interface layer.

11. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the high dielectric constant layer includes a mixture of one or more of magnesium oxide, aluminum oxide, calcium oxide, yttrium oxide, hafnium silicate, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, barium oxide, strontium oxide and zirconium silicate.

12. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate comprises an active region, the active region comprises a source region and a drain region, and a channel region is disposed between the source region and the drain region; an interface layer, the interface layer being disposed on the substrate; A high dielectric constant layer, wherein the high dielectric constant layer is arranged on the interface layer; wherein work function regulating particles are gathered at the interface between the interface layer and the high dielectric constant layer, the work function regulating particles are diffused from a work function composite layer located on a side of the high dielectric constant layer away from the interface layer to the interface between the interface layer and the high dielectric constant layer through thermal motion, the work function composite layer comprises a first barrier layer, a work function layer, and a second barrier layer which are sequentially stacked, the first barrier layer is located on a side of the work function layer close to the high dielectric constant layer, the second barrier layer is located on a side of the work function layer away from the high dielectric constant layer, and the work function composite layer is removed after the thermal motion diffusion; A transition layer, the transition layer is disposed on the high dielectric constant layer, and the material of the transition layer includes polysilicon; A metal gate layer is disposed on the transition layer, and a material of the metal gate layer includes aluminum or tungsten.

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