Method for improving metal gate contact hole etching process window

Abstract

The present invention provides a method for improving the etching process window of metal gate contact holes. A substrate is provided, and a plurality of device regions are formed on the substrate. A metal gate is formed in each device region. An interlayer dielectric layer is formed on the substrate, and then the interlayer dielectric layer is polished to expose the metal gate. A diffusion barrier layer is formed on the interlayer dielectric layer and the metal gate. An etching stop layer and an isolation layer are formed on the diffusion barrier layer in a stacked manner from bottom to top. A photoresist layer is formed on the isolation layer, and photolithography is performed to open the photoresist layer to expose the region other than the metal gate on at least one device region. The exposed isolation layer and the etching stop layer and the diffusion barrier layer thereunder are removed. The photoresist layer is removed, and then an interlayer dielectric layer is continuously formed on the substrate. The interlayer dielectric layer is etched to form contact holes respectively communicating with the source region, the drain region, and the metal gate. The present invention does not change the supporting process conditions such as the interlayer dielectric layer and the contact hole etching, improves the process window of the via etching, and improves the product reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the etching process window of metal gate contact holes. Background Art

[0002] In the 28nm high-voltage high-K metal gate manufacturing process platform, as Figure 1 shown, there are three working voltage regions in the chip: a low-voltage region (0.9V), a medium-voltage region (8V), and a high-voltage region (32V); among them, in the high-voltage region (32V devices), there are relatively large metal gates (MG). After the aluminum chemical mechanical planarization process, compared with the low-voltage region and the medium-voltage region, the metal gates in the high-voltage region are worn more severely. Therefore, during subsequent contact hole etching, the contact hole etching in the low-voltage region and the medium-voltage region stops above the metal gate, but in the high-voltage region, the metal gate has a smaller worn thickness and there is a risk of being etched through by the contact hole etching, which has serious side effects on the performance of the product, such as a reduction in the rated voltage and a reduction in reliability.

[0003] Therefore, a method for improving the etching process window of metal gate contact holes is needed to reduce the risk that the metal gate in the high-voltage region is etched through due to its smaller worn thickness. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for improving the etching process window of metal gate contact holes, which is used to solve the problem that in the prior art, the metal gates in the high-voltage region are worn more severely. Therefore, during subsequent contact hole etching, the contact hole etching in the low-voltage region and the medium-voltage region stops above the metal gate, but in the high-voltage region, the metal gate has a smaller worn thickness and there is a risk of being etched through by the contact hole etching.

[0005] To achieve the above purpose and other related purposes, the present invention provides a method for improving the etching process window of metal gate contact holes, including:

[0006] Step 1: Provide a substrate, on which a plurality of device regions are formed, and a metal gate is formed in each device region. An interlayer dielectric layer covering the plurality of device regions and the metal gate is formed on the substrate, and then the interlayer dielectric layer is polished to expose the metal gate.

[0007] Step 2: Form a diffusion barrier layer on the polished interlayer dielectric layer and the exposed metal gate.

[0008] Step 3: Sequentially form an etching barrier layer and an isolation layer on the diffusion barrier layer.

[0009] Step 4: Form a photoresist layer on the isolation layer, and photolithographically open the photoresist layer to expose the region other than the metal gate on at least one device region.

[0010] Step Five: Remove the exposed isolation layer and the underlying etch stop layer and diffusion barrier layer.

[0011] Step Six: Remove the photoresist layer, and then continue to form an interlayer dielectric layer covering the plurality of device regions and the metal gate on the substrate.

[0012] Step Seven: Etch the interlayer dielectric layer to form contact holes communicating with the source regions, drain regions, and the metal gate of each device region.

[0013] Preferably, the substrate in Step One is a silicon substrate.

[0014] Preferably, the materials of the interlayer dielectric layers in Step One and Step Six are both silicon dioxide.

[0015] Preferably, the material of the metal gate in Step One is aluminum.

[0016] Preferably, the polishing in Step One adopts a chemical mechanical planarization process.

[0017] Preferably, the material of the diffusion barrier layer in Step Two is titanium nitride.

[0018] Preferably, the material of the etch stop layer in Step Three is silicon nitride.

[0019] Preferably, the material of the diffusion barrier layer in Step Three is silicon dioxide.

[0020] Preferably, the plurality of device regions in Step One include a low-voltage device region, a medium-voltage device region, and a high-voltage device region.

[0021] Preferably, at least one of the device regions in Step Four includes a high-voltage device region.

[0022] Preferably, the size of the metal gate on the high-voltage device region is larger than that of the metal gates in the medium-voltage device region and the low-voltage device region.

[0023] Preferably, in Step Five, dry etching is used to remove the exposed isolation layer and the underlying etch stop layer, and then wet etching is used to remove the diffusion barrier layer.

[0024] As described above, the method for improving the etching process window of the metal gate contact hole of the present invention has the following beneficial effects:

[0025] In the case where the improvement of the wear of the large-size metal gate is weak, the present invention can prevent the thinner metal gate from being etched through by the via etching, and with less modification on the original process, without changing the supporting process conditions such as the interlayer dielectric layer and the via etching, thereby improving the process window of the via etching and improving the product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It shows a schematic structural diagram of a chip in the existing structure;

[0027] Figure 2 It shows a schematic structural diagram of the substrate after forming an etch stop layer according to the present invention;

[0028] Figure 3 It shows a lithography schematic diagram according to the present invention;

[0029] Figure 4 It shows a schematic diagram of continuously forming an interlayer dielectric layer according to the present invention;

[0030] Figure 5 It shows a schematic diagram of forming a contact hole according to the present invention;

[0031] Figure 6 It shows a schematic diagram of the process flow according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please refer to Figure 6 , a method for improving the etching process window of the metal gate 15 contact hole provided by the present invention includes:

[0034] Step 1, please refer to Figure 2 , provide a substrate 10, multiple device regions are formed on the substrate 10, a metal gate 15 is formed in each device region, an interlayer dielectric layer 14 covering the multiple device regions and the metal gate 15 is formed on the substrate 10, and then the interlayer dielectric layer 14 is polished to expose the metal gate 15;

[0035] In an alternative embodiment, the substrate 10 in Step 1 is a silicon substrate 10. Multiple device regions can be formed on the silicon substrate 10, and then the structures in each device region are formed. Alternatively, an epitaxial layer can be formed on the substrate 10, and multiple device regions can be formed on the epitaxial layer.

[0036] In an alternative embodiment, the material of the interlayer dielectric layer 14 in both Step 1 and Step 6 is silicon dioxide.

[0037] In an alternative embodiment, the material of the metal gate 15 in Step 1 is aluminum.

[0038] In an alternative embodiment, the multiple device regions in step one include a low-voltage device region, a medium-voltage device region, and a high-voltage device region. The metal gate 15 in the high-voltage device region is prone to wear during polishing, resulting in the metal gate 15 being etched through when forming contact holes later.

[0039] In an alternative embodiment, the polishing in step one uses a chemical mechanical planarization process.

[0040] Step two, form a diffusion barrier layer 11 on the polished interlayer dielectric layer 14 and the exposed metal gate 15.

[0041] In an alternative embodiment, the material of the diffusion barrier layer 11 in step two is titanium nitride, which can be used to prevent the diffusion of the metal gate 15 in subsequent process flows.

[0042] Step three, sequentially form an etch stop layer 12 and an isolation layer 13 on the diffusion barrier layer 11. The etch stop layer 12 is used to protect the metal gate 15 when forming contact holes later, thereby preventing the metal gate 15 from being etched through. The isolation layer 13 is used to isolate the etch stop layer 12 from the subsequent photoresist layer 16.

[0043] In an alternative embodiment, the material of the etch stop layer 12 in step three is silicon nitride.

[0044] In an alternative embodiment, the material of the diffusion barrier layer 11 in step three is silicon dioxide.

[0045] In an alternative embodiment, the diffusion barrier layer 11 made of titanium nitride also serves as an adhesion layer between the etch stop layer 12 made of silicon nitride.

[0046] Step four, please refer to Figure 3 , form a photoresist layer 16 on the isolation layer 13, and open the photoresist layer 16 by lithography to expose the area outside the metal gate 15 on at least one device region.

[0047] In an alternative embodiment, at least one device region in step four includes a high-voltage device region. If the metal gates in other device regions are also large in size, other device regions can also be included.

[0048] In an alternative embodiment, the size of the metal gate 15 on the high-voltage device region is larger than that of the metal gates 15 in the medium-voltage device region and the low-voltage device region, and it is prone to more wear during chemical mechanical planarization polishing.

[0049] Step five, remove the exposed isolation layer 13 and the underlying etch stop layer 12 and diffusion barrier layer 11, so that the etch stop layer 12, diffusion barrier layer 11, and isolation layer 13 on the metal gate 15 in the high-voltage device region are retained.

[0050] In an alternative embodiment, in step five, dry etching is used to remove the exposed isolation layer 13 and the etching stop layer 12 thereunder, and then wet etching is used to remove the diffusion barrier layer 11.

[0051] Step six, please refer to Figure 4 , the photoresist layer 16 is removed, which can usually be removed by ashing process and wet cleaning. Then, an interlayer dielectric layer 14 covering multiple device regions and the metal gate 15 is continuously formed on the substrate 10;

[0052] Step seven, please refer to Figure 5 , the interlayer dielectric layer 14 is etched to form contact holes communicating with the source region, drain region, and metal gate 15 in each device region. Since the metal gate 15 in the high-voltage device region is formed with an etching stop layer 12, the risk of the metal gate 15 being etched through is reduced when forming the contact holes.

[0053] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0054] In summary, when the improvement of the wear of the large-size metal gate is weak, the present invention can prevent the thinner metal gate from being etched through by the via etching, and has a small change on the basis of the original process without changing the supporting process conditions such as the interlayer dielectric layer and the contact hole etching, thereby improving the process window of the via etching and improving the product reliability. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0055] The above embodiments only illustrate the principle and its efficacy of the present invention by way of example, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the etching process window of a metal gate contact hole, characterized in that, At least including: Step 1: Provide a substrate, on which a plurality of device regions are formed. The plurality of device regions include a low-voltage device region, a medium-voltage device region, and a high-voltage device region. A metal gate is formed in each device region. The size of the metal gate on the high-voltage device region is larger than that of the metal gates in the medium-voltage device region and the low-voltage device region. An interlayer dielectric layer covering the plurality of device regions and the metal gates is formed on the substrate, and then the interlayer dielectric layer is polished to expose the metal gates; Step 2: Form a diffusion barrier layer on the polished interlayer dielectric layer and the exposed metal gates; Step 3: Sequentially form an etch stop layer and an isolation layer on the diffusion barrier layer; Step 4: Form a photoresist layer on the isolation layer, and open the photoresist layer by photolithography to expose the region other than the metal gate on the high-voltage device region; Step 5: Remove the exposed isolation layer and the etch stop layer and the diffusion barrier layer thereunder, so that only the etch stop layer, the diffusion barrier layer, and the isolation layer on the metal gate on the high-voltage device region are retained; Step 6: Remove the photoresist layer, and then continue to form an interlayer dielectric layer covering the plurality of device regions and the metal gates on the substrate; Step 7: Etch the interlayer dielectric layer to form contact holes communicating with the source region, the drain region, and the metal gate of each device region.

2. The method for improving the etching process window of a metal gate contact hole according to claim 1, wherein: The substrate in Step 1 is a silicon substrate.

3. The method for improving the etching process window of a metal gate contact hole according to claim 1, wherein: The materials of the interlayer dielectric layers in Step 1 and Step 6 are both silicon dioxide.

4. The method for improving the etching process window of a metal gate contact hole according to claim 1, wherein: The material of the metal gate in Step 1 is aluminum.

5. The method for improving the etching process window of a metal gate contact hole according to claim 1, wherein: The polishing in Step 1 adopts a chemical mechanical planarization process.

6. The method for improving the etching process window of a metal gate contact hole according to claim 1, characterized in that: The material of the diffusion barrier layer in Step 2 is titanium nitride.

7. The method for improving the etching process window of a metal gate contact hole according to claim 1, wherein: The material of the etch stop layer in Step 3 is silicon nitride.

8. The method for improving the etching process window of a metal gate contact hole according to claim 1, characterized in that: In Step 5, dry etching is used to remove the exposed isolation layer and the etch stop layer thereunder, and then wet etching is used to remove the diffusion barrier layer.

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