Display panels, array substrates and their manufacturing methods

Abstract

This application provides a display panel, an array substrate, and a method for manufacturing the same. The method for manufacturing the array substrate includes: forming a first polysilicon layer on a substrate; and forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate, wherein the thickness of the second polysilicon layer is less than the thickness of the first polysilicon layer. The display panel, array substrate, and manufacturing method provided by this application can effectively reduce the height of the protrusions on the surface of the polysilicon film layer in the array substrate, thereby reducing the surface roughness of the polysilicon film layer and helping to reduce the risk of leakage current in the channel region of the transistors in the array substrate.

Description

Technical Field

[0001] This application relates to the field of display panel manufacturing technology, and in particular to a display panel, an array substrate, and a method for producing the same. Background Technology

[0002] Thin-film transistors (TFTs) are crucial components in the array substrate of display panels. Compared to amorphous silicon TFTs, polycrystalline silicon TFTs offer higher electron mobility, faster response times, and higher resolution, and are now widely used in display devices as switching elements in the driving circuitry. Low-temperature polysilicon (LTPS) films are typically used when fabricating the active layer of polycrystalline silicon TFTs.

[0003] During the production of array substrates, the surface roughness of polysilicon films is usually high, resulting in large protrusions on the surface of polysilicon films. These protrusions can affect the conduction performance of the channel region of thin-film transistors and even cause leakage in the channel region. Summary of the Invention

[0004] This application provides a display panel, an array substrate, and a method for manufacturing the same, to improve the leakage current problem in the thin-film transistor channel region of the array substrate.

[0005] In a first aspect, embodiments of this application provide a method for manufacturing an array substrate, comprising: forming a first polysilicon layer on a substrate; forming a second polysilicon layer on a side of the first polysilicon layer away from the substrate, wherein the thickness of the second polysilicon layer is less than the thickness of the first polysilicon layer.

[0006] In some embodiments, the step of generating a first polycrystalline silicon layer on a substrate includes: generating a first amorphous silicon layer on the substrate; laser crystallizing the first amorphous silicon layer to transform the first amorphous silicon layer into a first polycrystalline silicon layer; optionally, generating the first amorphous silicon layer on the substrate using plasma-enhanced chemical vapor deposition; optionally, laser crystallizing the first amorphous silicon layer using an excimer laser annealing process.

[0007] In some embodiments, the step of generating a second polycrystalline silicon layer on the side of the first polycrystalline silicon layer away from the substrate includes: generating a second amorphous silicon layer on the side of the first polycrystalline silicon layer away from the substrate, wherein the thickness of the second amorphous silicon layer is less than the thickness of the first amorphous silicon layer; performing laser crystallization on the second amorphous silicon layer to transform the second amorphous silicon layer into the second polycrystalline silicon layer; optionally, using plasma-enhanced chemical vapor deposition to generate the second amorphous silicon layer on the side of the first polycrystalline silicon layer away from the substrate; optionally, using excimer laser annealing to perform laser crystallization on the second amorphous silicon layer.

[0008] In some embodiments, the thickness of the first amorphous silicon layer is h1, the thickness of the second amorphous silicon layer is h2, and the relationship between h1 and h2 satisfies: 0.4h1≤h2≤0.8h1; optionally, h2=0.5h1.

[0009] In some embodiments, the scanning direction for laser crystallization of the first amorphous silicon layer is a first direction, and the scanning direction for laser crystallization of the second amorphous silicon layer is a second direction. The first direction, the second direction, and the thickness direction of the array substrate intersect each other. Optionally, the first direction, the second direction, and the thickness direction of the array substrate are perpendicular to each other.

[0010] In some embodiments, prior to the step of forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate, the method for producing the array substrate further includes: cleaning the first polysilicon layer with a first solution comprising ozone; cleaning the first polysilicon layer with a second solution comprising hydrofluoric acid; optionally, the concentration of ozone in the first solution is 5 ppm to 20 ppm; optionally, the concentration of hydrofluoric acid in the second solution is 0.5 wt% to 5 wt%.

[0011] In some embodiments, after the step of cleaning the first polysilicon layer with a second solution, the method for producing the array substrate further includes: cleaning the first polysilicon layer with a third solution, wherein the third solution includes ozone and the concentration of ozone in the third solution is greater than the concentration of ozone in the first solution.

[0012] In some embodiments, the method for producing the array substrate further includes: cleaning the second polysilicon layer with a first solution, the first solution including ozone; and cleaning the second polysilicon layer with a second solution, the second solution including hydrofluoric acid.

[0013] Secondly, embodiments of this application provide an array substrate, which is manufactured using the production method of the array substrate provided in any of the above embodiments.

[0014] Thirdly, the present application provides an embodiment of a display panel that includes the array substrate mentioned in the above embodiments.

[0015] The display panel, array substrate, and manufacturing method provided in this application embodiment, by sequentially generating a first polysilicon layer and a second polysilicon layer on the substrate, that is, dividing the polysilicon film layer into multiple film formations, can effectively reduce the height of the protrusions on the surface of the polysilicon film layer in the array substrate, thereby reducing the surface roughness of the polysilicon film layer, which is beneficial to reducing the risk of leakage current in the channel region of the transistor in the array substrate. Attached Figure Description

[0016] The features, advantages, and technical effects of exemplary embodiments of the present application will now be described with reference to the accompanying drawings. In the drawings, the same parts are referred to by the same reference numerals. The drawings are not drawn to scale.

[0017] Figure 1 A flowchart illustrating a method for manufacturing an array substrate, as provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the structure of an intermediate component of an array substrate produced using the array substrate manufacturing method provided in the embodiments of this application.

[0019] Figure 3 A flowchart illustrating another method for manufacturing an array substrate provided in an embodiment of this application;

[0020] Figure 4 A schematic diagram of the structure of the array substrate after the formation of the first amorphous silicon film layer during the manufacturing process of the embodiment of this application;

[0021] Figure 5 A schematic diagram of the structure after the formation of the second amorphous film layer during the production process of the array substrate provided in this application embodiment;

[0022] Figure 6 A flowchart illustrating another method for manufacturing an array substrate provided in this application embodiment;

[0023] Figure 7 This is a flowchart illustrating another method for manufacturing an array substrate according to an embodiment of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10. Substrate; 20. Polycrystalline silicon film layer; 21'. First amorphous silicon layer; 21. First polycrystalline silicon layer; 22'. Second amorphous silicon layer; 22. Second polycrystalline silicon layer;

[0026] X, thickness direction. Detailed Implementation

[0027] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. In the accompanying drawings and the following description, at least some well-known structures and techniques are not shown to avoid unnecessarily obscuring the application; and, for clarity, the dimensions of some structures may be exaggerated. Furthermore, the features, structures, or characteristics described below can be combined in any suitable manner in one or more embodiments.

[0028] Furthermore, for the sake of understanding and ease of description, the dimensions and thicknesses of each configuration shown in the figures are arbitrarily illustrated, but the concept of this application is not limited thereto. In the figures, the thicknesses of layers, films, panels, and regions, etc., are enlarged for clarity. In the figures, the thicknesses of some layers and regions are enlarged for better understanding and ease of description.

[0029] It is understandable that when an element such as a layer, film, region, or substrate is described as being "on" another element, the element may be directly on that other element, or there may be intermediate elements present. In contrast, when an element is described as being "directly on" another element, there are no intermediate elements present. Furthermore, throughout the specification, the phrase "on" the target element indicates that it is positioned above or below the target element and does not necessarily indicate that it is positioned "on the upper side" based on the direction of gravity.

[0030] Furthermore, unless explicitly stated otherwise, the word "including" will be understood to include the stated elements but not exclude any other elements.

[0031] Currently, the active layer of LTPS transistors typically includes a polycrystalline silicon film. This polycrystalline silicon film is usually formed by laser crystallization of an amorphous silicon film. During laser crystallization, protrusions form on the surface of the amorphous silicon film, resulting in protrusions on the surface of the polycrystalline silicon film, affecting its surface roughness. During the use of LTPS transistors, the presence of these protrusions on the polycrystalline silicon film will affect the conductivity of the channel region of the active layer, and may even cause leakage current in the channel region.

[0032] In view of this, embodiments of this application provide a method for manufacturing an array substrate, an array substrate manufactured using the method, and a display panel using the array substrate. The display panel may be an organic light-emitting diode (OLED) display panel. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and display device.

[0033] like Figure 1 A flowchart illustrating a method for manufacturing an array substrate according to an embodiment of this application is shown; as follows: Figure 2 A schematic diagram of the structure of an intermediate component of an array substrate manufactured using the production method of the array substrate used in the embodiments of this application is shown.

[0034] like Figure 1 and Figure 2 As shown, the method for manufacturing an array substrate according to an embodiment of this application includes:

[0035] S10, A first polysilicon layer 21 is formed on the substrate 10;

[0036] S20, a second polysilicon layer 22 is formed on the side of the first polysilicon layer 21 away from the substrate 10, and the thickness of the second polysilicon layer 22 is less than the thickness of the first polysilicon layer 21.

[0037] Specifically, the first polycrystalline silicon layer 21 and the second polycrystalline silicon layer 22 can be produced on the substrate 10 from other materials, such as amorphous silicon, or they can be formed directly on the substrate by deposition of polycrystalline silicon. In other words, the first polycrystalline silicon layer 21 and the second polycrystalline silicon layer 22 can be formed on the substrate 10 after a chemical reaction, or they can be formed on the substrate 10 simply through changes in physical structure such as shape and state, and can be selected as needed.

[0038] The substrate 10 may include a substrate made of glass or a substrate made of a flexible material such as PI (Polyimide). The first polycrystalline silicon layer 21 may be formed directly on the substrate, or a buffer layer made of an insulating material may be formed on the substrate. The first polycrystalline silicon layer 21 is formed on the buffer layer. The insulating material may be an organic insulating material or an inorganic insulating material. Organic insulating materials have better flexibility, while inorganic insulating materials have better water and oxygen barrier properties. For example, the insulating material may be a compound including silicon oxide and silicon nitride, and the specific material may be selected according to the requirements.

[0039] The “thickness” of the first polysilicon layer 21 and the second polysilicon layer 22 described in this application refers to the dimensions of the first polysilicon layer 21 and the second polysilicon layer 22 along the stacking direction of the substrate 10, the first polysilicon layer 21 and the second polysilicon layer 22.

[0040] It should be noted that the array substrate described in this application, in which a first polysilicon layer 21 and a second polysilicon layer 22 are sequentially formed on substrate 10, is not limited to forming only two polysilicon layers. In fact, the first polysilicon layer 21 and the second polysilicon layer 22 in this application description only represent the order in which they are formed, and the thickness of the later-formed polysilicon layer is less than the thickness of the earlier-formed polysilicon layer. Therefore, the array substrate manufacturing method provided in this application embodiment can include two, three, or more polysilicon layers, and the thickness of each polysilicon layer formed is less than the thickness of the first-formed polysilicon layer. In actual production, the number of polysilicon layers can be specifically determined based on information such as the thickness of the polysilicon layers in the active layer of the array substrate and surface roughness requirements. By forming multiple polysilicon layers, the polysilicon film layer 20 of the array substrate is finally formed.

[0041] It is understandable that the smaller the thickness of the first polysilicon layer 21 or the second polysilicon layer 22, the smaller the height of the protrusions formed on its surface. Therefore, by forming the polysilicon film layer 20 of the array substrate in multiple stages, the height of the protrusions on the surfaces of the first polysilicon layer 21 and the second polysilicon layer 22 can be reduced simultaneously, and the second polysilicon layer 22 can fill the gaps in the protrusions formed on the first polysilicon layer 21, so that the surface roughness of the generated polysilicon film layer 20 is much smaller than that of the polysilicon film layer 20 formed in one stage.

[0042] The array substrate manufacturing method provided in this application provides that by sequentially generating a first polysilicon layer 21 and a second polysilicon layer 22 on the substrate 10, the polysilicon film layer 20 is formed in multiple layers. This can effectively reduce the height of the protrusions on the surface of the polysilicon film layer 20, thereby reducing the surface roughness of the polysilicon film layer 20 in the array substrate. This helps to reduce the risk of leakage current in the channel region of the transistors in the array substrate.

[0043] like Figure 3 A flowchart illustrating the method for manufacturing an array substrate according to an embodiment of this application is shown, as follows: Figure 4 It shows the use of, as Figure 3 The schematic diagram of the intermediate component of the array substrate produced by the shown array substrate manufacturing method is as follows. Figure 5 It shows the use of, as Figure 3 This is a schematic diagram of another intermediate component of the array substrate produced by the shown array substrate manufacturing method.

[0044] like Figure 3 and Figure 4 As shown, in some embodiments, step S10, forming a first polysilicon layer 21 on the substrate 10, includes:

[0045] S11. A first amorphous silicon layer 21' is formed on the substrate 10;

[0046] S12. Laser crystallization is performed on the first amorphous silicon layer 21' to transform the first amorphous silicon layer 21' into the first polycrystalline silicon layer 21.

[0047] Specifically, during the formation of the first polycrystalline silicon layer 21, the first amorphous silicon layer 21' can be deposited on the substrate 10 by chemical vapor deposition.

[0048] Laser crystallization is performed on the first amorphous silicon layer 21', that is, the high energy generated by the instantaneous laser pulse is incident on the first amorphous silicon layer 21'. The laser can instantly raise the temperature of the first amorphous silicon layer 21' to about 1000 degrees Celsius, transforming it into a crystalline state, that is, forming the first polycrystalline silicon layer 21.

[0049] By generating a first amorphous silicon layer 21' on the substrate 10 and then performing laser crystallization on the first amorphous silicon layer 21' to transform it into a first polycrystalline silicon layer 21, the formation of the first polycrystalline silicon layer 21 can be carried out at a relatively low temperature without damaging the substrate 10 or other structures. Furthermore, the formed first polycrystalline silicon layer 21 has large grains, good space selectivity, high doping efficiency, few intracrystalline defects, good electrical properties, and high mobility.

[0050] In some embodiments, in step S11, a first amorphous silicon layer 21' is formed on the substrate 10 using plasma enhanced chemical vapor deposition (PECVD).

[0051] Specifically, PECVD (Pressure Electron Vapor Deposition) utilizes electrons from glow discharge to activate the chemical vapor deposition reaction during low-pressure chemical vapor deposition. In the deposition of amorphous silicon films, silanes can be decomposed using methods such as radio frequency glow discharge. Under the influence of radio frequency power, the silane gas is broken down into various new particles: atoms, free radicals, and plasmas containing various ions. These new particles then undergo a series of complex processes, including migration and dehydrogenation, before being deposited.

[0052] During the process of generating the first amorphous silicon layer 21' by PECVD, the deposition temperature is low, which has little impact on the structure and physical properties of the substrate 10. The generated first amorphous silicon layer 21' has good thickness and composition uniformity, dense structure, few pinholes, and strong adhesion to the substrate 10.

[0053] In some embodiments, in step S12, the first amorphous silicon layer 21' is laser crystallized using an excimer laser annealing (ELA) process.

[0054] Specifically, the ELA method uses a high-energy excimer laser to irradiate the first amorphous silicon layer 21'. After absorbing the energy of the excimer laser, the first amorphous silicon layer 21' melts and crystallizes upon cooling to form the first polycrystalline silicon layer 21. The preparation process is generally carried out at a temperature of 400℃ to 600℃, which can effectively reduce the risk of deformation of the substrate 10.

[0055] Thus, by using the ELA method to transform the first amorphous silicon layer 21' into the first polycrystalline silicon layer 21, the transformation of the first amorphous silicon layer 21' into the first polycrystalline silicon layer 21 can be completed at a lower temperature, reducing the risk of deformation of the substrate 10 and other structures during laser crystallization, and helping to ensure the stability of the structure and physical properties of the substrate 10 and other structures.

[0056] like Figure 3 and Figure 5 As shown, in some embodiments, step S20, the step of forming a second polysilicon layer 22 on the side of the first polysilicon layer 21 away from the substrate 10, includes:

[0057] S21. A second amorphous silicon layer 22' is formed on the side of the first polycrystalline silicon layer 21 away from the substrate 10, and the thickness of the second amorphous silicon layer 22' is less than the thickness of the first amorphous silicon layer 21'.

[0058] S22. Laser crystallization is performed on the second amorphous silicon layer 22' to transform the second amorphous silicon layer 22' into the second polycrystalline silicon layer 22.

[0059] Specifically, a second amorphous silicon layer 22' can be deposited on the first polycrystalline silicon layer 21 by deposition. After the first polycrystalline silicon layer 21 is laser crystallized, there are protrusions on its surface, resulting in a high surface roughness of the first polycrystalline silicon layer 21. During the deposition of the second amorphous silicon layer 22' on the first polycrystalline silicon layer 21, the second amorphous silicon layer 22' can fill the spaces between the protrusions. As a result, the height of the protrusions from the first polycrystalline silicon layer 21 onto the second amorphous silicon layer 22' is reduced. After the second amorphous silicon layer 22' is transformed into the second polycrystalline silicon layer 22 by laser crystallization, since the thickness of the second amorphous silicon layer 22' is less than the thickness of the first amorphous silicon layer 21', the protrusions on the second polycrystalline silicon layer 22 are smaller than the protrusions on the first polycrystalline silicon layer 21. Since the protrusions on the first polycrystalline silicon layer 21 are filled by the second polycrystalline silicon layer 22, the height of the protrusions from the surface of the first polycrystalline silicon layer 21 onto the surface of the second polycrystalline silicon layer 22 is reduced. Therefore, the total protrusion height on the second polycrystalline silicon layer 22 is reduced, which reduces the surface roughness of the generated polycrystalline silicon film layer 20.

[0060] In some embodiments, a second amorphous silicon layer 22' is formed on the side of the first polycrystalline silicon layer 21 away from the substrate 10 using plasma-enhanced chemical vapor deposition. That is, the second amorphous silicon layer 22' is formed in step S21 using PECVD.

[0061] The first amorphous silicon layer 21' is generated using the same PECVD method. During the generation of the second amorphous silicon layer 22' using the same PECVD method, the deposition temperature is low, which has little impact on the structure and physical properties of the substrate 10. The generated second amorphous silicon layer 22' has good thickness and composition uniformity, dense structure, few pinholes, and strong adhesion to the substrate 10.

[0062] In some embodiments, the second amorphous silicon layer 22' is laser-crystallized using an excimer laser annealing process. That is, in step S22, the second amorphous silicon layer 22' is laser-crystallized using the ELA method.

[0063] Using the ELA method to laser crystallize the first amorphous silicon layer 21' has the same effect. By using the ELA method to transform the second amorphous silicon layer 22' into the second polycrystalline silicon layer 22, the transformation of the second amorphous silicon layer 22' into the second polycrystalline silicon layer 22 can be completed at a lower temperature, reducing the risk of deformation of the substrate 10 and other structures during the laser crystallization process, which is beneficial to ensuring the stability of the structure and physical properties of the substrate 10 and other structures.

[0064] It is understandable that as long as the thickness of the second amorphous silicon layer 22' is less than that of the first amorphous silicon layer 21', the purpose of reducing the surface roughness of the generated polycrystalline silicon film layer 20 can be achieved.

[0065] like Figure 4 and Figure 5 As shown, in some embodiments, the thickness of the first amorphous silicon layer 21' is h1, and the thickness of the second amorphous silicon layer 22' is h2, with the relationship between h1 and h2 satisfying: 0.4h1≤h2≤0.8h1. Specifically, h2 can be 0.4h1, 0.5h1, 0.6h1, 0.7h1, or 0.8h1, etc.

[0066] The greater the thickness of the amorphous silicon layer, the higher the height of the protrusions on the polycrystalline silicon layer formed after crystallization. Ideally, after the second polycrystalline silicon layer 22 is formed, the height of the protrusions of the second polycrystalline silicon layer 22 itself is the same as the height of the protrusions of the first polycrystalline silicon layer 21 protruding from the second polycrystalline silicon layer 22, which is more conducive to reducing the surface roughness of the formed polycrystalline silicon film layer 20.

[0067] Therefore, by setting 0.4h1≤h2≤0.8h1, after the second polysilicon layer 22 is generated, the height of the protrusion of the second polysilicon layer itself is approximately the same as the height of the protrusion of the first polysilicon layer 21 from the second polysilicon layer 22, which is beneficial to reduce the surface roughness of the polysilicon film layer 20 in the array substrate.

[0068] In some embodiments, h2 = 0.5h1. That is, the second amorphous silicon layer 22' is half the thickness of the first amorphous silicon layer 21'. With this configuration, for some amorphous silicon materials, the surface roughness of the generated polycrystalline silicon film layer 20 can be further reduced during the crystallization process.

[0069] In some embodiments, the scanning direction for laser crystallization of the first amorphous silicon layer 21' is the first direction, and the scanning direction for laser crystallization of the second amorphous silicon layer 22' is the second direction. The first direction, the second direction, and the thickness direction X of the array substrate intersect each other.

[0070] Specifically, setting both the first and second directions to intersect with the thickness direction X of the array substrate facilitates effective laser crystallization of the first amorphous silicon layer 21' and the second amorphous silicon layer 22'. Furthermore, setting the second direction to intersect with the first direction effectively reduces the surface roughness of the generated second polycrystalline silicon layer 22.

[0071] It should be noted that if more amorphous silicon film layers are added and multiple laser crystallizations are required, the scanning direction of each laser crystallization will intersect with the scanning direction of the previous laser crystallization, so as to further reduce the surface roughness of the generated polycrystalline silicon film layer 20.

[0072] In some embodiments, the first direction, the second direction, and the thickness direction X of the array substrate are perpendicular to each other.

[0073] It is understandable that setting both the first and second directions perpendicular to the thickness direction X of the array substrate is beneficial for further improving the efficiency of laser crystallization. Furthermore, setting the first and second directions perpendicularly, under the premise of other inconveniences, is beneficial for minimizing the surface roughness of the second polysilicon layer 22.

[0074] Optionally, step S20 can be performed directly after step S10, or other steps, such as cleaning, can be set between step S10 and step S20.

[0075] like Figure 6 This paper presents another flowchart of a method for manufacturing an array substrate provided in this application.

[0076] like Figure 6As shown, in some embodiments, prior to step S20, before the formation of the second polysilicon layer 22 on the side of the first polysilicon layer 21 away from the substrate 10, the method for manufacturing the array substrate further includes:

[0077] S31. The first polysilicon layer 21 is cleaned with a first solution, the first solution including ozone;

[0078] S32. The first polycrystalline silicon layer 21 is cleaned with a second solution, the second solution including hydrofluoric acid.

[0079] Specifically, after the first polysilicon layer 21 is formed, it is cleaned with a first solution. The ozone in the first solution combines with the first polysilicon layer 21, causing its surface to oxidize and form oxides such as silicon oxide. Then, the first polysilicon layer 21 is cleaned with a second solution. The hydrofluoric acid in the second solution reacts chemically with the oxides on the surface of the first polysilicon layer 21, etching away the oxides. Thus, through these two steps of oxidation and etching, impurities on the surface of the first polysilicon layer 21 can be removed. Furthermore, during the oxidation process of the first polysilicon layer 21, protrusions formed on its surface can also be oxidized. After cleaning with the second solution, some of these oxidized protrusions can be etched away, thereby reducing the surface roughness of the first polysilicon layer 21. In other words, by cleaning the first polysilicon layer 21 with the first solution and the second solution in steps S31 and S32 respectively, not only can impurities on the surface of the first polysilicon layer 21 be removed, but the surface roughness of the first polysilicon layer 21 can also be effectively reduced, which in turn helps to reduce the surface roughness of the polysilicon film layer 20 in the array substrate.

[0080] The concentration of ozone in the first solution is not limited, as long as it can form an oxide on the surface of the first polycrystalline silicon layer 21.

[0081] In some embodiments, the concentration of ozone in the first solution is 5 ppm to 20 ppm. Specifically, the concentration of ozone in the first solution can be 5 ppm, 10 ppm, 15 ppm, or 20 ppm, etc.

[0082] Setting the ozone concentration in the first solution to 5 ppm to 20 ppm ensures that oxides are formed on the surface of the first polysilicon, which can then be etched away by the second solution in subsequent steps.

[0083] There is no limit to the concentration of hydrofluoric acid in the second solution, as long as it can corrode the oxides formed after washing with the first solution.

[0084] In some embodiments, the concentration of hydrofluoric acid in the second solution is 0.5 wt% to 5 wt%. Specifically, the concentration of hydrofluoric acid in the second solution can be 0.5 wt%, 1 wt%, 1.5 wt%, 2 wt%, 2.5 wt%, 3 wt%, 4 wt%, or 5 wt%, etc. The second solution thus formed ensures that the oxides formed after cleaning with the first solution are etched away, without causing corrosion to the substrate 10 or other structures such as the second polysilicon layer 22 due to excessively high hydrofluoric acid concentration in the second solution.

[0085] In some embodiments, after step S32, which involves cleaning the first polysilicon layer 21 with a second solution, the method for manufacturing the array substrate further includes:

[0086] S33. The first polycrystalline silicon layer 21 is cleaned with a third solution, the third solution including ozone, and the concentration of ozone in the third solution is greater than the concentration of ozone in the first solution.

[0087] Understandably, after cleaning the surface of the first polysilicon layer 21 with the second solution, the first polysilicon layer 21 is then cleaned with the third solution, and the ozone concentration in the third solution is set to be higher than that in the first solution. On the one hand, this can remove the residual hydrofluoric acid on the surface of the first polysilicon layer 21, reducing its corrosion of the first polysilicon layer 21; on the other hand, the third solution can form a uniform and dense oxide layer on the surface of the first polysilicon layer 21, which is beneficial to the smooth progress of the process of forming the second polysilicon layer 22 on the first polysilicon layer 21.

[0088] like Figure 7 This paper illustrates another flowchart of a method for manufacturing an array substrate according to an embodiment of the present application.

[0089] like Figure 7 As shown, in some embodiments, the method for manufacturing the array substrate further includes:

[0090] S41. The second polysilicon layer 22 is cleaned with a first solution, the first solution including ozone.

[0091] S42. The second polysilicon layer 22 is cleaned with a second solution, which includes hydrofluoric acid.

[0092] Using the first solution and the second solution to clean the first polysilicon layer 21 in sequence has the same effect. Using the first solution and the second solution to clean the second polysilicon layer 22 in sequence can effectively reduce the surface roughness of the second polysilicon layer 22 while removing impurities from the surface of the second polysilicon, which in turn helps to reduce the surface roughness of the polysilicon film layer 20 in the array substrate.

[0093] In some embodiments, after step S42, a third solution may be used to clean the second polysilicon layer 22 to form a uniform and dense oxide layer on the second polysilicon layer 22, which is beneficial to ensuring the performance stability of the second polysilicon layer 22.

[0094] The array substrate provided in the embodiments of this application is manufactured using the manufacturing method of any of the above embodiments. The array substrate thus manufactured has a lower surface roughness of the active layer of the thin-film transistor, effectively reducing the risk of channel leakage in the thin-film transistor.

[0095] The display panel provided according to the embodiments of this application includes the array substrate provided in the above embodiments.

[0096] The display panel provided in this application embodiment has the same technical effect as the array substrate provided in the above embodiment, and will not be described again here.

[0097] Although this application has been described with reference to preferred embodiments, various modifications can be made thereto and components can be replaced with equivalents without departing from the scope of this application. In particular, the technical features mentioned in the various embodiments can be combined in any manner, provided there is no structural conflict. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A method for manufacturing an array substrate, characterized in that, include: A first polycrystalline silicon layer is formed on the substrate; A second polysilicon layer is formed on the side of the first polysilicon layer away from the substrate, and the thickness of the second polysilicon layer is less than the thickness of the first polysilicon layer. At least one polysilicon layer is sequentially formed on the side of the second polysilicon layer away from the substrate, the thickness of the polysilicon layer being less than the thickness of the second polysilicon layer, and the thickness of the polysilicon layer formed later being less than the thickness of the polysilicon layer formed earlier.

2. The method for producing an array substrate according to claim 1, characterized in that, The step of forming the first polysilicon layer on the substrate includes: A first amorphous silicon layer is formed on the substrate; The first amorphous silicon layer is laser crystallized to transform it into a first polycrystalline silicon layer.

3. The method for producing an array substrate according to claim 2, characterized in that, The first amorphous silicon layer is formed on the substrate using plasma-enhanced chemical vapor deposition.

4. The method for producing an array substrate according to claim 2, characterized in that, The first amorphous silicon layer was laser crystallized using an excimer laser annealing process.

5. The method for producing an array substrate according to claim 2, characterized in that, The step of forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate includes: A second amorphous silicon layer is formed on the side of the first polycrystalline silicon layer away from the substrate, and the thickness of the second amorphous silicon layer is less than the thickness of the first amorphous silicon layer. The second amorphous silicon layer is laser crystallized to transform it into the second polycrystalline silicon layer.

6. The method for producing an array substrate according to claim 5, characterized in that, A second amorphous silicon layer is formed on the side of the first polycrystalline silicon layer away from the substrate using plasma-enhanced chemical vapor deposition.

7. The method for producing an array substrate according to claim 5, characterized in that, The second amorphous silicon layer is laser crystallized using an excimer laser annealing process.

8. The method for producing an array substrate according to claim 5, characterized in that, The thickness of the first amorphous silicon layer is h1, and the thickness of the second amorphous silicon layer is h2. The relationship between h1 and h2 satisfies: 0.4h1≤h2≤0.8h1.

9. The method for producing an array substrate according to claim 8, characterized in that, h2 = 0.5h1.

10. The method for producing an array substrate according to claim 5, characterized in that, The scanning direction for laser crystallization of the first amorphous silicon layer is the first direction, and the scanning direction for laser crystallization of the second amorphous silicon layer is the second direction. The first direction, the second direction, and the thickness direction of the array substrate intersect each other.

11. The method for producing an array substrate according to claim 10, characterized in that, The first direction, the second direction, and the thickness direction of the array substrate are perpendicular to each other.

12. The method for producing an array substrate according to claim 1, characterized in that, Before the step of forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate, the method for manufacturing the array substrate further includes: The first polycrystalline silicon layer is cleaned with a first solution, the first solution including ozone; The first polycrystalline silicon layer is cleaned using a second solution, which includes hydrofluoric acid.

13. The method for producing an array substrate according to claim 12, characterized in that, The concentration of ozone in the first solution is 5 ppm to 20 ppm.

14. The method for producing an array substrate according to claim 12, characterized in that, The concentration of hydrofluoric acid in the second solution is 0.5 wt% to 5 wt%.

15. The method for producing an array substrate according to claim 12, characterized in that, After the step of cleaning the first polysilicon layer with the second solution, the method for producing the array substrate further includes: The first polycrystalline silicon layer is cleaned using a third solution, the third solution including ozone, the concentration of ozone in the third solution being greater than the concentration of ozone in the first solution.

16. The method for producing an array substrate according to claim 1, characterized in that, Also includes: The second polysilicon layer is cleaned using a first solution, the first solution including ozone; The second polycrystalline silicon layer is cleaned using a second solution, which includes hydrofluoric acid.

17. An array substrate, characterized in that, It is manufactured using the production method of the array substrate as described in any one of claims 1 to 16.

18. A display panel, characterized in that, Includes the array substrate as described in claim 17.

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