A semiconductor memory structure and a method for filling contact holes with conductive material
By using a gradient-doped silicon stacked structure, the problem of numerous pores in DRAM contact holes was solved, the density of conductive materials and the electrical performance of the device were improved, the difficulty of re-etching was reduced, and the device quality was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2020-12-25
- Publication Date
- 2026-05-26
Smart Images
Figure CN114695264B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing processes, and in particular to a semiconductor memory structure and a method for filling contact holes with conductive material. Background Technology
[0002] In semiconductor manufacturing, etching processes are used to form contact holes in dielectric layers, followed by the deposition of conductive materials within these contact holes for electrical connections between semiconductor devices. This is a widely used process. Contact holes can be directly connected to the gate, source, or drain terminals of devices, and can also be used for inter-layer electrical connections. The wiring connections in many semiconductor devices are crucial, and the technical applications of these connections are becoming increasingly complex.
[0003] Taking DRAM as an example, such as Figure 1 and 2 As shown, the conductive material embedded in the contact holes of the active region unit 101 connected to the capacitor is mostly polysilicon 102. With the development of semiconductor device integration and the miniaturization of circuit design, numerous holes 103 exist at the interface between the narrow contact holes and the silicon substrate, leading to device defects or reduced electrical performance (e.g., affecting operating speed and refresh rate). Therefore, existing technologies use repeated deposition and etching methods to reduce holes, often employing the following process:
[0004] Step 1: Spray a silicon source (e.g., diisopropylaminosilane (DIPAS)) onto the deposition substrate at 380–430°C;
[0005] The second step involves supplying silane and doping gas (e.g., PH3) for CAD deposition at 380–430°C.
[0006] The third step involves supplying silane and dopant gas (e.g., PH3) for CAD deposition at 510–530°C.
[0007] The first two steps are to form a seed layer to guide the unidirectional growth of silicon. Conductive materials formed using the above method include... Figure 2 As shown, the structure includes a seed crystal layer 201 and a phosphorus-doped polycrystalline silicon layer 202. There are still many pores 103 at the interface between the two layers, indicating that the method still has a large number of pores.
[0008] To address the aforementioned problems, this invention is proposed. Summary of the Invention
[0009] The main objective of this invention is to provide a method for filling contact holes of a memory device with conductive material. This method can reduce the number of holes in the contact holes and uses conductive material formed by gradient doped silicon layers, which reduces the difficulty of subsequent etch-back, makes device patterning easier, and makes it easier to improve device defects.
[0010] A second objective of this invention is to provide a semiconductor memory structure in which the contact holes are made of conductive material using a specific stacked structure, thereby avoiding the generation of a large number of holes and improving the electrical characteristics of the device.
[0011] To achieve the above objectives, the present invention provides the following technical solutions.
[0012] A method for filling the contact holes of a memory device with a conductive material includes:
[0013] A semiconductor substrate is provided, and an active region is formed in the semiconductor substrate;
[0014] A dielectric layer is formed above the semiconductor substrate, and a contact hole is formed in the dielectric layer to expose a portion of the active region.
[0015] Deposit a silicon seed layer into the contact hole;
[0016] A highly doped silicon layer is deposited on the surface of the silicon seed layer;
[0017] A low-doped silicon layer is deposited on the surface of the highly doped silicon layer;
[0018] An undoped silicon layer is deposited on the surface of the low-doped silicon layer;
[0019] Wherein, the content of doped atoms in the highly doped silicon layer is greater than the content of doped atoms in the low-doped silicon layer.
[0020] The method of this invention first forms a seed layer on the surface to promote the subsequent generation of single crystals. Then, a highly doped silicon layer, a low-doped silicon layer, and an undoped silicon layer are deposited sequentially according to a doping concentration gradient from high to low. This achieves the following effects: On the one hand, since the doping concentration of the shallow layer gradually decreases, the difficulty of subsequent patterning, including processes such as etch-back, is reduced, thereby avoiding device defects caused by damage in the corresponding processes and improving device quality. On the other hand, this filling method has a high silicon density in narrow holes such as deep trenches, which can achieve fewer holes and improve the electrical characteristics of the device (such as operating speed, refresh rate, and other parameters).
[0021] The present invention also provides a semiconductor structure, comprising:
[0022] A semiconductor substrate, wherein the semiconductor substrate includes an active region;
[0023] The dielectric layer located on the active region;
[0024] A contact hole located in the dielectric layer exposes a portion of the active region therein; and the contact hole is used for electrical connection between multilayer structures.
[0025] The contact hole is filled with a conductive material;
[0026] The conductive material comprises a silicon seed layer, a highly doped silicon layer, a low-doped silicon layer, and an undoped silicon layer stacked from bottom to top, wherein the content of doped atoms in the highly doped silicon layer is greater than the content of doped atoms in the low-doped silicon layer.
[0027] Compared to existing products, this semiconductor memory structure has fewer conductive material pores filling the contact holes and is easier to re-etch, resulting in better electrical characteristics of the device.
[0028] In summary, compared with the prior art, the present invention achieves the following technical effects:
[0029] (1) Reduced the number of pores in the conductive material of the contact hole;
[0030] (2) It reduces the difficulty of re-etching the conductive material in the contact hole;
[0031] (3) Improved the electrical characteristics of the device. Attached Figure Description
[0032] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.
[0033] Figure 1 This is a topographic map of the contact hole filling in DRAM in the prior art;
[0034] Figure 2 for Figure 1 Morphology of the conductive material in the contact hole;
[0035] Figure 3 The morphology of the conductive material obtained by filling the contact hole using the process provided by the present invention. Detailed Implementation
[0036] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.
[0037] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged and may have been omitted for clarity. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.
[0038] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.
[0039] The following will use the formation process of the memory node contact in DRAM manufacturing as an example to describe the embodiments of the present invention in detail.
[0040] First, a semiconductor substrate is provided, on which active regions and gate lines can be formed to form a BCAT (buried channel transistor). The semiconductor substrate can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, such as silicon-on-insulator (SOI), bulk silicon, germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. Bit lines and bit line contacts are formed on one of the active regions of the transistor, while the other active region typically contacts the memory node, and a capacitor can then be formed on it.
[0041] A dielectric layer may be formed over the semiconductor substrate, and a contact hole exposing the other active region may be formed in the dielectric layer. This dielectric layer may also have been formed during the bit line formation step.
[0042] Next, a contact portion needs to be formed in the contact hole. Specifically, a conductive material can be filled into the contact hole to form the contact portion. One embodiment of the present invention provides the following filling method:
[0043] The first step is to deposit a silicon seed layer into the contact hole.
[0044] The second step is to deposit a highly doped silicon layer on the surface of the silicon seed layer. This can be done using low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), a combination of atomic layer seed deposition and LPCVD, or plasma-enhanced chemical vapor deposition (PECVD).
[0045] The third step is to deposit a low-doped silicon layer on the surface of the highly doped silicon layer.
[0046] Step 4: Deposit an undoped silicon layer on the surface of the low-doped silicon layer.
[0047] Among them, the content of doped atoms in the highly doped silicon layer is greater than the content of doped atoms in the low-doped silicon layer.
[0048] Compared with existing technologies, this invention adds a third and fourth step, and changes the deposition conditions of the second step to a high concentration of doping, resulting in a gradient decrease in doping concentration from the bottom layer to the surface layer. This achieves the following effects: On the one hand, since the doping concentration gradually decreases in the shallow surface layer, the difficulty of subsequent patterning processes, including etch-back processes, is reduced, thereby avoiding device defects caused by damage in these processes and improving device quality. On the other hand, this filling method has a high filling density in narrow holes such as deep trenches, achieving fewer voids and improving device electrical characteristics (such as operating speed, refresh rate, and other parameters).
[0049] This invention can also be applied to the manufacture of contact portions of bit lines. Specific implementation methods can be found in the embodiments described above.
[0050] The above contact hole filling methods are applicable to any device that requires electrical connection through contact holes, including but not limited to typical DRAM, Flash, or logic devices.
[0051] The method for depositing a silicon seed layer in this invention can be adopted in any manner. The purpose is to form a seed layer on the substrate surface to promote the subsequent generation of single crystals and to make the filler exist in a single crystal structure to a greater extent.
[0052] In some preferred embodiments, the method for depositing the silicon seed layer is as follows:
[0053] First, silicon source is sprayed onto the semiconductor substrate at 380–450°C to perform silicon deposition, and then silicon deposition is performed at 380–450°C with the supply of silicon source and doping gas source.
[0054] The silicon source sprayed for the first time in this step can be at least one of diisopropylaminosilane (DIPAS), SiH4, SiH2Cl2, SiHCl3, SiCl4, and Si2H6, preferably at least one of DIPAS and SiH2Cl2. The silicon source deposited thereafter in the same temperature range can be at least one of DIPAS, SiH4, SiH2Cl2, SiHCl3, SiCl4, and Si2H6, preferably Si2H6.
[0055] In some preferred embodiments, the silicon source used for depositing the highly doped silicon layer, the lightly doped silicon layer, and the undoped silicon layer can be at least one of diisopropylaminosilane (DIPAS), SiH4, SiH2Cl2, SiHCl3, SiCl4, and Si2H6. It is preferred to use the same silicon source, with SiH4 being the most effective.
[0056] Throughout the filling process, the doped atoms can be adjusted according to the device function, and can be either N-type or P-type doped, such as B, P, As, etc. The corresponding doping gas sources include B2H6, PH3, AsH3, etc. Phosphorus doping is commonly used in this field. In addition, the doping type is the same in each layer of the same contact hole in the same device.
[0057] In some preferred embodiments, the deposition of the highly doped silicon layer, the deposition of the low-doped silicon layer, and the deposition of the undoped silicon layer are carried out at a higher temperature than the deposition of the seed layer, preferably 500°C to 550°C, such as 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, etc., or the temperature is controlled within a range with small fluctuations, so that the deposited film has more uniform properties.
[0058] In some preferred embodiments, the deposition pressure during the deposition of the highly doped silicon layer, the deposition of the lightly doped silicon layer, and the deposition of the undoped silicon layer is maintained at 0.5 Torr to 2 Torr.
[0059] In some preferred embodiments, during the deposition of the seed layer, the deposition pressure is maintained at 0.5 Torr to 2 Torr in the doped deposition process.
[0060] In some preferred embodiments, the flow rate of diisopropylaminosilane spraying is 50 sccm to 500 sccm, the supply flow rate of ethylsilane is 200 sccm to 1000 sccm, the supply flow rate of methylsilane is 1500 sccm to 2500 sccm, and the supply flow rate of the dopant gas source is 300 sccm to 2500 sccm.
[0061] In this article, the "sccm" indicator refers to milliliters per minute.
[0062] In some preferred embodiments, the ratio of the amount of doped atoms during the deposition of the highly doped silicon layer to the amount of doped atoms during the deposition of the low-doped silicon layer is 400-450:300-310. For example, the doping gas source supply is 450 mL during the deposition of the highly doped silicon layer and 310 mL during the deposition of the low-doped silicon layer.
[0063] Furthermore, the supply of the dopant gas source during seed crystal deposition is 280 mL.
[0064] In some preferred embodiments, the method further includes: forming a gate line in the semiconductor substrate; and forming a bit line structure on other portions of the active region.
[0065] In some preferred embodiments, the method further includes forming a gate on the semiconductor substrate.
[0066] In some preferred embodiments, the substrate refers to a structure including a gate, source / drain, and data line, which are disposed in the active region of the device. The gate may be covered with an insulating film, which may be made of materials such as silicon oxide or silicon nitride.
[0067] The present invention also provides a more preferred method for filling contact holes, comprising:
[0068] Step 1: Spray DIPAS onto the deposition surface (flow rate of 50 sccm to 500 sccm), and control the temperature at 380 to 450°C to perform silicon deposition.
[0069] The second step involves supplying Si2H6 and PH3, controlling the temperature at 380–450℃ and the pressure at 0.5 Torr–2 Torr, to perform silicon deposition. The supply flow rate of Si2H6 is 200 sccm–1000 sccm, and the supply volume is 410 mL. The supply flow rate of PH3 is 300 sccm–2500 sccm, and the supply volume is 280 mL.
[0070] The third step involves supplying SiH4 and PH3, controlling the temperature at 500–550℃ and the pressure at 0.5 Torr–2 Torr, to perform silicon deposition. The supply flow rate of silane is 1500 sccm–2500 sccm, and the supply volume is 2100 mL. The supply flow rate of PH3 is 300 sccm–2500 sccm, and the supply volume is 450 mL.
[0071] Step 4: Supply SiH4 and PH3, control the temperature at 500-550℃ and the pressure at 0.5 Torr-2 Torr, and perform silicon deposition; wherein, the supply flow rate of silane is 1500 sccm-2500 sccm and the supply volume is 2100 mL, and the supply flow rate of PH3 is 300 sccm-2500 sccm and the supply volume is 310 mL.
[0072] Step 5: Supply SiH4, control the temperature at 500-550℃ and the pressure at 0.5 Torr-2 Torr, and perform silicon deposition; wherein, the supply flow rate of silane is 1500 sccm-2500 sccm and the supply volume is 2100 mL.
[0073] The conductive material obtained by the above method has fewer and smaller pores, which reduces the contact hole resistance and helps improve the electrical characteristics of the device.
[0074] Taking DRAM as an example, an active region and gate line can be formed in a semiconductor substrate to form a BCAT (buried channel transistor). A dielectric layer is formed above the substrate, and a contact hole is formed in the dielectric layer to expose the aforementioned active region. Silicon is deposited in the contact hole using the method of this invention to form a contact portion, the morphology of which is as follows... Figure 3 As shown, from bottom to top, there are silicon seed layer 301, highly doped silicon layer 302, low doped silicon layer 303 and undoped silicon layer 304, with very few holes in the contact area.
[0075] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.
Claims
1. A method for filling contact holes of a memory device with conductive material, characterized in that, include: A semiconductor substrate is provided, and an active region is formed in the semiconductor substrate; A dielectric layer is formed above the semiconductor substrate, and a contact hole is formed in the dielectric layer to expose a portion of the active region. Deposit a silicon seed layer into the contact hole; A highly doped silicon layer is deposited on the surface of the silicon seed layer; A low-doped silicon layer is deposited on the surface of the highly doped silicon layer; An undoped silicon layer is deposited on the surface of the low-doped silicon layer; The operating conditions for depositing a highly doped silicon layer on the surface of the silicon seed layer include: a deposition temperature of 500℃-550℃, a deposition pressure maintained at 0.5 Torr ~ 2 Torr, and a supply flow rate of 300 sccm ~ 2500 sccm for the doping gas source. The content of doped atoms in the highly doped silicon layer is greater than the content of doped atoms in the low-doped silicon layer, and the ratio of the amount of doped atoms when depositing the highly doped silicon layer to the amount of doped atoms when depositing the low-doped silicon layer is 400-450:300-310.
2. The method according to claim 1, characterized in that, Also includes: A gate line is formed in the semiconductor substrate; a bit line structure is formed on other portions of the active region.
3. The method according to claim 2, characterized in that, Also includes: A gate is formed on the semiconductor substrate.
4. The method according to claim 1, characterized in that, The method for depositing the silicon seed layer is as follows: First, silicon source is sprayed onto the semiconductor substrate at 380~450℃ to perform silicon deposition, and then doped silicon deposition is performed at 380~450℃ with the supply of silicon source and doping gas source.
5. The method according to claim 4, characterized in that, The deposition temperature for both the deposition of the low-doped silicon layer and the deposition of the undoped silicon layer is 500~550℃.
6. The method according to claim 5, characterized in that, In the method for filling conductive materials, the silicon source used in each step is independently selected from at least one of diisopropylaminosilane, SiH4, SiH2Cl2, SiHCl3, SiCl4, and Si2H6.
7. The method according to claim 6, characterized in that, The method for depositing the silicon seed layer is as follows: first, diisopropylaminosilane is sprayed onto the semiconductor substrate at 380~450℃ to perform silicon deposition, and then doped silicon deposition is performed at 380~450℃ with Si2H6 and a doping gas source supplied. The silicon source used in depositing the highly doped silicon layer, the lightly doped silicon layer, and the undoped silicon layer is SiH4. In the method of filling the contact hole with conductive material, all doping is phosphorus doping.
8. The method according to claim 7, characterized in that, The deposition pressure during both the deposition of the low-doped silicon layer and the deposition of the undoped silicon layer is maintained at 0.5 Torr ~ 2 Torr.
9. The method according to claim 7, characterized in that, The flow rate of diisopropylaminosilane spraying is 50 sccm to 500 sccm, the supply flow rate of ethylsilane is 200 sccm to 1000 sccm, the supply flow rate of methylsilane is 1500 sccm to 2500 sccm, and the supply flow rate of the doping gas source is 300 sccm to 2500 sccm.
10. A semiconductor memory structure prepared by any one of claims 1-9, characterized in that, include: A semiconductor substrate, wherein the semiconductor substrate includes an active region; The dielectric layer located on the active region; A contact hole located in the dielectric layer exposes a portion of the active region therein; and the contact hole is used for electrical connection between multilayer structures. The contact hole is filled with a conductive material; The conductive material comprises a silicon seed layer, a highly doped silicon layer, a low-doped silicon layer, and an undoped silicon layer stacked from bottom to top, wherein the content of doped atoms in the highly doped silicon layer is greater than the content of doped atoms in the low-doped silicon layer.
11. The semiconductor memory structure according to claim 10, characterized in that, The semiconductor substrate includes a buried channel gate line, which, together with a portion of the active region, forms a transistor; the other portion of the active region includes a bit line structure.
12. The semiconductor memory structure according to claim 11, characterized in that, The semiconductor substrate includes a gate, and the gate and the active region form a transistor.