Thin film flip chip packaging

Abstract

A thin film flip chip package is disclosed, wherein the thin film flip chip package includes a base film, a patterned wiring layer, a solder resist layer, a chip, and a graphite sheet. The base film includes a first surface and a mounting region on the first surface. The patterned wiring layer is disposed on the first surface. The solder resist layer partially covers the patterned wiring layer. The chip is disposed on the mounting region and electrically connected to the patterned wiring layer. The graphite sheet covers at least a portion of the solder resist layer, wherein an outer edge of the graphite sheet is aligned with an outer edge of the solder resist layer.

Description

[0001] The present application is a divisional application of a Chinese patent application with application number 202010250246.X and with a filing date of 03-Nov-2017 for a thin film flip chip package and a method of manufacturing the same. TECHNICAL FIELD

[0002] The present application relates to a flip chip package and a method of manufacturing the same, and in particular, to a thin film flip chip package and a method of manufacturing the same. BACKGROUND

[0003] In semiconductor production, the fabrication of integrated circuits (ICs) can be divided into three different stages, namely, a chip manufacturing stage, an IC manufacturing stage, and an IC packaging stage, such as a chip-on-film (COF) packaging.

[0004] In order to increase the dissipation of heat from the chip in the COF package, a heat sink is usually attached to the top surface of the base film to cover the entire chip or to the bottom surface of the base film opposite the chip using a thermally conductive adhesive after the chip is electrically connected to the film via bumps. In the prior art, in the fabrication process of attaching a heat sink on the film for covering the chip, it is difficult to tightly attach the heat sink and the chip together, and thus air is usually present in the gap between the chip and the heat sink. Therefore, during the subsequent heat treatment, the air trapped between the chip and the heat sink expands, thus separating the heat sink and the chip and reducing the reliability of the chip package. Furthermore, since the thermal conductivity of air is actually low, the air trapped in the space between the chip and the heat sink further affects the efficiency of heat generated from the chip to be conducted to the heat sink. SUMMARY

[0005] The present application provides a thin film flip chip package and a method of manufacturing the same, which has a good heat dissipation effect.

[0006] A thin film flip chip package of the present application includes a base film, a patterned wiring layer, a solder resist layer, a chip, and a graphite sheet. The base film includes a first surface and a mounting area on the first surface. The patterned wiring layer is disposed on the first surface. The solder resist layer partially covers the patterned wiring layer. The chip is disposed on the mounting area and electrically connected to the patterned wiring layer. The graphite sheet covers at least a portion of the solder resist layer, wherein an outer edge of the graphite sheet is aligned with an outer edge of the solder resist layer.

[0007] In an embodiment of the present application, the graphite sheet further includes an opening exposing at least a portion of the chip.

[0008] In an embodiment of the present invention, the opening exposes at least a portion of the upper surface of the chip.

[0009] In an embodiment of the present invention, the graphite sheet covers at least a portion of the upper surface of the chip and the opening exposes both side surfaces of the chip completely.

[0010] In an embodiment of the present invention, the opening exposes at least a portion of the side surfaces of the chip.

[0011] In an embodiment of the present invention, the opening exposes at least a portion of both short side surfaces of the chip.

[0012] In an embodiment of the present invention, the opening exposes both short side surfaces of the chip completely.

[0013] In an embodiment of the present invention, the opening exposes at least a portion of both long side surfaces of the chip.

[0014] In an embodiment of the present invention, the opening exposes both long side surfaces of the chip completely.

[0015] In an embodiment of the present invention, the opening exposes a portion of the upper surface of the chip.

[0016] In an embodiment of the present invention, the graphite sheet covers the upper surface of the chip completely.

[0017] In an embodiment of the present invention, the opening exposes the upper surface of the chip completely.

[0018] In an embodiment of the present invention, the distance between the outer edge of the graphite sheet and the outer edge of the solder resist layer is equal to or less than 1 mm.

[0019] In an embodiment of the present invention, the patterned wiring layer extends to the mounting area and the solder resist layer exposes a portion of the patterned wiring layer that extends to the mounting area.

[0020] In an embodiment of the present invention, the chip is mounted on the portion of the patterned wiring layer that extends to the mounting area.

[0021] In an embodiment of the present invention, the opening of the graphite sheet exposes the portion of the patterned wiring layer that extends to the mounting area.

[0022] In an embodiment of the present invention, the film flip chip package further comprises an underfill adhesive filled between the chip and the base film, and the opening exposes the underfill adhesive.

[0023] In an embodiment of the present invention, the opening exposes the entire upper surface of the chip and there is a gap between the opening and the side surfaces of the chip.

[0024] In an embodiment of the present invention, the gap has a width equal to or greater than 2 millimeters (mm).

[0025] In an embodiment of the present invention, the graphite sheet has a thickness in a range of 17 micrometers (pm) to 20 micrometers (pm).

[0026] In an embodiment of the present invention, the film flip chip package further includes an adhesive layer disposed on the bonding surface of the graphite sheet, and the bonding surface is attached to the surface of the solder resist layer through the adhesive layer.

[0027] In an embodiment of the present invention, the film flip chip package further includes a back graphite sheet disposed on a second surface of the base film opposite the first surface of the base film.

[0028] In an embodiment of the present invention, the back graphite sheet overlaps at least the mounting area along a normal direction of the base film.

[0029] In an embodiment of the present invention, an outer edge of the back graphite sheet is aligned with an outer edge of the solder resist layer.

[0030] A method of manufacturing a film flip chip package of the present invention includes the following steps. A graphite roll is provided, wherein the graphite roll includes a plurality of graphite sheets and a release film, the graphite sheets are attached to the release film and each graphite sheet includes an opening; the graphite roll is unwound and one of the graphite sheets on the unwound portion of the graphite roll is picked up from the release film; and the one of the graphite sheets is placed and pressed on a base film, wherein the base film includes a chip mounted thereon and the opening of the one of the graphite sheets exposes the chip.

[0031] In an embodiment of the present invention, the one of the graphite sheets is pressed on the base film by a pressing head.

[0032] In an embodiment of the present invention, the pressing head is an elastic pressing head.

[0033] In an embodiment of the present invention, the pressing head includes a recess, and the chip is located in the recess when the pressing head presses the one of the graphite sheets onto the base film.

[0034] In an embodiment of the present invention, a gap is maintained between the recess and a side surface of the chip.

[0035] In an embodiment of the present invention, a shortest distance from the recess to the side surface of the chip is 1 millimeter (mm) to 3 millimeters (mm).

[0036] In an embodiment of the present application, one of the graphite sheets described above further comprises an adhesive layer disposed on the bonding surface of the graphite sheet, and the release film covers the adhesive layer.

[0037] Based on the above, the graphite sheet is attached to the film flip-chip package of the embodiment of the present application, wherein the graphite sheet exposes at least a portion of the chip and the outer edge of the graphite sheet is aligned with the outer edge of the solder resist layer of the film flip-chip package. In this configuration, the contact area between the graphite sheet and the solder resist layer / chip can be maximized to improve the heat dissipation efficiency of the film flip-chip package. Moreover, since the graphite sheet does not completely cover the chip, the air and / or moisture trapped between the chip and the graphite sheet can easily escape, so that the graphite sheet will not deform or even separate from the chip under high temperature and / or high humidity conditions, thereby improving the reliability of the film flip-chip package.

[0038] In addition, a plurality of graphite sheets can be connected to each other via the release film to form a graphite roll. Therefore, graphite sheets with poor elasticity can be applied to a roll-to-roll manufacturing process, so that the graphite sheets can be applied to the film flip-chip package for mass production. Thus, the heat dissipation of the film flip-chip package in the embodiment of the present application can be improved.

[0039] In order to make the above features and advantages of the present application more obvious and easy to understand, the following specific embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 Cross-sectional view of the film flip-chip package of the embodiment of the present application;

[0041] Figure 2 Top view of the film flip-chip package of the embodiment of the present application;

[0042] Figure 3 Cross-sectional view of the graphite sheet of the embodiment of the present application;

[0043] Figure 4 Top view of the film flip-chip package of the embodiment of the present application;

[0044] Figure 5 Cross-sectional view of the film flip-chip package of the embodiment of the present application;

[0045] Figure 6 Schematic view of the film flip-chip package of the embodiment of the present application;

[0046] Figures 7A to 7C Schematic view of a part of the manufacturing process of the film flip-chip package of the embodiment of the present application;

[0047] Figure 8 Front view of the jig for attaching the graphite sheet to the film flip-chip package of the embodiment of the present application.

[0048] Symbol Explanation

[0049] 100: Thin Film Flip Chip Package

[0050] 110: Base Film

[0051] 112: First Surface

[0052] 114: Second Surface

[0053] 118: Patterned Wiring Layer

[0054] 119: Solder Resist Layer

[0055] 120: Chip

[0056] 130: Graphene Sheet

[0057] 130a: Graphene Roll

[0058] 131: Release Film

[0059] 132: Graphene Layer

[0060] 134: First Adhesion Layer

[0061] 136: Protective Layer

[0062] 138: Second Adhesion Layer

[0063] 140: Backside Graphene Sheet

[0064] 142: Graphene Layer

[0065] 144: First Adhesion Layer

[0066] 146: Protective Layer

[0067] 148: Second Adhesion Layer

[0068] 150: Underfill

[0069] 700: Press Head

[0070] E1 / E2: Outer Edge

[0071] G1 / G2: Gap

[0072] OP1: Opening

[0073] R1: Mounting Area

[0074] T1: Thickness DETAILED DESCRIPTION

[0075] Figure 1 A cross-sectional view of a thin film flip chip package according to an embodiment of the present application is illustrated. Figure 2A top view of a thin film flip-chip package according to embodiments of the present application is illustrated. It should be noted Figure 1 is a cross-sectional view along line A-A' Figure 2 Figure 1 and Figure 2 In this embodiment, the thin film flip-chip package 100 includes a base film 110, a patterned wiring layer 118, a solder resist layer 119, a chip 120, and a graphite sheet 130. The base film 110 includes a first surface 112. A mounting region Rl is a region where the chip 120 is mounted and located on the first surface 112. The patterned wiring layer 118 is disposed on the first surface 112 of the base film 110. The solder resist layer 119 partially covers the patterned wiring layer 118. The chip 120 is disposed in the mounting region Rl and electrically connected to the patterned wiring layer 118.

[0076] More specifically, for example, as shown in this embodiment, the solder resist layer 119 covers the patterned wiring layer 118 and exposes a portion of the patterned wiring layer 118, such that the chip 120 is electrically connected to the portion of the patterned wiring layer 118 exposed by the solder resist layer 119. In this embodiment, the patterned wiring layer 118 extends to the mounting region Rl and the solder resist layer 119 exposes a portion of the patterned wiring layer 118 extending to the mounting region Rl, as shown in Figure 1 The chip 120 is mounted on the portion of the patterned wiring layer 118 extending to the mounting region Rl.

[0077] Further, the graphite sheet 130 covers at least a portion of the solder resist layer 119. Advantageously, the graphite sheet 130 can have a soft property and good thermal conductivity, thus increasing the area of heat dissipation and therefore the enhanced heat dissipation effect. Preferably, but not limitingly, the outer edges E1 / E2 of the graphite sheet 130 can be configured to be approximately aligned with the outer edges of the solder resist layer 119. For example, the distance between the outer edges E1 / E2 of the graphite sheet 130 and the outer edges of the solder resist layer 119 is equal to or less than 1 mm.

[0078] In some embodiments, as shown in this embodiment, the graphite sheet 130 can include a plurality of alignment holes Hl for aligning the outer edges E1 / E2 of the graphite sheet 130 with the outer edges of the solder resist layer 119. The alignment holes Hl can be any shape depending on the desired or required design. Preferably, but not limitingly, the size of the holes Hl can be configured to be less than 3 mm to maximize the heat dissipation effect of the graphite sheet 130.

[0079] ​In the present embodiment, after the encapsulation process is completed, the encapsulation structure can be cut along the plurality of dicing lines to form a plurality of thin film flip chip packages 100, where the dicing lines can be aligned with the outer edges E1 / E2 of the solder resist layer 119. By the configuration that the outer edges E1 / E2 of the graphite sheet 130 are aligned with the outer edges of the solder resist layer 119, the contact area between the graphite sheet 130 and the solder resist layer 119 / chip 120 can be maximized, thus improving the heat dissipation of the thin film flip chip package 100.

[0080] Generally, if the heat dissipation layer completely covers the chip, the heat dissipation layer can be deformed or even separated from the chip under high temperature and / or high humidity conditions due to the expansion of air and / or moisture trapped between the chip and the heat dissipation layer. Therefore, in some embodiments as shown in the present embodiment, the graphite sheet 130 can further include one or more openings OP1 exposing at least a portion of the chip 120 and a portion of the patterned circuit layer 118 extending to the mounting region R1. By this configuration, air and / or moisture trapped between the chip 120 and the graphite sheet 130 can easily escape through the openings OP1 to avoid unwanted deformation or separation of the graphite sheet 130, thus improving the reliability of the thin film flip chip package 100.

[0081] In the present embodiment, the openings OP1 can completely expose the plurality of side surfaces and the upper surface of the chip 120 as shown in Figure 1 and Figure 2 , but the present application is not limited thereto. In addition, the thin film flip chip package 100 can further include an underfill adhesive 150 filled between the chip 120 and the base film 110. The underfill adhesive 150 can also be filled between the side surfaces of the chip 120 exposed by the openings OP1 and the side surfaces of the graphite sheet 130 as shown in Figure 1 . In the present embodiment, there is one or more gaps G1 / G2 between the side surfaces of the graphite sheet 130 / openings OP1 and the side surfaces of the chip 120. For example, there can be a gap G1 between the side surfaces of the graphite sheet 130 / openings OP1 and the short side surfaces of the chip 120, and there can be a gap G2 between the other side surfaces of the graphite sheet 130 / openings OP1 and the long side surfaces of the chip 120 as shown in Figure 2 . Preferably but not limitatively, the width of the gaps G1 / G2 can be configured to be about equal to or greater than 2 mm. In addition, it should be noted that the width of the gap G1 can be about the same as or different from the width of the gap G2.

[0082] It should be noted that in the present embodiment, the graphite sheet 130 exposes the upper surface and the plurality of side surfaces (e.g., four side surfaces) of the chip 120, which means that none of the upper surface and the side surfaces of the chip 120 is completely covered, but the present application is not limited thereto. For example, in some other embodiments, the graphite sheet 130 partially or completely covers the upper surface of the chip while completely exposing the side surfaces of the chip 120. Further, in some other embodiments, the graphite sheet 130 partially or completely covers the upper surface and two short / long side surfaces of the chip while completely exposing two long / short side surfaces of the chip 120. Further, in some further other embodiments, the graphite sheet 130 completely or partially covers the upper surface and each side surface of the chip 120, which means that none of the upper surface and the side surfaces of the chip 120 is completely exposed. More other different combinations of the graphite sheet exposing or covering the upper surface and the side surfaces of the chip 120 can be implemented as needed and are not limited in the present application.

[0083] In some embodiments, the thin film flip-chip package 100 further includes an adhesive layer 138 disposed on the bonding surface of the graphite sheet 130, wherein the bonding surface is the surface of the graphite sheet 130 bonded to the solder resist layer 119 through the adhesive layer 138. Figure 3 A cross-sectional view of the graphite sheet according to such embodiments of the present application is illustrated. In detail, the graphite sheet 130 can include a graphite layer 132, a first adhesive layer 134, a second adhesive layer 138, and a protective layer 136, as shown in Figure 3 Further, the structure shown in Figure 3 may be applied to Figure 1 or other embodiments in the present application, but is not limited thereto. The graphite layer 132 is bonded to the base film 110 and the chip 120 through the first adhesive layer 134. The protective layer 136 is adhered to the graphite layer 132 through the second adhesive layer 138. Preferably but not limitingly, the first adhesive layer 134 can be an organic double-sided tape, and / or the second adhesive layer 138 can be an inorganic double-sided tape, and / or the protective layer 136 can include an insulating film, for example, a polyimide (PI) film, but the embodiments are for illustration only and the present application does not limit the materials of the first adhesive layer 134, the second adhesive layer 138, and the protective layer 136. In some embodiments, the thickness T1 of the graphite sheet 130 can be approximately in the range of 17 μm to 20 μm, but is not limited thereto.

[0084] In Figure 1In some embodiments exemplified in the examples, the thin-film flip package 100 further includes a back graphite sheet 140 disposed on a second surface 114 of the base film 110 opposite to a first surface 112 of the base film 110. The back graphite sheet 140 overlaps with at least the mounting region R1 along the normal direction of the base film 110. The back graphite sheet 140 may also include a graphite layer 142, a first adhesive layer 144, a second adhesive layer 148, and a protective layer 146, such as Figure 1 As shown in the diagram, graphite layer 142 is bonded to the second surface 114 of substrate film 110 via a first adhesive layer 144. Protective layer 146 is bonded to graphite layer 142 via a second adhesive layer 148. Advantageously, the outer edge of back graphite sheet 140 can be configured to approximately align with the outer edge of solder resist layer 119 to maximize the contact area between back graphite sheet 140 and substrate film 110 and further promote heat dissipation of thin-film flip package 100.

[0085] Figure 4 A top view illustrating a thin-film flip-chip package according to an embodiment of the present invention. Figure 5 A cross-sectional view illustrating a thin-film flip-chip package according to an embodiment of the present invention is provided. Note that... Figure 5 It is along line B-B' Figure 4 The cross-sectional view, and, Figure 4 and Figure 5 The thin-film flip package shown is different from the previous one. Figures 1 to 3 Similar to the thin-film flip-chip package 100 in the previous embodiment, this embodiment uses the component designations and some content from the previous embodiment, employing the same designations to represent the same or similar components, and omitting descriptions of identical technical content. For explanations of the omitted parts, please refer to the previous embodiment; this embodiment will not repeat them. Please refer to... Figure 1 as well as Figure 3 The following will focus on the thin-film flip packaging and... Figures 1 to 3 The differences in the thin-film flip-chip packaging 100 are explained.

[0086] It must be noted here that the reference Figure 4 and Figure 5 A graphite sheet 130 covers at least a portion of the upper surface of the chip 120, and an opening OP1 exposes at least a portion of the side surfaces of the chip 120. Specifically, the opening OP1 can expose at least a portion of both short side surfaces of the chip 120. In this embodiment, the opening OP1 completely exposes both short side surfaces of the chip 120. It should be noted that the term "short side surface of the chip 120" means parallel to the short axis of the chip 120 (e.g., ...). Figure 4 The two side surfaces of axis A2 in the middle.

[0087] In detail, the chip 120 has a chip length LI along a first axis Al of the chip 120. A portion of the graphite sheet 130 having the opening OP1 has a length L2 along the first axis Al, and another portion of the graphite sheet 130 not having the opening OP1 has a length L3 along the first axis Al. Thus, the length L3 is greater than the length L2, and the length LI is greater than the length L2. Therefore, the opening OP1 exposes a portion of the upper surface of the chip 120 and the opening OP1 exposes both short side surfaces of the chip 120 as shown in Figure 4

[0088] Figure 6 A schematic diagram of a thin film flip chip package according to an embodiment of the present application is illustrated. It should be noted that the thin film flip chip package shown in Figure 6 is similar to the thin film flip chip package 100 in the foregoing embodiment, and thus, the present embodiment adopts the element reference numerals and parts of the foregoing embodiment, in which the same reference numerals are used to denote the same or similar elements, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the foregoing embodiment, which will not be repeated here. Please refer to Figure 1 and Figure 3 , the differences between the thin film flip chip package of the present embodiment and the thin film flip chip package 100 in the foregoing embodiment will be described.

[0089] Referring to Figure 6 , the graphite sheet 130 can completely cover the upper surface of the chip 120 and the opening OP1 exposes at least a portion of the side surface of the chip 120. In detail, the opening OP1 can expose at least a portion of both long side surfaces of the chip 120. In the present embodiment, the opening OP1 completely exposes both long side surfaces of the chip 120. It should be noted that the so-called "long side surface of the chip 120" means the two side surfaces parallel to the long axis (e.g., the axis Al in Figure 4 .

[0090] Figures 7A to 7C A part of the manufacturing process of a thin film flip chip package according to an embodiment of the present application is illustrated. Figure 8 A front view of a jig for attaching a graphite sheet to a thin film flip chip package according to an embodiment of the present application is illustrated. In the present embodiment, the thin film flip chip package 100 can be formed by a manufacturing method including the following steps. First, the graphite roll 130a shown in Figure 7A and Figure 7B is provided. The graphite roll 130a includes a plurality of graphite sheets 130 and a release film 131. The graphite sheets 130 are attached to the release film 131 and each graphite sheet 130 includes an opening OP1. In detail, each graphite sheet 130 can be similar to Figure 3 ​The graphite flakes 130 shown in FIG. 1A and also include an adhesive layer (e.g., the second adhesive layer 138 shown in FIG. 1B) disposed on the bonding surface of the graphite flakes 130. The release film 131 covers the adhesive layer of the graphite flakes 130. Figure 3 The graphite flakes 130 shown in FIG. 1A and also include an adhesive layer (e.g., the second adhesive layer 138 shown in FIG. 1B) disposed on the bonding surface of the graphite flakes 130. The release film 131 covers the adhesive layer of the graphite flakes 130.

[0091] With this configuration, the graphite flakes 130 can be connected to each other via the release film 131 to form a graphite flake tape and this graphite flake tape can be rolled up to form a graphite roll 130a. Thus, the graphite flakes 130 having poor elasticity can be applied to a roll-to-roll fabrication process so as to be suitable for mass production. Subsequently, the graphite roll 130a is unrolled as shown in FIG. 1C, and one of the graphite flakes 130 on the unrolled portion of the graphite roll 130a can be picked up from the release film 131. Figure 7B

[0092] Subsequently, with reference to FIG. 1D, the picked-up graphite flake 130 is placed on the base film 110 and is bonded on the base film 110 by the bonding head 700. In some embodiments, a plurality of base films 110 having the chips 120 mounted thereon can also be connected to each other and rolled into a base film roll. The base film roll is then unrolled and transported along a first direction Dl, and the graphite roll 130a having a plurality of graphite flakes 130 is unrolled and transported along a second direction D2. The first direction Dl and the second direction D2 can intersect each other. Thus, by the bonding head 700, one of the graphite flakes 130 is placed on and bonded on the corresponding base film 110, and an opening (e.g., the opening OPI shown in FIG. 1E) of the corresponding graphite flake 130 is exposed to the chip 120 on the corresponding base film 110. Figure 7C Figure 8 Figure 2 In this embodiment, the bonding head 700 is an elastic bonding head to avoid undesired damage to the thin film flip chip 100. In detail, the bonding head 700 can include a recess as shown in FIG. 1F. Thus, when the bonding head 700 bonds the graphite flake 130 to the base film 110, the chip 120 is located in the recess without being compressed and damaged. A gap can be maintained between the recess and the side surface of the chip 120 to further prevent the bonding head 700 from damaging the chip 120, and the shortest distance from the recess to the side surface of the chip 120 is 1 mm to 3 mm.

[0093] Figure 8

[0094] ​​​​​In summary, in the embodiments of the present application, the graphite sheet can be used for heat dissipation. The graphite sheet can have good thermal conductivity and thus improved heat dissipation effect. In addition, the outer edge of the graphite sheet can be aligned with the outer edge of the solder resist layer of the thin film flip chip package to maximize the coverage of the graphite sheet and thus the heat dissipation effect. With such a configuration, the contact area between the graphite sheet and the solder resist layer / chip can be maximized to improve the heat dissipation of the thin film flip chip package. In addition, the graphite sheet can include an opening for exposing at least a portion of the chip. In this way, the air and / or moisture trapped between the chip and the graphite sheet can be easily discharged through the opening, so that the graphite sheet does not deform or even separate from the chip under high temperature and / or high humidity conditions, so as to improve the reliability of the thin film flip chip package.

[0095] In addition, in the manufacturing process, a plurality of graphite sheets can be connected to each other via a release film to form a graphite roll. Therefore, the graphite sheet with poor elasticity can be applied to the roll-to-roll manufacturing process, so that the graphite sheet can be applied to the thin film flip chip package for mass production. Therefore, the heat dissipation of the thin film flip chip package in the present application can be improved.

[0096] Although the present application is disclosed in connection with the above embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application should be defined by the appended claims.

Claims

1. A thin film flip-chip package, comprising: The thin film flip chip package comprises: a base film including a first surface and a mounting area on the first surface; a patterned circuit layer disposed on the first surface; an insulating solder resist layer partially covering the patterned circuit layer; a chip disposed on the mounting area and electrically connected to the patterned circuit layer; and a graphite sheet covering at least a portion of the insulating solder resist layer, wherein an outer edge of the graphite sheet is aligned with an outer edge of the insulating solder resist layer, the insulating solder resist layer does not extend to an area between the chip and the first surface of the base film, the graphite sheet further includes an opening, and the opening completely exposes an upper surface of the chip, two short side surfaces of the chip, and two long side surfaces of the chip.

2. A flip-chip thin film package, comprising: The thin film flip chip package comprises: a base film including a first surface and a mounting area on the first surface; a patterned circuit layer disposed on the first surface; an insulating solder resist layer partially covering the patterned circuit layer; a chip disposed on the mounting area and electrically connected to the patterned circuit layer; and a graphite sheet covering at least a portion of the insulating solder resist layer, wherein: opposite sides of the insulating solder resist layer directly contact the patterned circuit layer and the graphite sheet, respectively, such that the patterned circuit layer and the graphite sheet are separated from each other; there is no conductive material between the patterned circuit layer and the graphite sheet that electrically connects the patterned circuit layer and the graphite sheet; and the graphite sheet further includes an opening, and the opening completely exposes an upper surface of the chip, two short side surfaces of the chip, and two long side surfaces of the chip.

3. The thin film flip chip package of claim 2, wherein a distance between an outer edge of the graphite sheet and an outer edge of the insulating solder resist layer is equal to or less than 1 millimeter.

4. The thin film flip chip package of claim 1 or 2, wherein the patterned circuit layer extends to the mounting area and the insulating solder resist layer exposes a portion of the patterned circuit layer that extends to the mounting area.

5. The thin film flip chip package of claim 4, wherein the chip is disposed on the portion of the patterned circuit layer that extends to the mounting area.

6. The thin film flip chip package of claim 4, wherein the opening of the graphite sheet exposes the portion of the patterned circuit layer that extends to the mounting area.

7. The thin film flip chip package of claim 1 or 2, further comprising an underfill adhesive filled between the chip and the base film, and the opening exposes the underfill adhesive.

8. The thin film flip chip package of claim 1 or 2, wherein the opening exposes an entire upper surface of the chip and there is a gap between the opening and side surfaces of the chip.

9. The thin film flip chip package of claim 8, wherein a width of the gap is equal to or greater than 2 millimeters.

10. The thin film flip chip package of claim 1 or 2, wherein a thickness of the graphite sheet is in a range of 17 micrometers to 20 micrometers.

11. The thin film flip chip package of claim 1 or 2, further comprising an adhesive layer disposed on a bonding surface of the graphite sheet, and the bonding surface is a surface to which the insulating solder resist layer is attached through the adhesive layer.

12. The thin film flip chip package of claim 1 or 2, further comprising a backside graphite sheet disposed on a second surface of the base film opposite the first surface of the base film.

13. The thin film flip chip package of claim 12, wherein the backside graphite sheet overlaps at least the mounting region along a normal direction of the base film.

14. The thin film flip chip package of claim 12, wherein an outer edge of the backside graphite sheet is aligned with an outer edge of the insulating solder resist layer.

15. The thin film flip chip package of claim 2, wherein the insulating solder resist layer does not extend to an area between the chip and the first surface of the base film.

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