Semiconductor element and method for manufacturing the same

Abstract

A semiconductor element and a method of manufacturing the same. The semiconductor element includes a conductive feature, a dielectric layer disposed above the conductive feature, and a contact feature extending through the dielectric layer. The contact feature has an upper portion and a lower portion. The upper portion is separated from the dielectric layer by a spacer layer. The lower portion is electrically coupled to the conductive feature and in contact with the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, and more particularly to the contact characteristics of a semiconductor device, and a method for manufacturing the semiconductor device. Background Technology

[0002] The semiconductor industry has made significant progress in pursuing higher device density and lower costs. In the development of semiconductor devices, functional density (e.g., the number of interconnected conductive features per unit area of ​​a wafer) has typically increased while geometric dimensions have decreased. This miniaturization process usually provides benefits by increasing production efficiency and reducing associated costs. However, increased functional density increases the complexity of semiconductor devices, for example, by reducing the distance between adjacent conductive features. When the distance between adjacent conductive features decreases, it can be difficult to form contact features for each conductive feature. For example, the distance between contact features typically decreases as the distance between adjacent conductive features decreases, which can significantly increase the likelihood of short circuits in the contact features.

[0003] Therefore, it is necessary to improve the contact characteristics and the methods for their formation. Summary of the Invention

[0004] One aspect of this disclosure is a semiconductor device comprising: a first conductive feature, a first dielectric layer disposed above the first conductive feature, and a first contact feature extending through the first dielectric layer and electrically coupled to the first conductive feature. The upper portion of the first contact feature is laterally separated from a first inner sidewall of the first dielectric layer via a second dielectric layer, and the lower portion of the first contact feature is in contact with the first inner sidewall of the first dielectric layer.

[0005] Another aspect of this disclosure is to provide a semiconductor device comprising: a conductive feature, a dielectric layer disposed above the conductive feature, and a contact feature extending through the dielectric layer; wherein the contact feature has an upper portion and a lower portion, the upper portion being separated from the dielectric layer by a spacer layer, and the lower portion being electrically coupled to the conductive feature and in contact with the dielectric layer.

[0006] Another aspect of this disclosure is a method for fabricating a semiconductor device, comprising: recessing an upper portion of a first dielectric layer disposed above a conductive feature; filling the upper portion of the recess with a second dielectric layer to form a hole embedded in the second dielectric layer; etching the second dielectric layer and the first dielectric layer to form a contact hole, the contact hole exposing at least a portion of the conductive feature such that at least the lower portion of the contact hole is perpendicularly aligned with the conductive feature; and filling the contact hole with a conductive material to form a contact feature electrically coupled to the conductive feature. Attached Figure Description

[0007] A better understanding of the features disclosed herein will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be arbitrarily scaled.

[0008] Figure 1 This is a flowchart illustrating an exemplary method for forming a semiconductor device according to some embodiments;

[0009] Figures 2 to 7 This is a cross-sectional view of an exemplary semiconductor device during various manufacturing stages, illustrated according to some embodiments. Figure 1 It was made using the method described above;

[0010] Figure 8A These are exemplary semiconductor elements, illustrated according to some embodiments, comprising one or more contact features, which are made of Figure 1 It was made using the method described above;

[0011] Figure 8B It is illustrated according to some embodiments. Figure 8A The corresponding top view of the semiconductor element;

[0012] Figure 9A This is another exemplary semiconductor element, illustrated according to some embodiments, comprising one or more contact features, which is composed of... Figure 1 It was made using the method described above;

[0013] Figure 9B It is illustrated according to some embodiments. Figure 9A The corresponding top view of the semiconductor element;

[0014] Figure 10A This is yet another exemplary semiconductor element, illustrated according to some embodiments, comprising one or more contact features, which is composed of... Figure 1 It was made using the method described above;

[0015] Figure 10B It is illustrated according to some embodiments. Figure 10A The corresponding top view of the semiconductor element;

[0016] Figure 11A This is yet another exemplary semiconductor element, illustrated according to some embodiments, comprising one or more contact features, which is composed of... Figure 1 It was made using the method described above;

[0017] Figure 11B It is illustrated according to some embodiments. Figure 11A The corresponding top view of the semiconductor element;

[0018] Figure 12This is an exemplary top view illustrating contact features according to some embodiments, which is... Figure 1 It was made using the method described above;

[0019] Figure 13 This is an illustrative top view of another contact feature illustrated according to some embodiments, which is... Figure 1 It was made using the method described above.

[0020] [Symbol Explanation]

[0021] 100: Method

[0022] 102: Operation

[0023] 104: Operation

[0024] 106: Operation

[0025] 108: Operation

[0026] 110: Operation

[0027] 200: Semiconductor components

[0028] 202: Substrate

[0029] 204: Conductivity characteristics

[0030] 206: First dielectric layer

[0031] 206S: Inner sidewall of the first dielectric layer

[0032] 207: Depressed area

[0033] 208: Second dielectric layer

[0034] 210: Hole

[0035] 212: Contact hole

[0036] 213: Etching Process

[0037] 214: Spacing layer

[0038] 216: Contact Characteristics

[0039] 216I: Intermediate Boundary

[0040] 216L: Lower part

[0041] 216U: Upper part

[0042] 800: Semiconductor Components

[0043] 801: Substrate

[0044] 802: Transistor

[0045] 802D: Drain Characteristics

[0046] 802G: Gate Features

[0047] 802S: Source Characteristics

[0048] 803: Well

[0049] 804: Transistor

[0050] 804D: Drain Characteristics

[0051] 804G: Gate Features

[0052] 804S: Source Characteristics

[0053] 805: Low dielectric constant dielectric layer

[0054] 806: Contact Characteristics

[0055] 806U: Upper part of the contact feature

[0056] 807: Spacer layer

[0057] 808: Contact Characteristics

[0058] 808U: Upper part of the contact feature

[0059] 809: Spacing layer

[0060] 850: Pattern

[0061] 900: Semiconductor Components

[0062] 902: Transistor

[0063] 902D: Drain Characteristics

[0064] 902G: Gate Features

[0065] 902S: Source Characteristics

[0066] 904: Transistor

[0067] 904D: Drain Characteristics

[0068] 904G: Gate Features

[0069] 904S: Source Characteristics

[0070] 905: Low dielectric constant layer

[0071] 906: Contact Characteristics

[0072] 906L: Lower part of the contact feature

[0073] 906U: Upper part of the contact feature

[0074] 907: Spacer layer

[0075] 908: Contact Characteristics

[0076] 908L: Lower part of the contact feature

[0077] 908U: Upper part of the contact feature

[0078] 909: Spacing layer

[0079] 920: Pattern

[0080] 950: Pattern

[0081] 1000: Semiconductor components

[0082] 1001: Substrate

[0083] 1002: Transistor

[0084] 1002D: Drain Characteristics

[0085] 1002G: Gate Features

[0086] 1002S: Source Characteristics

[0087] 1004: Transistor

[0088] 1004D: Drain characteristics

[0089] 1004G: Gate Features

[0090] 1004S: Source Characteristics

[0091] 1006: Contact Characteristics

[0092] 1008: Contact Characteristics

[0093] 1050: Pattern

[0094] 1100: Semiconductor Components

[0095] 1101: Substrate

[0096] 1102: Transistor

[0097] 1102D: Drain Characteristics

[0098] 1102G: Gate Features

[0099] 1102S: Source Characteristics

[0100] 1104: Contact Characteristics

[0101] 1106: Contact Characteristics

[0102] 1108: Contact Characteristics

[0103] 1110: Contact Characteristics

[0104] 1150: Pattern

[0105] 1155: Pattern

[0106] 1200: Contact Characteristics

[0107] 1200L: Lower part of the contact feature

[0108] 1200U: Upper part of the contact feature

[0109] 1300: Contact Characteristics

[0110] 1300L: Lower part of the contact feature

[0111] 1300U: Upper part of the contact feature

[0112] T1: Thickness

[0113] T2: Depth

[0114] W1: Width

[0115] W2: Width

[0116] W3: Thickness

[0117] W4: Width Detailed Implementation

[0118] The following disclosure provides numerous different embodiments or illustrations to implement different features of the subject matter. The specific illustrations of the components and arrangements described below are for the purpose of simplifying this disclosure. These are, of course, merely illustrative and are not intended to be limiting. For example, the process description of a first feature forming on or above a second feature includes embodiments where the first and second features are in direct contact, as well as embodiments where other features are formed between the first and second features such that the first and second features are not in direct contact. Hereinafter, the phrase "the first feature forming on or above the second feature" represents that the first and second features are in direct contact. Furthermore, references to numerical values ​​and / or letters are repeated in various illustrations in this disclosure. This repetition is intended to simplify and clarify the description and does not imply a relationship between the various discussed embodiments and / or configurations.

[0119] Furthermore, spatially relative terms, such as "below," "below," "lower," "above," and "upper," are used to easily describe the relationship between an element or feature depicted in the accompanying drawings and other elements or features. In addition to the directions depicted in the drawings, spatially relative terms also include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein can be interpreted accordingly.

[0120] This disclosure provides various embodiments of a semiconductor device comprising at least one contact feature formed via a hole. Using this hole, the contact feature can be characterized to dimensions exceeding the limits of patterning processes (e.g., photolithography). This allows for successful formation of the contact feature without any problems (e.g., short-circuiting the conductive features) when forming contact features for conductive features laterally spaced apart from each other at relatively small distances. For example, a hole can be formed in a dielectric layer by adjusting the conditions used for depositing the dielectric layer. A hole can be formed by intentionally forming a protrusion of the dielectric layer on a recess of relatively large size, which may be limited by certain patterning processes. Accordingly, the hole can be characterized to a size generally smaller than the size of the recess. Contact holes can be formed self-aligned with the hole and can also inherit dimensions generally similar to the hole size. Accordingly, by filling the contact hole with a conductive material, contact features characterized to dimensions exceeding the limits of patterning processes can be formed.

[0121] Figure 1 This is a flowchart illustrating a method 100 for manufacturing a semiconductor device 200 according to various aspects of this disclosure. It should be noted that method 100 is merely illustrative and is not intended to limit the scope of this disclosure. Accordingly, it should be understood that... Figure 1 Additional operations are provided before, during, and after method 100, and only a few other operations may be briefly described herein. In some embodiments, the operations of method 100 may be related to, for example... Figures 1 to 7 The cross-sectional views of semiconductor devices at various manufacturing stages shown are related and will be discussed in more detail later.

[0122] Please refer to the following: Figure 1Method 100 begins at operation 102, in which a conductive feature covered by a first dielectric layer is provided. Method 100 proceeds to operation 104, in which a portion of the first dielectric layer is recessed. Method 100 proceeds to operation 106, in which a hole is formed by filling the recess with a second dielectric layer. Method 100 proceeds to operation 108, in which a contact hole is formed by etching through the hole between the first and second dielectric layers. Method 100 proceeds to operation 110, in which a contact feature is formed by filling the contact hole with a conductive material.

[0123] As mentioned above, Figures 2 to 7 It is based on Figure 1 The embodiment of method 100 shows a schematic cross-sectional view of a semiconductor device 200 at various stages of manufacturing. The semiconductor device 200 may be included in a microprocessor, storage unit, and / or other integrated circuit (IC). It should be noted that... Figure 1 The current method cannot produce a complete semiconductor device 200. Semiconductor device 200 can be fabricated using complementary metal-oxide-semiconductor (CMOS) technology. Accordingly, it should be understood that... Figure 1 Additional processes are provided before, during, and after method 100, and only a few other operations may be briefly described herein. Furthermore, for a better understanding of this disclosure, Figures 1 to 7 It has been simplified. For example, although the attached diagram shows semiconductor element 200, it should be understood that the IC may contain many other elements, including transistors, resistors, capacitors, inductors, fuses, etc.

[0124] Corresponding to Figure 1 Operation 102, Figure 2 This is a cross-sectional view of a semiconductor device 200 at various stages of manufacturing according to some embodiments, comprising a substrate 202 having at least one conductive feature 204, the conductive feature 204 being covered by a first dielectric layer 206. Although in Figure 2 The semiconductor element 200 in the illustrative embodiment includes only one conductive feature 204, but it should be understood that... Figure 2 The illustrative embodiments and subsequent figures are for illustrative purposes only. Therefore, the semiconductor element 200 may include any desired number of conductive features while remaining within the scope of this disclosure. For example, on each side of the conductive feature 204, the semiconductor element 200 may include at least one conductive feature substantially similar to the conductive feature 204.

[0125] Semiconductor substrate 202 comprises a substrate of semiconductor material, such as silicon. Alternatively, substrate 202 may comprise semiconductor materials of other elements, such as germanium. Substrate 202 may also comprise compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. Substrate 202 may comprise alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide. In one embodiment, substrate 202 comprises an epitaxial layer. For example, the substrate may have an epitaxial layer covering a bulk semiconductor. Furthermore, substrate 202 may comprise a semiconductor-on-insulator (SOI) structure. For example, the substrate may comprise a buried oxide (BOX) layer formed by processes such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and polishing.

[0126] In the above embodiments where the substrate 202 comprises semiconductor material, the conductive feature 204 may be a source feature (e.g., source electrode), drain feature (e.g., drain electrode), or gate feature (e.g., gate electrode) of a transistor (e.g., a metal oxide semiconductor field-effect transistor; MOSFET). Alternatively, the conductive feature 204 may be a self-aligned silicide feature disposed on the source, drain, or gate electrode. The self-aligned silicide feature is formed using a self-aligned silicide technique.

[0127] In some other embodiments, substrate 202 is a dielectric material substrate formed over various element features (e.g., the source, drain, or gate electrode of a transistor). Such a dielectric material substrate 202 may comprise at least one of silicon oxide, a dielectric material having a relatively low dielectric constant (k value) less than about 4.0, or a combination thereof. In some embodiments, dielectric material substrate 202 is formed of a material comprising a low-dielectric-constant dielectric material, an extremely low-dielectric-constant dielectric material, a porous low-dielectric-constant dielectric material, or a combination thereof. The term "low-dielectric-constant" is intended to define the dielectric constant of a dielectric material as 3.0 or less. The term "extremely low-dielectric-constant" (ELK) refers to a dielectric constant of 2.5 or less, preferably between 1.9 and 2.5. The term "porous low-dielectric-constant" refers to a dielectric constant of 2.0 or less, preferably 1.5 or less. Some embodiments disclosed herein may employ a variety of low dielectric constant materials, such as spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymers, silicone glass, FSG (SiOF series materials), hydrosilsesquioxane (HSQ) series materials, methylsilsesquioxane (MSQ) series materials, or porous organic series materials.

[0128] In embodiments where the substrate 202 is formed of a dielectric material, the conductive feature 204 may be a horizontal conductive structure, a vertical conductive structure, or a combination thereof formed within the substrate 202. For example, the conductive feature 204 may be an interconnect structure (e.g., a horizontal conductive structure), a through-hole structure (e.g., a vertical conductive structure), or a combination thereof. Accordingly, the conductive feature 204 may be electrically coupled to element features of a transistor, such as the source, drain, or gate features of a transistor disposed beneath a layer, interconnect layer, or metallized layer. In such embodiments, the conductive feature 204 may be formed of a metallic material (e.g., copper (Cu), aluminum (Al), tungsten (W), etc.).

[0129] The first dielectric layer is a dielectric material formed to cover various conductive features (e.g., conductive feature 204, etc.). The first dielectric layer 206 may comprise at least one of silicon oxide, a dielectric material having a relatively low dielectric constant (k value) less than about 4.0, or a combination thereof. In some embodiments, the dielectric material substrate 202 is formed of a material comprising a low-dielectric-constant dielectric material, an extremely low-dielectric-constant dielectric material, a porous low-dielectric-constant dielectric material, or a combination thereof. The term "low-dielectric-constant" is intended to define the dielectric constant of a dielectric material as 3.0 or less. The term "extremely low-dielectric-constant" (ELK) refers to a dielectric constant of 2.5 or less, preferably between 1.9 and 2.5. The term "porous low-dielectric-constant" refers to a dielectric constant of 2.0 or less, preferably 1.5 or less. Some embodiments disclosed herein may employ a variety of low dielectric constant materials, such as spin-on inorganic dielectrics, spin-on organic dielectrics, porous dielectric materials, organic polymers, silicone glass, FSG (SiOF series materials), hydrosilsesquioxane (HSQ) series materials, methyl silsesquioxane (MSQ) series materials, or porous organic series materials.

[0130] Corresponding to Figure 1 Operation 104, Figure 3 This is a cross-sectional view of semiconductor device 200, wherein a portion of the first dielectric layer 206 is recessed (hereinafter referred to as "recessed portion 207"). The recessed portion 207 can be formed using optical lithography with masking techniques and one or more dry etching operations, such as plasma etching or reactive ion etching. Alternatively or additionally, one or more wet etching operations can be used to form the recessed portion 207. The recessed portion 207 is formed to be perpendicularly aligned with the conductive feature 204.

[0131] In some embodiments, the recess 207 may extend partially through the first dielectric layer 206 along a first direction (e.g., the Y direction) relative to the substrate 202. Specifically, the first dielectric layer 206 may be formed and characterized by a thickness T1, and the recessed portion 207 may extend into the first dielectric layer 206 at a depth T2, wherein the depth T2 is substantially less than the thickness T1. For example, the thickness T1 may be in the range of about 150 nanometers (nm) to about 180 nanometers, while the depth T2 may be in the range of about 120 nanometers to about 150 nanometers. In some embodiments, the recessed portion 207 may be characterized by a width (or cross-sectional length) W1 in a second direction (e.g., the X direction) intersecting the first direction, such as... Figure 3As shown. Such a width W1 can be associated with (e.g., defined by) a critical dimension of a certain patterning process (e.g., optical lithography) to form the recessed portion 207. For example, the width W1 can range from 30 nanometers to 80 nanometers. The recessed portion 207 can be formed to gradually taper from the top surface of the first dielectric layer 206 toward the substrate 202. The recessed portion 207 does not need to be formed to have a substantially small size (e.g., W1). In this way, the cost and / or resources (e.g., the number of photoresist layers in an optical lithography process) of forming the recessed portion 207 can be significantly reduced. According to some embodiments, the recessed portion 207 can have an aspect ratio (T2 / W1) greater than 1.5 to facilitate the formation of holes. Details of the holes will be discussed below.

[0132] Corresponding to Figure 1 Operation 106, Figure 4 This is a cross-sectional view of a semiconductor device 200 including a hole 210 formed in the second dielectric layer 208. The hole 210 is formed simultaneously with the formation of the second dielectric layer 208, which will be discussed in further detail below. The hole 210 is formed to be perpendicularly aligned with the conductive feature 204. In some embodiments, the hole 210 is characterized by a width (or cross-sectional length) W2 along the X direction, which is generally smaller than the width W1 of the recessed portion 207. For example, the width W2 may be less than or equal to 1 / 3 of the width W1. In another example, the width W2 may be less than or equal to 1 / 2 of the width W1. In this way, the hole 210 can then be used to form a contact feature that inherits the width W2 of the hole 210 and is self-aligned with the conductive feature 204. This further reduces the critical size of such a contact feature beyond the limits of optical lithography processes.

[0133] In one embodiment, a suitable deposition process (e.g., chemical vapor deposition, physical vapor deposition, etc.) is used to form the second dielectric layer 208, wherein the deposition process is adjusted such that the recessed portion 207 and the deposition rate are such that the deposition process will not completely fill the recessed portion 207, but will instead form the desired aperture 210 in the second dielectric layer 208. As a non-limiting example, when the depth and width of the recessed portion 207 are as described above... Figure 3As described, when silicon oxide (an exemplary material of the second dielectric layer 208) is deposited therein, the deposition process can begin by introducing a precursor such as silane (SiH4) and oxygen (O2) into the first dielectric layer 206. In one embodiment, silane is introduced at a flow rate between about 100 (standard cubic centimeter per minute; sccm) and about 10,000 sccm, such as about 2,000 sccm, while oxygen is introduced at a flow rate between about 500 sccm and about 10,000 sccm, such as about 4,000 sccm. Furthermore, deposition can be performed at a temperature between about 200°C and about 500°C, such as about 400°C, and at a pressure between about 0.1 Torr and about 10 Torr, such as about 3 Torr.

[0134] By using these process parameters, a relatively high deposition rate can be achieved to deposit the second dielectric layer 208, such as a deposition rate between about 1 nanometer / second and about 10 nanometer / second (e.g., about 3 nanometer / second). At such a deposition rate, and with the dimensions of the recessed portion 207 as described above, vias 210 can be formed in the second dielectric layer 208. In some other embodiments, the second dielectric layer 208 may comprise any other suitable dielectric material, such as silicon nitride, silicon carbide, silicon oxynitride, polysilicon, or combinations thereof, while still remaining within the scope of this disclosure. According to various embodiments of this disclosure, the first dielectric layer 206 and the second dielectric layer 208 may comprise similar or different dielectric materials, provided that the two dielectric materials are characterized by different etch properties (e.g., certain etchants with different etch rates).

[0135] Corresponding to Figure 1 Operation 108, Figure 5 This is a cross-sectional view of a semiconductor element 200 in which contact holes 212 are formed. In some embodiments, this can be achieved through a second dielectric layer 208 ( Figure 4 The first dielectric layer 206 and the second dielectric layer 208 are etched together to form the contact hole 212. The etching process 213 can be anisotropic or directional etching, wherein the etchant (e.g., particles, ions, or plasma) can be guided along a specific direction (e.g., the Y direction). As described above, the first dielectric layer 206 and the second dielectric layer 208 can be characterized at different etch rates. Accordingly, a portion of the second dielectric layer 208 (hereinafter referred to as the "spacer layer" 214) can maintain a thickness W3, such as... Figure 7 As shown. The spacer layer 214 may extend along the upper part of the inner sidewall 206S of the first dielectric layer 206. As will be described below, when the contact hole 212 (and the recessed portion 207) is filled with a conductive material, the spacer layer 214 may protect one or more other conductive features in the first dielectric layer 206 and / or on the substrate 202 from damage.

[0136] Furthermore, according to various embodiments, when the second dielectric layer 208 is etched, the hole 210 facilitates the etchant of the etching process 213 to remove a portion of the second dielectric layer 208 directly beneath the hole 210, and subsequently a portion of the first dielectric layer 206 directly beneath the hole 210 also forms a contact hole 212. This etching process 213 is guided to be substantially parallel to the direction in which the hole 210 extends (e.g., the Y direction). Therefore, the contact hole 212 can be "self-aligned" with the hole 210, resulting in the contact hole 212 inheriting the width W2 of the hole 210. Unlike the prior art, the prior art typically requires additional cost and / or resources to reduce the recessed portion 207 (regarding...). Figure 3 The critical size of the contact hole 212 (as discussed in the previous section) can be formed to have a size that is substantially smaller than that of the recessed portion 207. Figure 3 The width W1 of the aperture 210 may be greater than or exceed the limits of optical lithography processes. Alternatively or additionally, etching process 213 may comprise one or more etching processes, each with similar or different etching conditions, thereby creating contact holes 212 and etching through a portion of the first dielectric layer 206 beneath the holes 210, such as... Figure 6 As shown. In this way, at least a portion of the upper surface of the conductive feature 204 can be exposed.

[0137] Corresponding to Figure 1 Operation 110, Figure 7 This is a cross-sectional view of a semiconductor element 200 including contact features 216. Contact holes 212 can be filled with a conductive material. Figure 5 and Figure 6 The conductive material is then subjected to a grinding process (e.g., chemical mechanical polishing (CMP)) to form contact features 216. The conductive material may include metallic materials such as copper (Cu), aluminum (Al), tungsten (W), or combinations thereof.

[0138] As shown in some embodiments, contact feature 216 includes an upper portion 216U and a lower portion 216L. The upper portion 216U is laterally spaced (or surrounded) from the upper portion of the inner sidewall 206S of the first dielectric layer 206 by a spacer layer 214. Thus, the upper portion 216U may have a width (or cross-sectional length) W4, which may be equal to W1-2W3. Conversely, the lower portion 216L, formed by the hole 210, contacts the lower portion of the inner sidewall 206S of the first dielectric layer 206. Therefore, the lower portion 216L may inherit the width W2 of the hole 210, which is approximately or less than 1 / 3 of the width W1. In some embodiments, the width W2 may be approximately or less than 1 / 2 of the width W1. Given different dimensions for the upper and lower portions of the contact feature 216, the contact feature 216 may include (or otherwise define) an intermediate boundary 216I at the intersection of the upper portion 216U and the lower portion 216L. In some embodiments, the intermediate boundary 216I may be substantially parallel to the X direction.

[0139] Contact hole 212 is formed by using hole 210. Figure 5 and Figure 6 The critical dimension (e.g., width W2) of the lower portion 216L of the formed contact feature 216 can be substantially smaller than the width W1, which may sometimes be limited by the optical lithography process. Furthermore, by extending the inner sidewall 206S of the first dielectric layer 206 with a spacer layer 214, a plurality of contact features (some of which may resemble contact feature 216) can be formed relatively close to each other. The spacer layer 214 can serve as an additional protective layer (relative to the first dielectric layer 206) to electrically isolate adjacent contact features.

[0140] Figure 8A and Figure 8B Cross-sectional and top views of an illustrative semiconductor device 800 are shown, which includes at least one of the contact features disclosed herein. Figure 8A As shown, semiconductor device 800 includes two transistors 802 and 804 formed on substrate 801. Transistor 802 includes a gate feature (or electrode) 802G, a drain feature 802D, and a source feature 802S; and transistor 804 is formed in a well 803 of substrate 801, including a gate feature (or electrode) 804G, a drain feature 804D, and a source feature 804S. In an example where substrate 801 is P-type doped, well 803 may be N-type doped. Therefore, transistor 802 may be an N-type transistor, and transistor 804 may be a P-type transistor. Although transistors 802 and 804 are depicted as planar transistors in the illustrative embodiment of FIG. 8, it should be understood that each transistor may comprise any other type of transistor (e.g., FinFET, nanowire transistor, or nanosheet transistor) and is still within the scope of this disclosure.

[0141] In some cases, the formed gate features 802G and 804G may be substantially close to each other. Therefore, the method disclosed herein can be helpful in forming one or more contact features, such as contact features 806 and contact features 808, between such substantially close gate features. For example, although the respective dimensions of the upper portion 806U of contact feature 806 and the upper portion 808U of contact feature 808 may be limited by the optical lithography process, the lower portion 806L of contact feature 806 and the upper portion 808L of contact feature 808, which are actually connected to conductive features (e.g., 802S and 804D), can still be formed with dimensions exceeding (e.g., less than) the limit. Furthermore, since the upper portions 806U and 808U are separated from the low dielectric constant dielectric layer 805 by spacer layers 807 and 809, spacer layers 807 and 809 can protect gate features 802G and gate features 804G from damage when forming contact features 806 and contact features 808.

[0142] Figure 8B A corresponding top view of the semiconductor element 800 is shown. In some embodiments, Figure 8B This allows for the layout design of semiconductor device 800. As shown in the figure, Figure 8A Each feature shown can be based on Figure 8B The patterns are formed by the respective patterns. For example, the pattern used to form the gate feature 802G may extend across the pattern used to form the source / drain features 802S / 802D; the pattern used to form the gate feature 802G may extend across the pattern used to form the source / drain features 802S / 802D, which is surrounded by the pattern used to form the well 803; and the pattern used to form the contact features 806 and 808 (e.g., pattern 850) may overlap with portions of the source feature 802S and the drain feature 804D. It should be noted that, when viewed from the top, each contact feature 806 and contact feature 808 may be surrounded by its respective spacer layer (e.g., spacer layer 807 and spacer layer 809).

[0143] Figure 9A and Figure 9B Cross-sectional and top views of another exemplary semiconductor device 900 are shown, which includes at least one of the contact features disclosed herein. Figure 9A As shown, semiconductor device 900 includes two transistors, transistor 902 and transistor 904. Transistor 902 includes a gate feature (or electrode) 902G, a drain feature 902D, and a source feature 902S; transistor 904 includes a gate feature (or electrode) 904G, a drain feature 904D, and a source feature 904S. Although in Figure 1In the illustrative embodiments, transistors 902 and 904 are depicted as planar transistors. It should be understood that each transistor may comprise any other type of transistor (e.g., FinFET, nanowire transistor, or nanosheet transistor) and is still within the scope of this disclosure. Semiconductor element 900 may include two contact features, contact feature 906 and contact feature 908, which are electrically connected to source / drain features 902S / 904D and gate feature 904G, respectively. Each contact feature 906 and contact feature 908 may include an upper portion and a lower portion. As shown, contact feature 906 includes an upper portion 906U separated from the low-dielectric-constant layer 905 by a spacer layer 907, and a lower portion 906L electrically connected to the source / drain features 902S / 904D; and contact feature 908 includes an upper portion 908U separated from the low-dielectric-constant layer 905 by a spacer layer 909, and a lower portion 908L electrically connected to the gate feature 904G.

[0144] Figure 9B A corresponding top view of the semiconductor element 900 is shown. In some embodiments, Figure 9B This allows for the layout design of semiconductor device 900. As shown in the figure, Figure 9A Each feature shown can be based on Figure 9B The patterns are formed by the respective patterns. For example, the pattern used to form the gate feature 902G may extend across the patterns used to form the drain / source features 902D / 902S / 904D / 904S, and another pattern (e.g., pattern 920) used to form other source / drain features; the pattern used to form the gate feature 904G may extend across the patterns used to form the drain / source features 902D / 902S / 904D / 904S, and pattern 920; and the pattern used to form the contact features 906 and 908 (e.g., pattern 950) may overlap with portions of the source / drain features 902S / 904D and the gate feature 904G. It should be noted that, when viewed from above, each contact feature 906 and contact feature 908 may be surrounded by its respective spacer layer (e.g., spacer layer 907 and spacer layer 909).

[0145] Figure 10A and Figure 10B Perspective and top views of another exemplary semiconductor device 1000 are shown, which include at least one of the contact features disclosed herein. Figure 10AAs shown, semiconductor device 1000 includes two transistors, transistor 1002 and transistor 1004, formed on substrate 1001. Transistor 1002 includes a gate feature (or electrode) 1002G, a drain feature 1002D, and a source feature 1002S; and transistor 1004 includes a gate feature (or electrode) 1004G, a drain feature 1004D, and a source feature 1004S. Although in Figure 10A In the illustrative embodiments, transistors 1002 and 1004 are shown as FinFETs. It should be understood that each transistor may comprise any other type of non-planar transistor (e.g., nanowire transistor or nanosheet transistor) while still within the scope of this disclosure. The semiconductor element 1000 may include two contact features, contact features 1006 and 1008, electrically connected respectively to the drain / source features 1002D / 1004S and the gate feature 1004G. Each contact feature 1006 and contact feature 1008 may include an upper portion and a lower portion, as shown above.

[0146] Figure 10B A corresponding top view of the semiconductor element 1000 is shown. In some embodiments, Figure 10B This allows for the layout design of semiconductor device 1000. As shown in the figure, Figure 9A Each feature shown can be based on Figure 9B Each pattern is formed from its own design. For example, Figure 10A Each feature shown can be based on Figure 10B The patterns are formed by the respective elements. For example, the pattern used to form the gate feature 1002G may extend across the patterns used to form the source / drain features 1002S / 1002D / 1004S / 1004D; the pattern used to form the gate feature 904G may extend across the patterns used to form the source / drain features 1002S / 1002D / 1004S / 1004D; and the pattern used to form the contact features 1006 and 1008 (e.g., pattern 1050) may overlap with portions of the source / drain features 1002D / 1004S and the gate feature 1004G. It should be noted that each contact feature 1006 and contact feature 1008 may be surrounded or arranged by its respective spacer layer.

[0147] Figure 11A and Figure 11B A perspective view and a top view of another exemplary semiconductor element 1100 are shown, which include at least one of the contact features disclosed herein. For example... Figure 11AAs shown, semiconductor device 1100 includes transistor 1102 formed on substrate 1101. Transistor 1102 includes a gate feature (or electrode) 1102G, a drain feature 1102D, and a source feature 102S. Although in Figure 1 In the illustrative embodiment, transistor 1102 is depicted as a FinFET; however, it should be understood that the transistor may comprise any other type of non-planar transistor (e.g., nanowire transistor or nanosheet transistor) while still within the scope of this disclosure. Semiconductor element 1100 may include four contact features: contact feature 1104, contact feature 1106, contact feature 1108, and contact feature 1110. Contact features 1104 and 1106 are electrically connected to source feature 1102S, and contact features 1108 and 1110 are electrically connected to drain feature 1102D. Each of contact features 1104 through 1110 may include an upper portion and a lower portion, as shown above.

[0148] Figure 11B A corresponding top view of the semiconductor element 1100 is shown. In some embodiments, Figure 11B This allows for the layout design of semiconductor device 1100. As shown in the figure, Figure 11A Each feature shown can be based on Figure 11B The respective patterns are formed. For example, the pattern used to form the gate feature 1102G may extend across the patterns used to form the source / drain features 1102S / 1102D; the pattern used to form contact features 1104 and 1106 (e.g., pattern 1150) may partially overlap with the source feature 1102S; and the pattern used to form contact features 1108 and 1110 (e.g., pattern 1155) may partially overlap with the drain feature 1102D. It should be noted that each of the contact features 1004 to 1010 may be surrounded or arranged by its respective spacer layer.

[0149] Figure 12 and Figure 13 Illustrative top views of the contact features disclosed herein are shown. For example, in Figure 12 In this embodiment, contact feature 1200 includes an upper portion 1200U and a lower portion 1200L. In some embodiments, the upper portion 1200U and the lower portion 1200L may each be formed as a circular shape and concentric with each other. Therefore, the lower portion 1200L may be characterized by a diameter (or cross-sectional length) smaller than that of the upper portion 1200U. Figure 13In another example, contact feature 1300 includes an upper portion 1300U and a lower portion 1300L. In some embodiments, the upper portion 1300U and the lower portion 1300L are respectively shaped as a square or a rectangle, extending along a specific direction (e.g., the X direction). Thus, the lower portion 1300L can be characterized by being smaller than the width (or cross-sectional length) W1 of the upper portion 1300U and the width (or cross-sectional length) W2 (in the direction perpendicular to the X direction).

[0150] The foregoing summary describes the features of many embodiments, thus enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that other processes and structures can be designed or modified based on this disclosure to achieve the same purpose and / or the same advantages as the described embodiments. Those skilled in the art should also understand that equivalent architectures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure.

[0151] This disclosure provides a semiconductor device comprising: a first conductive feature, a first dielectric layer disposed above the first conductive feature, and a first contact feature extending through the first dielectric layer and electrically coupled to the first conductive feature. The upper portion of the first contact feature is laterally separated from a first inner sidewall of the first dielectric layer via a second dielectric layer, and the lower portion of the first contact feature is in contact with the first inner sidewall of the first dielectric layer. In some embodiments, the first conductive feature includes a feature selected from the group consisting of a drain feature of a first transistor, a source feature of a first transistor, a gate feature of a first transistor, and a first interconnect feature laterally extending in a metallized layer. In some embodiments, the semiconductor device further includes: a second conductive feature, and a second contact feature extending through the first dielectric layer and electrically coupled to the second conductive feature; wherein the upper portion of the second contact feature is laterally separated from a second inner sidewall of the first dielectric layer via a third dielectric layer, the third dielectric layer being substantially similar to the second dielectric layer. In some embodiments, the second conductive feature includes a feature selected from the group consisting of the drain feature of the first transistor, the source feature of the first transistor, the gate feature of the first transistor, the drain feature of the second transistor, the source feature of the second transistor, the gate feature of the second transistor, and a second interconnect feature laterally extending in the metallized layer. In some embodiments, each of the second and third dielectric layers is characterized by a first etch rate different from the second etch rate of the first dielectric layer. In some embodiments, the second dielectric layer includes a material selected from the group consisting of oxide-based dielectric materials, nitride-based dielectric materials, and polysilicon materials. In some embodiments, the first lateral width of the lower portion is substantially smaller than the sum of the second lateral width of the upper portion and the thickness of the second dielectric layer. In some embodiments, the first lateral width of the lower portion is equal to or less than one-third of the sum of the second lateral width of the upper portion and one or more thicknesses of the second dielectric layer. In some embodiments, the first contact feature further includes a lateral boundary at the intersection of the upper and lower portions.

[0152] Another aspect of this disclosure provides a semiconductor device comprising: a conductive feature, a dielectric layer disposed above the conductive feature, and a contact feature extending through the dielectric layer; wherein the contact feature has an upper portion and a lower portion, the upper portion being separated from the dielectric layer by a spacer layer, and the lower portion being electrically coupled to the conductive feature and in contact with the dielectric layer. In some embodiments, a first lateral width of the lower portion of the contact feature is equal to or less than one-third of the sum of a second lateral width of the upper portion of the contact feature and the thickness of one or more spacer layers. In some embodiments, the spacer layer comprises a material selected from the group consisting of oxide-based dielectric materials, nitride-based dielectric materials, and polycrystalline silicon materials. In some embodiments, the first conductive feature comprises a feature selected from the group consisting of a drain feature of a transistor, a source feature of a transistor, a gate feature of a transistor, and interconnect features laterally extending in a metallized layer.

[0153] Another aspect of this disclosure is a method of fabricating a semiconductor device, comprising: recessing an upper portion of a first dielectric layer disposed above a conductive feature; filling the upper portion of the recess with a second dielectric layer to form a hole embedded in the second dielectric layer; etching the second dielectric layer and the first dielectric layer to form a contact hole, the contact hole exposing at least a portion of the conductive feature such that at least a lower portion of the contact hole is perpendicularly aligned with the conductive feature; and filling the contact hole with a conductive material to form a contact feature electrically coupled to the conductive feature. In some embodiments, filling the upper portion of the recess with the second dielectric layer to form a hole further comprises: adjusting the deposition rate of filling the second dielectric layer to form a protrusion of the second dielectric layer, the protrusion comprising a first portion and a second portion extending laterally toward each other to surround the hole. In some embodiments, etching the second dielectric layer and the first dielectric layer to form a contact hole further comprises: etching a portion of the second dielectric layer and a portion of the first dielectric layer, wherein each of these portions is perpendicularly aligned to the hole, thus leaving a residual portion of the second dielectric layer extending along the inner sidewall of the upper portion of the contact hole. In some embodiments, etching the second dielectric layer and the first dielectric layer to form a contact hole further comprises: etching the second dielectric layer and the first dielectric layer to form the upper portion of the contact hole, while leaving a residual portion of the second dielectric layer extending along the inner sidewall of the upper portion of the contact hole and etching the first dielectric layer through the formation of the lower portion of the contact hole to expose conductive features. In some embodiments, the method of fabricating a semiconductor device further comprises: grinding the first dielectric layer and the second dielectric layer to form substantially flat surfaces prior to etching the second dielectric layer and the first dielectric layer to form a contact hole. In some embodiments, the first lateral width of the recessed upper portion is substantially greater than the second lateral width of the lower portion of the contact hole. In some embodiments, the first lateral width of the upper recess is equal to or greater than three times the second lateral width of the lower part of the contact hole.

Claims

1. A semiconductor device, characterized in that, Include: First electrical conductivity characteristic; A first dielectric layer is disposed above the first conductive feature; and A first contact feature extends through the first dielectric layer, and the first contact feature is electrically coupled to the first conductive feature; The upper part of the first contact feature is laterally separated from a first inner sidewall of the first dielectric layer through a second dielectric layer, and the lower part of the first contact feature is in contact with the first inner sidewall of the first dielectric layer. The first contact feature includes an intermediate boundary that extends laterally from a lower edge of the upper sidewall to an upper edge of the lower sidewall.

2. The element according to claim 1, characterized in that, The first conductive feature includes a feature selected from a group consisting of a drain feature of a first transistor, a source feature of the first transistor, a gate feature of the first transistor, and a first interconnect feature extending laterally in a metallized layer.

3. The element according to claim 2, characterized in that, Also includes: A second conductive characteristic; and A second contact feature extends through the first dielectric layer and is electrically coupled to the second conductive feature; The upper part of the second contact feature is laterally separated from a second inner wall of the first dielectric layer by a third dielectric layer, which is substantially similar to the second dielectric layer.

4. The element according to claim 3, characterized in that, The second conductive feature includes a feature selected from a group consisting of the drain feature of the first transistor, the source feature of the first transistor, the gate feature of the first transistor, a drain feature of a second transistor, a source feature of the second transistor, a gate feature of the second transistor, and a second interconnect feature extending laterally in the metallized layer.

5. The element according to claim 3, characterized in that, Each of the second dielectric layer and the third dielectric layer is characterized at a first etch rate, which is different from the second etch rate of the first dielectric layer.

6. The element according to claim 1, characterized in that, The second dielectric layer comprises a material selected from a group consisting of an oxide-based dielectric material, a nitride-based dielectric material, and a polycrystalline silicon material.

7. The element according to claim 1, characterized in that, The first lateral width of the lower portion is substantially smaller than the sum of the second lateral width of the upper portion and the thickness of the second dielectric layer.

8. The element according to claim 1, characterized in that, The first lateral width of the lower portion is equal to or less than one-third of the sum of the second lateral width of the upper portion and the thickness of one or more of the second dielectric layer.

9. The element according to claim 6, characterized in that, The first contact feature is also included at a lateral boundary at an intersection of the upper and lower parts.

10. A semiconductor element, characterized in that, Include: One electrical conductivity characteristic; A dielectric layer is disposed above the conductive feature; and A contact feature extends and penetrates the dielectric layer; The contact feature has an upper portion and a lower portion. The upper portion is separated from the dielectric layer by a spacer layer, and the lower portion is electrically coupled to the conductive feature and in contact with the dielectric layer. The contact feature includes an intermediate boundary that extends laterally from a lower edge of the upper sidewall to an upper edge of the lower sidewall.

11. The element according to claim 10, characterized in that, The lower portion of the contact feature has a first lateral width equal to or less than one-third of the upper portion of the contact feature and the sum of the thickness of one or more of the spacer layers.

12. The element according to claim 10, characterized in that, The spacer layer comprises a material selected from a group consisting of an oxide-based dielectric material, a nitride-based dielectric material, and a polycrystalline silicon material.

13. The element according to claim 10, characterized in that, The conductive feature includes a feature selected from a group consisting of a drain feature of a transistor, a source feature of the transistor, a gate feature of the transistor, and an interconnect feature extending laterally in a metallized layer.

14. A method for manufacturing a semiconductor device, characterized in that, Include: A recess is provided on the upper part of a first dielectric layer above a conductive feature; The upper part of the recess is filled with a second dielectric layer to form a hole embedded in the second dielectric layer, wherein the width of the recess is greater than the width of the hole; The second dielectric layer and the first dielectric layer are etched to form a contact hole, which exposes at least a portion of the conductive feature so that at least a lower portion of the contact hole is perpendicularly aligned with the conductive feature. as well as The contact hole is filled with a conductive material to form a contact feature electrically coupled to the conductive feature.

15. The method according to claim 14, characterized in that, Filling the upper part of the depression with a second dielectric layer to form a hole also includes: Adjust a deposition rate to fill the second dielectric layer to form a protrusion of the second dielectric layer, the protrusion comprising a first portion and a second portion extending laterally toward each other to surround the hole.

16. The method according to claim 14, characterized in that, Etching the second dielectric layer and the first dielectric layer to form a contact hole further includes: A portion of the second dielectric layer and a portion of the first dielectric layer are etched, each of the portion of the second dielectric layer and the portion of the first dielectric layer being vertically aligned with the hole, thus leaving a residual portion of the second dielectric layer extending along an inner sidewall of an upper portion of the contact hole.

17. The method according to claim 14, characterized in that, Etching the second dielectric layer and the first dielectric layer to form a contact hole further includes: The second dielectric layer and the first dielectric layer are etched to form an upper part of the contact hole, while leaving a residual portion of the second dielectric layer extending along an inner sidewall of the upper part of the contact hole. as well as The first dielectric layer is etched by forming the lower part of the contact hole to expose the conductive feature.

18. The method according to claim 14, characterized in that, Also includes: Before etching the second dielectric layer and the first dielectric layer to form a contact hole, the first dielectric layer and the second dielectric layer are ground to form a substantially flat surface.

19. The method according to claim 14, characterized in that, The upper part of the recess has a first lateral width that is substantially greater than the lower part of the contact hole has a second lateral width.

20. The method according to claim 14, characterized in that, The upper part of the recess has a first lateral width that is equal to or greater than three times the lower part of the contact hole has a second lateral width.

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