Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a manufacturing method thereof. The display panel includes: a substrate and a thin-film transistor; the thin-film transistor includes: an active layer, a first electrode, a second electrode, an insulating layer, and a gate; the active layer is disposed on the substrate; the first electrode and the second electrode respectively cover portions of the active layer and form a gap region exposing the active layer; the insulating layer covers the first electrode, the second electrode, and the gap region and forms a groove in the gap region; the gate is accommodated in the groove. The present application accommodates the gate in the groove of the insulating layer, and the groove is located in the gap region between the first electrode and the second electrode, so that the orthographic projections of the first electrode and the second electrode on the substrate do not overlap with the orthographic projection of the gate on the substrate, thereby achieving automatic alignment of the gate with the first electrode and the second electrode, reducing the parasitic capacitance of the display panel, reducing the impact of capacitive coupling on the display panel drive signal, and improving the display quality of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof. Background Art

[0002] Existing mainstream display technologies include liquid crystal display (LCD) technology, organic light emitting diode (OLED) display technology and micro light emitting diode (Micro LED) display technology. Regardless of the display technology, the driving element is often a thin-film transistor (TFT).

[0003] In the manufacturing process of existing display panels, deformation caused by changes in temperature or stress can lead to the pattern alignment between the film layers in the thin film transistor not being completely consistent. For example, when the gate deviates from the channel region of the active layer, the thin film transistor will not be able to open or close normally under the control of the gate, seriously affecting the performance of the device. In order to avoid the occurrence of the above problems, the current common practice is to increase the area of ​​the gate so that there is a certain amount of overlap between the gate and the source and drain. Although this method can avoid the deterioration of device performance caused by slight alignment deviations, the overlapping setting of the gate and the source and drain will introduce parasitic capacitance in the display panel. The parasitic capacitance will affect the driving signal of the display panel, thereby affecting the display quality. Therefore, how to avoid the overlap of the gate and the source and drain, thereby avoiding the introduction of parasitic capacitance, is a major problem to be solved by R&D personnel. Summary of the Invention

[0004] The present application provides a display panel and a manufacturing method thereof, which can avoid overlap between the gate and the source and drain, reduce the parasitic capacitance of the display panel, reduce the influence of capacitive coupling on the display panel driving signal, and improve the display quality of the display panel.

[0005] In order to achieve the above-mentioned objectives, the display panel and the manufacturing method thereof of the present application adopt the following technical solutions.

[0006] On the one hand, the present application provides a display panel, which includes: a base substrate and a thin film transistor arranged on the base substrate; the thin film transistor includes: an active layer, a first electrode, a second electrode, an insulating layer and a gate, wherein the active layer is arranged on the base substrate; the first electrode and the second electrode respectively cover part of the active layer and form a gap area exposing the active layer; the insulating layer covers the first electrode, the second electrode and the gap area, and forms a groove in the gap area; the gate is accommodated in the groove.

[0007] Optionally, the gate is made of conductive photoresist, which is in a liquid state with leveling properties in a first state and in a stable solid state in a second state.

[0008] Optionally, the active layer includes a channel region, the bottom of the groove covers the channel region, and the gate covers the bottom of the groove.

[0009] Optionally, the active layer also includes a first electrode region and a second electrode region located on both sides of the channel region, wherein the first electrode includes a first part and a second part, the first part is arranged on the first electrode region, and the second part is arranged on the base substrate; the second electrode includes a third part and a fourth part, the third part is arranged on the second electrode region, and the fourth part is arranged on the base substrate.

[0010] Optionally, the thicknesses of the first portion and the third portion are both the first thickness, the thickness of the gate is the second thickness, and the second thickness is smaller than the first thickness.

[0011] Optionally, the display panel further includes scan lines and data lines cross-arranged on the base substrate, wherein the scan lines are arranged in different layers from the respective film layers in the thin film transistor and are electrically connected to the gate; the data lines are arranged in the same layer as the first electrode and the second electrode and are electrically connected to one of the first electrode or the second electrode.

[0012] Optionally, the display panel further includes an overlapping portion located outside the gap area, wherein the overlapping portion is provided in the same layer as the gate and is electrically connected to the gate and the scan line respectively.

[0013] On the other hand, the present application further provides a method for manufacturing a display panel, the method comprising the following steps:

[0014] forming a patterned active layer on a substrate;

[0015] forming a patterned electrode layer, the electrode layer comprising a first electrode and a second electrode, the first electrode and the second electrode respectively covering a portion of the active layer, and forming a gap region between the first electrode and the second electrode to expose the active layer;

[0016] forming an insulating layer, the insulating layer covering the first electrode, the second electrode and the gap region, and forming a groove in the gap region;

[0017] coating a conductive photoresist with leveling properties on the insulating layer, wherein after coating, at least a portion of the conductive photoresist above the first electrode and the second electrode flows into a region where the first electrode and the second electrode are not provided, and the region where the first electrode and the second electrode are not provided includes the groove;

[0018] The conductive photoresist is exposed, developed and stripped, and the conductive photoresist remaining in the groove is converted into a gate with a stable shape.

[0019] Optionally, before exposing, developing and stripping the conductive photoresist, the method further includes the following steps: removing the conductive photoresist remaining on the first electrode and the second electrode by a plasma ashing process.

[0020] Optionally, after forming the gate having a stable shape, the method further includes the following steps: forming a patterned metal layer, wherein the metal layer includes a scan line electrically connected to the gate.

[0021] The present application places the gate in a groove of the insulating layer, and the groove is located in the gap area between the first electrode and the second electrode, so that the orthographic projections of the first electrode and the second electrode on the substrate do not overlap with the orthographic projection of the gate on the substrate, thereby achieving automatic alignment of the gate with the first electrode and the second electrode, reducing the parasitic capacitance of the display panel, reducing the impact of capacitive coupling on the display panel driving signal, and improving the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a schematic cross-sectional view of a thin film transistor in a display panel in the prior art;

[0024] Figure 2A schematic cross-sectional view of a region including a thin film transistor in a display panel provided by an embodiment of the present application;

[0025] Figure 3 A schematic plan view of a region containing thin film transistors in a display panel provided by an embodiment of the present application;

[0026] Figure 4 A schematic diagram of the manufacturing process of a display panel provided in an embodiment of the present application;

[0027] Figure 5a 、 5b Schematic cross-sectional view and schematic plan view of a region of the display panel including a thin film transistor corresponding to step S01, respectively;

[0028] Figure 6a 、 6b are respectively a cross-sectional schematic diagram and a planar schematic diagram of a region of the display panel including a thin film transistor corresponding to step S02;

[0029] Figure 7a 、 7b are respectively a cross-sectional schematic diagram and a plan schematic diagram of a region of the display panel including a thin film transistor corresponding to step S03;

[0030] Figure 8a 、 8b are respectively a cross-sectional schematic diagram and a planar schematic diagram of a region of the display panel including the thin film transistor corresponding to step S04;

[0031] Figure 9a 、 9b 1 and 2 are respectively a cross-sectional schematic diagram and a plan schematic diagram of a region including a thin film transistor in the display panel corresponding to step S05 . DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0033] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, examples of various specific processes and materials are provided in the present application, but a person of ordinary skill in the art will recognize the application of other processes and / or the use of other materials. Each of the following is described in detail. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0034] Figure 1 FIG. 1 is a cross-sectional diagram of a thin film transistor in a display panel in the prior art. Figure 1 As shown, the thin film transistor includes a base substrate 10' and a thin film transistor arranged on the base substrate 10', the thin film transistor includes a gate 20', a gate insulating layer 30', an active layer 40', and a source-drain layer stacked in sequence, wherein the active layer 40' includes a channel region 41', the source-drain layer includes a source electrode 51' and a drain electrode 52', the width of the gate 20' is greater than the width of the channel region 41', the orthographic projection of the gate 20' on the base substrate 10' partially overlaps with the orthographic projection of the source electrode 51' on the base substrate 10', and the orthographic projection of the gate 20' on the base substrate 10' partially overlaps with the orthographic projection of the drain electrode 52' on the base substrate 10'. In the prior art, in order to prevent the orthographic projection of the gate 20' in the thin film transistor on the active layer 40' from being unable to completely cover the channel region 41' due to deformation caused by changes in temperature or stress, the width of the gate 20' is made larger than the width of the channel region 41' during design, causing the orthographic projection of the gate 20' on the base substrate 10' to partially overlap with the orthographic projections of the source 51' and the drain 52' on the base substrate 10', thereby introducing parasitic capacitance, affecting the driving signal of the display panel, and further affecting the display quality.

[0035] The present application provides a display panel that can avoid the overlap problem between the gate and the source and drain, avoid the introduction of parasitic capacitance that affects the driving signal of the display panel, and improve display quality.

[0036] Figure 2 A schematic cross-sectional view of a region including a thin film transistor in a display panel provided by an embodiment of the present application; Figure 3 A schematic plan view of a region of a display panel including a thin film transistor according to an embodiment of the present application. Figure 2 and Figure 3As shown, the present application provides a display panel, which can be any one of a liquid crystal display panel, an organic light emitting diode display panel, and a micro light emitting diode display panel. The display panel includes: a base substrate 10 and a thin film transistor disposed on the base substrate 10. The thin film transistor includes: an active layer 20, a first electrode 31, a second electrode 32, an insulating layer 40, and a gate 50, wherein the active layer 20 is disposed on the base substrate 10; the first electrode 31 and the second electrode 32 respectively cover a portion of the active layer 20 and form a gap region exposing the active layer 20; the insulating layer 40 covers the first electrode 31, the second electrode 32, and the gap region, and forms a groove 401 in the gap region; the gate 50 is accommodated in the groove 401. In the present application, since the gate 50 is arranged in the groove 401 of the insulating layer 40, and the groove 401 is located in the gap area between the first electrode 31 and the second electrode 32, the orthographic projection of the first electrode 31 and the second electrode 32 on the base substrate 10 does not overlap with the orthographic projection of the gate 50 on the base substrate 10, thereby achieving automatic alignment of the gate 50 with the first electrode 31 and the second electrode 32, reducing the parasitic capacitance of the display panel, reducing the influence of capacitive coupling on the display panel driving signal, and improving the display quality of the display panel.

[0037] In this embodiment, the base substrate 10 is a flexible substrate or a rigid substrate, and the base substrate 10 can be made of glass, plastic, polyimide, or the like.

[0038] In this embodiment, the thin film transistor may be any one of a metal oxide (Metal Oxide) thin film transistor, an amorphous silicon (a-Si) thin film transistor, and a low temperature polycrystalline silicon (LTPS) thin film transistor. Preferably, the thin film transistor is an indium gallium zinc oxide (IGZO) thin film transistor, which is a type of metal oxide thin film transistor.

[0039] In this embodiment, the active layer 20 is located on the base substrate 10. Other layers, such as a light shielding layer and a buffer layer, may be disposed between the active layer 20 and the base substrate 10. The active layer 20 includes a channel region 23 and a first electrode region 21 and a second electrode region 22 located on either side of the channel region 23. Preferably, the active layer 20 is made of a metal oxide semiconductor, and neither the first electrode region 21 nor the second electrode region 22 undergoes a conductorization process.

[0040] In this embodiment, the first electrode 31 covers a portion of the active layer 20, that is, at least a portion of the first electrode 31 is located on the active layer 20. Specifically, the first electrode 31 includes a first portion 311 and a second portion 312, which are adjacently disposed. The first portion 311 is disposed on the active layer 20 and covers the first electrode region 21 of the active layer 20; the second portion 312 is disposed on the base substrate 10 and covers the edge of the first electrode region 21.

[0041] In this embodiment, the second electrode 32 covers a portion of the active layer 20, that is, at least a portion of the second electrode 32 is located on the active layer 20. Specifically, the second electrode 32 includes a third portion 321 and a fourth portion 322, wherein the third portion 321 and the fourth portion 322 are adjacently disposed. The third portion 321 is disposed on the active layer 20 and covers the second electrode region 22 of the active layer 20; the fourth portion 322 is disposed on the base substrate 10 and covers the edge of the second electrode region 22.

[0042] In this embodiment, since the first electrode 31 covers the edge of the first electrode area 21 and the second electrode 32 covers the edge of the second electrode area 22, the channel area 23 can be protected to avoid the problem of device performance degradation caused by external ambient light irradiating the channel from the side.

[0043] In this embodiment, the first electrode 31 and the second electrode 32 are made of the same material, which can be a metal, alloy, or metal composite film containing at least one of Cu, Al, Mo, Nb, and Ti. The thickness of the first electrode 31 and the second electrode 32 are both within a range of 100 nm to 1000 nm. Furthermore, the thickness of the first electrode 31 and the second electrode 32 are both within a range of 400 nm to 1000 nm.

[0044] In this embodiment, the first electrode 31 is a source electrode, the second electrode 32 is a drain electrode, the first electrode region 21 is a source region, and the second electrode region 22 is a drain region. However, in other embodiments of the present application, the first electrode 31 may be a drain electrode, the second electrode 32 may be a source electrode, the first electrode region 21 may be a drain region, and the second electrode region 22 may be a source region.

[0045] In this embodiment, the first electrode 31 and the second electrode 32 are in the same layer and are spaced apart. The first electrode 31 and the second electrode 32 can be patterned in a single film forming process. A gap region exposing the active layer 20 is formed between the first electrode 31 and the second electrode 32. The orthographic projection of the gap region on the base substrate 10 covers the orthographic projection of the channel region 23 on the base substrate 10.

[0046] In this embodiment, the insulating layer 40 covers the first electrode 31, the second electrode 32, and the gap region, and forms a groove 401 in the gap region. This application utilizes the structure in which the first electrode 31 and the second electrode 32 protrude from the active layer 20 to form a groove 401 in the gap region on the insulating layer 40. The bottom of the groove 401 covers the channel region 23.

[0047] In this embodiment, the gate 50 is accommodated in the groove 401, so that the orthographic projection of the gate 50 on the base substrate 10 does not overlap with the orthographic projection of the first electrode 31 on the base substrate 10 and the orthographic projection of the second electrode 32 on the base substrate 10, thereby achieving automatic alignment of the gate 50 with the first electrode 31 and the second electrode 32, reducing the parasitic capacitance of the display panel, reducing the impact of capacitive coupling on the display panel driving signal, and improving the display quality of the display panel.

[0048] In this embodiment, the gate 50 covers the bottom of the groove 401, that is, the orthographic projection of the gate 50 on the active layer 20 covers the channel region 23, thereby enabling automatic alignment of the gate 50 and the channel region 23, thereby avoiding the failure problem of the thin film transistor being unable to open or close normally due to the offset of the gate 50 relative to the channel region 23.

[0049] In this embodiment, the gate 50 is made of a conductive photoresist, which can be a transparent conductive photoresist or an opaque conductive photoresist. The conductive photoresist is in a leveling liquid state in a first state and in a stable solid state in a second state. Specifically, the first state is the state of the conductive photoresist before exposure to light and / or heating, and the second state is the state of the conductive photoresist after exposure to light and / or heating. Among them, since the conductive photoresist is in a liquid state with leveling properties when not irradiated with light and / or heated, and at the same time, the insulating layer 40 uses the first electrode 31 and the second electrode 32 to protrude from the active layer 20 structure to form an uneven structure including the groove 401, therefore, when the conductive photoresist in the first state is coated on the insulating layer 40, most of the conductive photoresist located above the first electrode 31 and the second electrode 32 will flow into the groove 401 or other areas where the first electrode 31 and the second electrode 32 are not set; when the conductive photoresist in the first state is subjected to light and / or heat treatment, the conductive photoresist accommodated in the groove 401 is transformed from the first state to the second state, thereby forming a gate 50 with a stable shape and conductive function. Under the limitation of the groove 401, the gate 50 avoids the parasitic capacitance problem caused by the overlap of the gate 50 with the first electrode 31 and the second electrode 32 in the direction perpendicular to the base substrate 10.

[0050] In this embodiment, the thickness of the first portion 311 and the third portion 321 are both the first thickness, and the thickness of the gate 50 is the second thickness. The gate 50 is accommodated in the groove 401, and the thickness of the gate 50 is less than or equal to the depth of the groove 401, that is, the second thickness is less than or equal to the first thickness. Preferably, the thickness of the gate 50 is less than the depth of the groove 401, and the second thickness is less than the first thickness. In this state, the surface of the gate 50 is lower than the surface of the insulating layer 40 on both sides thereof, thereby reducing the risk of the gate 50 overlapping with the first electrode 31 and the second electrode 32 due to the conductive photoresist overflowing the groove 401.

[0051] In this embodiment, the display panel also includes a scanning line 60 and a data line 33 that are cross-arranged on the base substrate 10, wherein the scanning line 60 is arranged in a different layer from the various film layers in the thin film transistor (that is, the active layer, the electrode layer where the first electrode and the second electrode are located, the insulating layer and the gate layer where the gate is located), and is electrically connected to the gate 50; the data line 33 is arranged in the same layer as the first electrode 31 and the second electrode 32, and is electrically connected to one of the first electrode 31 or the second electrode 32.

[0052] In this embodiment, the scan line 60 is provided on the insulating layer 40, and the orthographic projection of the scan line 60 on the base substrate 10 does not overlap with the orthographic projection of the gate 50 on the base substrate 10. The display panel further includes a lap joint 51 located outside the gap region, the lap joint 51 being provided on the same layer as the gate 50, and being electrically connected to the gate 50 and the scan line 60, respectively. In this embodiment, the lap joint 51 is provided on the same layer as the gate 50, so that the lap joint 51 and the gate 50 can be formed in the same film forming process, but the present application does not limit the formation method of the lap joint 51. In other embodiments of the present application, the lap joint 51 can also be formed in the same film forming process as the scan line 60.

[0053] On the other hand, the present application also provides a method for manufacturing a display panel. Figure 4 、 Figure 5a 、 Figure 5b 、 Figure 6a 、 Figure 6b 、 Figure 7a 、 Figure 7b 、 Figure 8a 、 Figure 8b 、 Figure 9a 、 Figure 9b , the manufacturing method of the display panel comprises the following steps:

[0054] S01: forming a patterned active layer 20 on a base substrate 10;

[0055] S02: forming a patterned electrode layer, the electrode layer including a first electrode 31 and a second electrode 32, wherein the first electrode 31 and the second electrode 32 respectively cover a portion of the active layer, and a gap region 300 is formed between the first electrode 31 and the second electrode 32 to expose the active layer 20;

[0056] S03: forming an insulating layer 40 , wherein the insulating layer 40 covers the first electrode 31 , the second electrode 32 and the gap region 300 , and forms a groove 401 in the gap region 300 ;

[0057] S04: coating a conductive photoresist 500 with leveling properties on the insulating layer 40 . After coating, at least a portion of the conductive photoresist 500 located above the first electrode 31 and the second electrode 32 flows into a region where the first electrode 31 and the second electrode 32 are not provided. The region where the first electrode 31 and the second electrode 32 are not provided includes the groove 401 .

[0058] S05 : exposing, developing, and stripping the conductive photoresist 500 , so that the conductive photoresist 500 remaining in the groove 401 is transformed into a gate 50 with a stable shape.

[0059] In the manufacturing method of the above-mentioned display panel provided in the present application, since the material of the gate 50 is conductive photoresist, the conductive photoresist is in a liquid state with leveling properties when not subjected to light treatment. Therefore, after the liquid conductive photoresist 500 is coated on the uneven insulating layer 40, most of the conductive photoresist 500 located above the first electrode 31 and the second electrode 32 will spontaneously flow into the groove 401 or other areas where the first electrode 31 and the second electrode 32 are not set; after the conductive photoresist 500 is exposed, developed and stripped, the conductive photoresist 500 remaining in the groove 401 has been transformed from the original liquid state into a solid state with a stable form, thereby forming a gate 50 that does not overlap with the first electrode 31 and the second electrode 32 in a direction perpendicular to the base substrate 10, thereby avoiding the introduction of parasitic capacitance.

[0060] Moreover, in the actual preparation process, the active layer 20 of the present application does not need to undergo a conductorization process. When the position of the channel region 23 of the active layer 20 is determined, the gap area 300 between the first electrode 31 and the second electrode 32 is also relatively determined. When the gap area 300 is determined, the position of the groove 401 of the insulating layer 40 is also determined, and the position of the corresponding gate 50 can also be determined. Therefore, the display panel prepared by the display panel manufacturing method provided in the present application can not only realize automatic alignment of the gate 50 with the first electrode 31 and the second electrode 32, but also realize automatic alignment of the gate 50 with the channel region 23.

[0061] Furthermore, the step S04 further includes: using a plasma ashing process to remove the conductive photoresist 500 remaining above the first electrode 31 and the second electrode 32. Specifically, after the conductive photoresist 500 coated on the insulating layer 40 is fully leveled, in order to avoid a small amount of conductive photoresist 500 remaining in the area above the first electrode 31 and the second electrode 32, the present application further includes the following steps before exposing, developing, and stripping the conductive photoresist 500: using a plasma ashing process to remove the conductive photoresist remaining above the first electrode 31 and the second electrode 32, thereby reducing the overall thickness of the conductive photoresist 500 and making the thickness of the conductive photoresist 500 located in the groove 401 less than the depth of the groove 401.

[0062] Furthermore, after forming the gate 50 having a stable shape, the following step S06 is further included: forming a patterned metal layer on the insulating layer 40, the metal layer including a scan line electrically connected to the gate. The scan line can be electrically connected to the gate 50 via a lap joint, which can be formed in the same layer as the gate 50 in step S05, and the lap joint is located outside the groove 401.

[0063] In summary, the present application provides a display panel and a method for manufacturing the same, wherein the display panel includes: a base substrate and a thin film transistor disposed on the base substrate; the thin film transistor includes: an active layer, a first electrode, a second electrode, an insulating layer, and a gate, wherein the active layer is disposed on the base substrate; the first electrode and the second electrode respectively cover a portion of the active layer and form a gap region exposing the active layer; the insulating layer covers the first electrode, the second electrode, and the gap region and forms a groove in the gap region; the gate is accommodated in the groove. The present application accommodates the gate in the groove of the insulating layer, and the groove is located in the gap region between the first electrode and the second electrode, so that the orthographic projections of the first electrode and the second electrode on the base substrate do not overlap with the orthographic projection of the gate on the base substrate, thereby achieving automatic alignment of the gate with the first electrode and the second electrode, reducing the parasitic capacitance of the display panel, reducing the influence of capacitive coupling on the display panel drive signal, and improving the display quality of the display panel.

[0064] The above is a detailed introduction to a display panel and a manufacturing method thereof provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes: a base substrate and a thin film transistor disposed on the base substrate; the thin film transistor includes: an active layer, a first electrode, a second electrode, an insulating layer, and a gate electrode, wherein the active layer is disposed on the base substrate; the first electrode and the second electrode respectively cover a portion of the active layer and form a gap region exposing the active layer; the insulating layer covers the first electrode, the second electrode, and the gap region and forms a groove in the gap region; the gate electrode is accommodated in the groove; The gate is made of conductive photoresist. The conductive photoresist is in a liquid state with leveling properties in a first state and in a stable solid state in a second state.

2. The display panel according to claim 1, wherein: The active layer includes a channel region, the bottom of the groove covers the channel region, and the gate covers the bottom of the groove.

3. The display panel according to claim 2, wherein: The active layer also includes a first electrode region and a second electrode region located on both sides of the channel region, wherein the first electrode includes a first part and a second part, the first part is arranged on the first electrode region, and the second part is arranged on the base substrate; the second electrode includes a third part and a fourth part, the third part is arranged on the second electrode region, and the fourth part is arranged on the base substrate.

4. The display panel according to claim 3, wherein: The thicknesses of the first portion and the third portion are both a first thickness, the thickness of the gate is a second thickness, and the second thickness is smaller than the first thickness.

5. The display panel according to any one of claims 1 to 4, wherein: The display panel also includes scan lines and data lines cross-arranged on the base substrate, wherein the scan lines are arranged in different layers from the film layers in the thin film transistor and are electrically connected to the gate; the data lines are arranged in the same layer as the first electrode and the second electrode, and are electrically connected to one of the first electrode or the second electrode.

6. The display panel according to claim 5, wherein: The display panel further includes an overlapping portion located outside the gap area. The overlapping portion is provided in the same layer as the gate and is electrically connected to the gate and the scan line respectively.

7. A method for manufacturing a display panel, characterized in that: The following steps are involved: forming a patterned active layer on a substrate; forming a patterned electrode layer, the electrode layer comprising a first electrode and a second electrode, the first electrode and the second electrode respectively covering a portion of the active layer, and forming a gap region between the first electrode and the second electrode to expose the active layer; forming an insulating layer, the insulating layer covering the first electrode, the second electrode and the gap region, and forming a groove in the gap region; coating a conductive photoresist with leveling properties on the insulating layer, wherein after coating, at least a portion of the conductive photoresist above the first electrode and the second electrode flows into a region where the first electrode and the second electrode are not provided, and the region where the first electrode and the second electrode are not provided includes the groove; The conductive photoresist is exposed, developed and stripped, and the conductive photoresist remaining in the groove is converted into a gate with a stable shape.

8. The method for manufacturing a display panel according to claim 7, wherein: Before exposing, developing and stripping the conductive photoresist, the method further includes the following steps: removing the conductive photoresist remaining on the first electrode and the second electrode by a plasma ashing process.

9. The method for manufacturing a display panel according to claim 7, wherein: After forming the gate with a stable shape, the method further includes the following steps: forming a patterned metal layer, wherein the metal layer includes a scan line electrically connected to the gate.

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