Thin film transistor substrate

Abstract

The present invention relates to a thin film transistor substrate, comprising: an insulating substrate; a conductor layer, the conductor layer including a top gate electrode portion of an oxide semiconductor thin film transistor; an oxide semiconductor layer, the oxide semiconductor layer being located below the top gate electrode portion and including a channel region of the oxide semiconductor thin film transistor; and an upper insulating layer, the upper insulating layer being located between the conductor layer and the oxide semiconductor layer. The oxide semiconductor layer includes a low-resistance region, and the resistance of the low-resistance region is lower than that of the channel region. The low-resistance region sandwiches the channel region in the in-plane direction of the substrate and contains impurities that cause the resistance of the low-resistance region to decrease. The concentration distribution of the impurities that cause the resistance of the low-resistance region to decrease has one or more peaks in the stacking direction. The one or more peaks are located outside the oxide semiconductor layer.

Description

Technical Field

[0001] The present invention relates to a thin film transistor substrate. Background Art

[0002] A technique of combining a low-temperature polysilicon thin-film transistor (LTPS TFT) and an oxide semiconductor TFT into one circuit has been put into practical use. For example, a pixel circuit including a low-temperature polysilicon TFT and an oxide semiconductor TFT has been proposed. Combining a low-temperature polysilicon TFT having a high mobility and an oxide semiconductor TFT generating a small leakage current in one circuit can improve the characteristics of the circuit and reduce the power consumption of the circuit.

[0003] The semiconductor layer of the oxide semiconductor TFT includes a channel region and source / drain regions sandwiching the channel region. The source / drain regions are low-resistance regions whose resistance is lower than that of the channel region. The above low-resistance region can be formed by exposing the oxide semiconductor layer to plasma of a specific element, or by doping the oxide semiconductor layer with impurity ions by ion implantation. Summary of the Invention

[0004] When reducing the resistance of the oxide semiconductor layer, it is important to maintain the designed channel length. Therefore, when ion implantation is used to reduce the resistance of the oxide semiconductor layer, it is important to precisely control the concentration distribution of the implanted ions. If the concentration of impurities remaining in the oxide semiconductor layer is too high, the channel length will become short, resulting in a failure of the TFT having a short channel.

[0005] A thin film transistor substrate according to an aspect of the present invention includes: an insulating substrate; a conductor layer including a top gate electrode portion of an oxide semiconductor thin film transistor; an oxide semiconductor layer located below the top gate electrode portion and including a channel region of the oxide semiconductor thin film transistor; and an upper insulating layer located between the conductor layer and the oxide semiconductor layer. The oxide semiconductor layer includes a low-resistance region whose resistance is lower than that of the channel region. The low-resistance region sandwiches the channel region in the in-plane direction of the substrate and contains impurities that cause the resistance of the low-resistance region to decrease. The concentration distribution of the impurities that cause the resistance of the low-resistance region to decrease has one or more peaks in the stacking direction. The one or more peaks are located outside the oxide semiconductor layer.

[0006] An aspect of the present invention improves the characteristics of an oxide semiconductor thin film transistor.

[0007] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory, and do not limit the present invention. Description of the Drawings

[0008] Figure 1 Schematically shows an example of the structure of an OLED display device;

[0009] Figure 2 Shows an example of the structure of a pixel circuit;

[0010] Figure 3 Schematically shows a cross-sectional structure of a part of a TFT substrate;

[0011] Figure 4 Shows an example of a CMOS circuit;

[0012] Figure 5 Schematically shows an example of a cross-sectional structure of a CMOS circuit;

[0013] Figure 6A Shows an example of a method for manufacturing an oxide semiconductor TFT;

[0014] Figure 6B Shows an example of a method for manufacturing an oxide semiconductor TFT;

[0015] Figure 6C Shows an example of a method for manufacturing an oxide semiconductor TFT;

[0016] Figure 6D Shows an example of a method for manufacturing an oxide semiconductor TFT;

[0017] Figure 7A Shows another example of a method for manufacturing an oxide semiconductor TFT;

[0018] Figure 7B Shows yet another example of a method for manufacturing an oxide semiconductor TFT;

[0019] Figure 7C Shows still another example of a method for manufacturing an oxide semiconductor TFT;

[0020] Figure 7D Shows another example of a method for manufacturing an oxide semiconductor TFT;

[0021] Figure 8 Shows the implantation of impurity ions into an oxide semiconductor TFT in an example of the related art;

[0022] Figure 9A Shows an example of the concentration distribution of impurities in an oxide semiconductor TFT and its vicinity in an embodiment of this specification;

[0023] Figure 9B An example of the measured concentration distribution of boron in an IGZO TFT and its vicinity in one embodiment of this specification is provided;

[0024] Figure 9C Measurement results of an oxide semiconductor TFT in one embodiment of this specification are provided;

[0025] Figure 10A An example of the concentration distribution of impurities in an oxide semiconductor TFT and its vicinity in another embodiment of this specification is shown;

[0026] Figure 10B An example of the concentration distribution of impurities in an oxide semiconductor TFT and its vicinity in yet another embodiment of this specification is shown;

[0027] Figure 11 The relationship between the dC / dV signal obtained by SCM analysis of an n-type semiconductor and the carrier density is schematically shown;

[0028] Figure 12 The change in the dC / dV signal value in an oxide semiconductor layer in one embodiment of this specification is shown; and

[0029] Figure 13 The change in the dC / dV signal value in an oxide semiconductor layer in another embodiment of this specification is shown. Detailed Embodiments

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are only examples for implementing the present invention and do not limit the technical scope of the present invention. The dimensions or shapes of some elements in the drawings are enlarged for clear understanding of the description.

[0031] Overview

[0032] The following description uses an Organic Light-Emitting Diode (OLED) display device as an example of a device including a thin film transistor substrate. The OLED display device in the present invention includes low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) and oxide semiconductor TFTs in pixel circuits and / or peripheral circuits. An example of the oxide semiconductor is indium gallium zinc oxide (IGZO). This thin film transistor substrate can be used not only in OLED display devices but also in flat panel displays (such as liquid crystal display devices) or electronic devices (such as storage devices or high-voltage devices).

[0033] The oxide semiconductor TFT generates a small leakage current, and thus, it can be used as a switching transistor connected to a storage capacitor (capacitive element), for example, to maintain the gate potential of a driving transistor in a pixel circuit. For example, a low-temperature polycrystalline silicon TFT having a high mobility can be used as the driving transistor. The structure disclosed herein is also applicable to devices other than display devices.

[0034] In an embodiment of the present specification, the resistance of the oxide semiconductor layer is reduced by doping impurity ions. The region where the resistance is reduced includes the source region / drain region of the oxide semiconductor TFT. When reducing the resistance of the oxide semiconductor layer, it is important to maintain the designed channel length. Therefore, when ion implantation is used to reduce the resistance of the oxide semiconductor layer, it is important to precisely control the concentration distribution of the implanted ions. If the concentration of the impurities retained in the oxide semiconductor layer is too high, the channel length will become short, resulting in a failure of the TFT having a short channel.

[0035] In an embodiment of the present specification, the concentration distribution of the impurities in the stacking direction has one or more peaks, and the one or more peaks are located outside the oxide semiconductor layer. Shifting the peak of the impurity concentration distribution from the oxide semiconductor layer helps to generate an ideal low-resistance oxide semiconductor region.

[0036] The oxide semiconductor layer in an embodiment of the present specification includes a transition region extending outward from the end of the top gate electrode portion. In this transition region, the carrier density increases as it moves away from the top gate electrode portion. This structure provides characteristics more suitable for the oxide semiconductor TFT. The dC / dV value obtained from the SCM analysis of this transition region has a negative minimum value. Specifically, the dC / dV value at the end of the top gate electrode portion is negative. As the distance from the top gate electrode portion increases, the dC / dV value decreases to the minimum value and then increases. The dC / dV value reaches a zero value outside this transition region. This structure provides characteristics more suitable for the oxide semiconductor TFT.

[0037] Structure of a display device

[0038] Figure 1The structure example of the OLED display device 1 is schematically shown. The OLED display device 1 includes a thin-film transistor (TFT) substrate 10 and a thin-film encapsulation (TFE) portion 20. An organic light-emitting element (OLED element) and a pixel circuit are fabricated on the substrate 10, and the thin-film encapsulation (TFE) portion 20 is used to encapsulate the organic light-emitting element. The thin-film encapsulation portion 20 is a kind of structure encapsulation unit. Another example of the structure encapsulation unit is an encapsulation substrate for encapsulating the organic light-emitting element and an adhesive (glass frit seal) for bonding the TFT substrate 10 to the encapsulation substrate. The space between the TFT substrate 10 and the encapsulation substrate is filled with dry nitrogen, for example.

[0039] Around the periphery of the cathode electrode region 14 outside the display region 25 of the TFT substrate 10, a scan driver 31, a light-emitting driver 32, a protection circuit 33, a driver IC (Integrated Circuit) 34, and a demultiplexer 36 are provided. The driver IC 34 is connected to an external device through a flexible printed circuit (FPC) 35. The scan driver 31, the light-emitting driver 32, and the protection circuit 33 are peripheral circuits fabricated on the TFT substrate 10.

[0040] The scan driver 31 drives the scan lines on the TFT substrate 10. The light-emitting driver 32 drives the light-emitting control lines to control the light-emitting time period of the pixels. For example, the driver IC 34 is mounted with an anisotropic conductive film (ACF).

[0041] The protection circuit 33 protects the elements in the pixel circuit from electrostatic discharge. The driver IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the light-emitting driver 32, and also supplies power and data signals to the demultiplexer 36.

[0042] The demultiplexer 36 continuously outputs the output of one pin of the driver IC 34 to d data lines (d is an integer greater than 1). The demultiplexer 36 changes the data lines to output the data signal from the driver IC 34 d times within each scan time period to drive d times as many data lines as the output pins of the driver IC 34.

[0043] Structure of the pixel circuit

[0044] A plurality of pixel circuits are fabricated on the TFT substrate 10 to control the current to be supplied to the anode electrode portion of the sub-pixels (also referred to as pixels). Figure 2Shows a structural example of a pixel circuit. Each pixel circuit includes a driving transistor T1, a selection transistor T2, a light-emitting transistor T3, and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. The transistors are TFTs. The transistors other than the driving transistor T1 are switching transistors.

[0045] The selection transistor T2 is a switch for selecting a sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, whose gate terminal is connected to the scan line 16, whose source terminal is connected to the data line 15, and whose drain terminal is connected to the gate terminal of the driving transistor T1.

[0046] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel low-temperature polycrystalline silicon TFT, whose gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the drain terminal of the light-emitting transistor T3, and the drain terminal of the driving transistor T1 is connected to the OLED element E1. The storage capacitor C1 is provided between the gate terminal of the driving transistor T1 and the power supply line 18.

[0047] The light-emitting transistor T3 is a switch for controlling the supply / stop of the driving current to the OLED element E1. The light-emitting transistor T3 is a p-channel low-temperature polycrystalline silicon TFT, whose gate terminal is connected to the light-emission control line 17. The source terminal of the light-emitting transistor T3 is connected to the power supply line 18, and the drain terminal of the light-emitting transistor T3 is connected to the source terminal of the driving transistor T1.

[0048] Next, the operation of the pixel circuit is described. The scan driver 31 outputs a selection pulse to the scan line 16 to turn on the selection transistor T2. The data voltage provided from the driver IC 34 via the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage during the period of one frame. The conductance of the driving transistor T1 is changed in an analog manner according to this stored voltage, so that the driving transistor T1 supplies a forward bias current corresponding to the light-emission level to the OLED element E1.

[0049] The light-emitting transistor T3 is located on the supply path of the driving current. The light-emission driver 32 outputs a control signal to the light-emission control line 17 to control the on / off of the light-emitting transistor T3. When the light-emitting transistor T3 is turned on, the driving current is supplied to the OLED element E1. When the light-emitting transistor T3 is turned off, the supply of the driving current is stopped. The light-emission period (duty ratio) in one frame period can be controlled by controlling the on / off of the transistor T3. Figure 2 The circuit structure in is just an example; the pixel circuit can have a different structure.

[0050] Structure of the TFT substrate

[0051] In the following, a structural example of a TFT substrate including a low-temperature polysilicon TFT and an oxide semiconductor TFT is described. The oxide semiconductor may be IGZO. The structure described in this specification is applicable to a TFT substrate including TFTs of other types of oxide semiconductors.

[0052] Figure 3 The cross-sectional structure of a part of the TFT substrate is schematically shown. A low-temperature polysilicon TFT 141, an oxide semiconductor TFT 142, a storage capacitor 143, and an OLED element 144 are fabricated on an insulating substrate 101. These elements correspond to Figure 2 the driving transistor T1, the selection transistor T2, the storage capacitor C1, and the OLED element E1 in

[0053] The insulating substrate 101 is a flexible or non-flexible substrate made of resin or glass. The low-temperature polysilicon TFT 141 includes a low-temperature polysilicon portion 102. The low-temperature polysilicon portion 102 is included in the low-temperature polysilicon layer and may be an island-shaped low-temperature polysilicon film or may be a part of a larger low-temperature polysilicon film. The low-temperature polysilicon portion 102 includes source / drain regions 104 and 105 and a channel region 103 interposed therebetween in the in-plane direction.

[0054] The source / drain regions 104 and 105 are made of low-temperature polysilicon with reduced resistance by doping high-concentration impurities. The source / drain regions 104 and 105 are connected to a source electrode portion 109 and a drain electrode portion 110. The channel region 103 is made of low-temperature polysilicon with unchanged resistance (high-resistance low-temperature polysilicon).

[0055] The low-temperature polysilicon portion 102 is included in the low-temperature polysilicon layer. The low-temperature polysilicon layer includes the low-temperature polysilicon portions of the low-temperature polysilicon TFTs in a plurality of pixel circuits. The low-temperature polysilicon layer is directly formed on the insulating substrate 101. Although Figure 3 the low-temperature polysilicon portion 102 in the example of

[0056] The low-temperature polysilicon TFT 141 has a top-gate structure. The low-temperature polysilicon TFT 141 may also have a bottom gate in addition to the top gate. The low-temperature polysilicon TFT 141 further includes a gate electrode portion 107 and a gate insulating portion, and the gate insulating portion is located between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulating portion is the part of the insulating layer 106 located between the gate electrode portion 107 and the channel region 103. The insulating layer 106 includes the gate insulating portions of other low-temperature polysilicon TFTs. The channel region 103, the gate insulating portion, and the gate electrode portion 107 are arranged in sequence from the bottom (the side closer to the insulating substrate 101); the gate insulating portion is in contact with the channel region 103 and the gate electrode portion 107.

[0057] The gate electrode portion 107 is made of a conductor and is included in the conductor layer. The gate electrode portion 107 may be made of a metal. For example, the metal material can be preferably selected from Mo, W, Nb, and Al. The insulating layer 106 in this example is made of silicon oxide.

[0058] An interlayer insulating film 108 is provided to cover the low-temperature polysilicon portion 102, the gate insulating portion, and the gate electrode portion 107. The interlayer insulating film 108 may be a silicon nitride film. The source / drain electrode portions 109 and 110 are provided above the interlayer insulating film 108 and are connected to the source / drain regions 104 and 105 through contact holes formed through the interlayer insulating film 108 and the insulating layer 106. The materials of the source / drain electrode portions 109 and 110 may be, for example, Al or Ti.

[0059] The storage capacitor 143 includes a lower electrode portion 111, an upper electrode portion 120 opposite to the lower electrode portion 111, and an insulating portion sandwiched between the lower electrode portion 111 and the upper electrode portion 120. The lower electrode portion 111 is located above the interlayer insulating film 108 and extends from the source / drain electrode portion 110. The lower electrode portion 111 is included in the same conductor layer as the source / drain electrode portions 109 and 110.

[0060] Another interlayer insulating film 112 is arranged above the interlayer insulating film 108. The interlayer insulating film 112 may be a silicon oxide film. The interlayer insulating film 112 is provided to cover the lower electrode portion 111, the source / drain electrode portions 109 and 110, and the interlayer insulating film 108. The part of the interlayer insulating film 112 located between the lower electrode portion 111 and the upper electrode portion 120 corresponds to the insulating portion.

[0061] The oxide semiconductor TFT 142 includes an oxide semiconductor portion 113. The oxide semiconductor portion 113 may be an oxide semiconductor film or a part of the oxide semiconductor film, and includes source / drain regions 115 and 116, and a channel region 114 sandwiched between the source / drain regions 115 and 116 in the in-plane direction.

[0062] The source / drain regions 115 and 116 are made of IGZO with reduced resistance. The source / drain regions 115 and 116 are connected to the source / drain electrode portions 122 and 123. The channel region 114 is made of IGZO without reduced resistance (high-resistance IGZO).

[0063] The oxide semiconductor portion 113 is included in the oxide semiconductor layer. The oxide semiconductor layer includes the oxide semiconductor portions of a plurality of oxide semiconductor TFTs. The oxide semiconductor layer is provided above the interlayer insulating film 112.

[0064] The oxide semiconductor TFT 142 has a top-gate structure. In addition to having a top-gate, the oxide semiconductor TFT 142 may also have a bottom-gate. The oxide semiconductor TFT 142 further includes a gate electrode portion 119 and a gate insulating portion that is located between the gate electrode portion 119 and the channel region 114 in the stacking direction. The gate insulating portion is a portion of the insulating layer 117 that is located between the gate electrode portion 119 and the channel region 114.

[0065] The channel region 114, the gate insulating portion, and the gate electrode portion 119 are arranged in order from the bottom (the side closer to the insulating substrate 101). The gate insulating portion is in contact with the channel region 114 and the gate electrode portion 119. The gate electrode portion 119 is made of a conductor and is included in the conductor layer. The gate electrode portion 119 may be made of a metal. For example, the metal material may be preferably selected from Mo, W, Nb, and Al. For example, the insulating layer 117 may be made of silicon oxide.

[0066] Although Figure 3 one low-temperature polysilicon TFT and one oxide semiconductor TFT are shown, the other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit have the same structure.

[0067] The interlayer insulating film 121 is provided to cover the oxide semiconductor portion 113, the gate insulating portion, and the gate electrode portion 119 of the oxide semiconductor TFT 142 and the upper electrode portion 120 of the storage capacitor 143. The interlayer insulating film 121 covers a part of the interlayer insulating film 112. The interlayer insulating film 121 may be a silicon oxide film.

[0068] The source / drain electrode portions 122 and 123 of the oxide semiconductor TFT 142 are provided above the interlayer insulating film 121. The source / drain electrode portions 122 and 123 are connected to the source / drain regions 115 and 116 of the oxide semiconductor TFT 142 via contact holes formed through the interlayer insulating film 121 and the insulating layer 117.

[0069] The connecting portion 129 extending from the source / drain electrode portion 123 is connected to the upper electrode portion 120 of the storage capacitor 143 via a contact hole formed through the interlayer insulating film 121 and the insulating layer 117, and is also connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 via a contact hole formed through the interlayer insulating film 121, the interlayer insulating film 112, the interlayer insulating film 108, and the insulating layer 117.

[0070] The connecting portion 129 interconnects the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107. The source / drain electrode portions 122 and 123 and the connecting portion 129 are included in the conductor layer. The material of the conductor layer is ideally selected. For example, Al or Ti can be used.

[0071] An insulating planarization film 124 is laid to cover the exposed portions of the aforementioned conductor layer and the interlayer insulating film 121. The planarization film 124 can be made of an organic material. The anode electrode portion 125 is provided above the planarization film 124. The anode electrode portion 125 is connected to the source / drain electrode portion 109 of the low-temperature polysilicon TFT 141 via a contact hole formed through the planarization film 124, the interlayer insulating film 121, the interlayer insulating film 112, and the insulating layer 117.

[0072] For example, the anode electrode portion 125 can include the following three layers: a transparent film of ITO or IZO; a reflective film of a metal (such as Ag, Mg, Al, or Pt) or an alloy containing such a metal; and another transparent film as described above. This three-layer structure of the anode electrode portion 125 is merely an example. The anode electrode portion 125 can have a two-layer structure.

[0073] An insulating pixel defining layer 126 is provided above the anode electrode portion 125 to isolate the OLED element 144. The pixel defining layer 126 can be made of an organic material. The organic light-emitting film 127 is provided above the anode electrode portion 125. For example, the organic light-emitting film 127 is composed of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer sequentially arranged from the bottom. The stacking structure of the organic light-emitting film 127 is determined according to the design.

[0074] In addition, a cathode electrode portion 128 is provided above the organic light-emitting film 127. The cathode electrode portion 128 of one OLED element 144 is a part of an unseparated conductor film. The cathode electrode portion 128 transmits a part of the visible light from the organic light-emitting film 127. The stacked structure of the anode electrode portion 125, the organic light-emitting film 127, and the cathode electrode portion 128 provided in the opening of the pixel defining layer 126 corresponds to the OLED element 144.

[0075] Next, the structure of a complementary metal-oxide semiconductor (CMOS) circuit included in the driving circuit 31 or the driving circuit 32 on the TFT substrate will be described. Figure 4 An example of the CMOS circuit is shown. The CMOS circuit includes a p-channel low-temperature polycrystalline silicon TFT 201 and an n-channel oxide semiconductor TFT 202. The source / drain of the low-temperature polycrystalline silicon TFT 201 is connected to the source / drain of the n-channel oxide semiconductor TFT 202. The gates of the low-temperature polycrystalline silicon TFT 201 and the oxide semiconductor TFT 202 are connected and are supplied with the same signal.

[0076] Figure 5 Schematically shows Figure 4 An example of the cross-sectional structure of the shown CMOS circuit. The main description will focus on the differences from Figure 3 the example of the cross-sectional structure shown. In Figure 5 the structural example, the storage capacitor 143 in Figure 3 the structural example is removed. In addition, the source / drain electrode portion 210 of the low-temperature polycrystalline silicon TFT 201 is connected to the source / drain electrode portion 223 of the oxide semiconductor TFT 202, and the gate electrode portion 207 and the gate electrode portion 219 are connected.

[0077] Figure 5 The low-temperature polycrystalline silicon TFT 201 in Figure 3 can have the same structure as the low-temperature polycrystalline silicon TFT 141 in

[0078] The low-temperature polycrystalline silicon portion 208 includes a channel region 203 and source / drain regions 204 and 205. The source / drain electrode portions 209 and 210 are connected to the source / drain regions 204 and 205 via contact holes formed through the interlayer insulating film 108 and the insulating layer 106.

[0079] The low-temperature polycrystalline silicon portion 208, the gate insulating portion, the gate electrode portion 207, and the source / drain electrode portions 209 and 210 respectively correspond to Figure 3 the low-temperature polycrystalline silicon portion 102, the gate insulating portion, the gate electrode portion 107, and the source / drain electrode portions 109 and 110 in

[0080] Figure 5The oxide semiconductor TFT 202 therein may have the same structure as Figure 3 the oxide semiconductor TFT 142 therein. Their sizes may be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213, a gate insulating portion, and a gate electrode portion 219. The gate insulating portion is the portion of the insulating layer 117 between the gate electrode portion 219 and the oxide semiconductor portion 213.

[0081] The oxide semiconductor portion 213 includes a channel region 214 and source / drain regions 215 and 216. The oxide semiconductor portion 213, the gate insulating portion, and the gate electrode portion 219 respectively correspond to Figure 3 the oxide semiconductor portion 113, the gate insulating portion, and the gate electrode portion 119 therein. Each element is included in the same layer as the corresponding element.

[0082] The connecting portion 229 extends from the source / drain electrode portion 223 of the oxide semiconductor TFT 202 and is connected to the source / drain electrode portion 210 of the low-temperature polycrystalline silicon TFT 201 via a contact hole formed through the interlayer insulating film 112, the interlayer insulating film 121, and the insulating layer 117. The connecting portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 via a contact hole formed through the interlayer insulating film 121 and the planarization film 124. The connecting portion 230 is also connected to the gate electrode portion 207 of the low-temperature polycrystalline silicon TFT 201 via a contact hole formed through the interlayer insulating film 108, the interlayer insulating film 112, the interlayer insulating film 121, the planarization film 124, and the insulating layer 117.

[0083] Hereinafter, an example of a method for manufacturing an oxide semiconductor TFT is described. Figures 6A to 6D A method is shown in which impurities are implanted into the oxide semiconductor through the insulating layer. Figures 7A to 7D Another method is shown in which the insulating layer is partially removed by etching to form the gate insulating portion and impurities are implanted into the oxide semiconductor.

[0084] Referring to Figure 6A , in this manufacturing method, the interlayer insulating film 112 is formed by chemical vapor deposition (CVD), and then the oxide semiconductor portion 113 is formed. The oxide semiconductor portion 113 can be formed by forming an oxide semiconductor layer by sputtering and patterning the oxide semiconductor layer by photolithography. Next, the insulating layer 117 is formed by CVD, and then the gate electrode portion 119 is formed by forming a metal film by sputtering and etching the metal film using a mask patterned by photolithography.

[0085] Referring to Figure 6B, The manufacturing method injects impurities (e.g., boron) into the oxide semiconductor portion 113 through the insulating layer 117. The injection of impurity ions generates source / drain regions 115 and 116 with reduced resistance in the oxide semiconductor portion 113. The region between the source / drain regions 115 and 116 is the channel region 114.

[0086] The acceleration voltage of the impurity ions can be from 20 keV to 80 keV. As described below, in the embodiments of this specification, the concentration distribution of the impurities has a peak at positions outside the oxide semiconductor portion 113.

[0087] Reference Figure 6C , The manufacturing method generates an interlayer insulating film 121 to cover the gate electrode portion 119 and the insulating layer 117. The interlayer insulating film 121 can be generated by CVD. Reference Figure 6D , The manufacturing method forms contact holes in the interlayer insulating film 121 and the insulating layer 117 by etching using a mask patterned by photolithography. In addition, the manufacturing method deposits a metal film by sputtering and forms source / drain electrode portions 122 and 123 by etching the metal film using a mask patterned by photolithography.

[0088] Next, reference Figure 7A , The manufacturing method generates an interlayer insulating film 162 by CVD, and then generates an oxide semiconductor portion 163. The oxide semiconductor portion 163 can be formed by forming an oxide semiconductor layer by sputtering and patterning the oxide semiconductor layer by photolithography. Next, the manufacturing method generates an insulating layer 176 by CVD, and then generates a gate electrode portion 169 by forming a metal film by sputtering and etching the metal film using a mask patterned by photolithography.

[0089] Reference Figure 7B , The manufacturing method generates a gate insulating portion 177 by etching the insulating layer 176 using the gate electrode portion 169 as a mask. Through this process, the portion of the insulating layer 176 not covered by the gate electrode portion 169 is removed, and the oxide semiconductor portion 163 under the insulating layer 176 is exposed.

[0090] Subsequently, the manufacturing method injects impurities (e.g., boron) into the oxide semiconductor portion 163. The injection of impurity ions generates low-resistance regions 165 and 166 in the oxide semiconductor portion 163. These low-resistance regions correspond to the source / drain regions of the oxide semiconductor TFT 192. The region between the source / drain regions 165 and 166 corresponds to the channel region 164.

[0091] The acceleration voltage of the impurity ions can be from 10 keV to 30 keV. As described below, the concentration distribution of the impurities in the embodiments of the present specification has a peak at a position outside the oxide semiconductor portion 163.

[0092] Reference Figure 7C , the manufacturing method forms an interlayer insulating film 181 to cover the gate electrode portion 169 and the insulating layer 178. The interlayer insulating film 181 can be formed by CVD. Reference Figure 7D , the manufacturing method forms contact holes in the interlayer insulating film 181 and the insulating layer 178 by etching using a mask patterned by photolithography. In addition, the manufacturing method sputter-deposits a metal film, and forms source / drain electrode portions 182 and 183 by etching the metal film using a mask patterned by photolithography.

[0093] Distribution of impurity concentration

[0094] Hereinafter, the distribution of the impurity concentration in the oxide semiconductor TFT is described. The oxide semiconductor TFT in the embodiments of the present specification has a low-resistance region generated by impurity ion implantation in the oxide semiconductor portion. Examples of the selected impurity elements that cause a reduction in resistance include B, He, Ne, Ar, H, and P.

[0095] Figure 8 Shows a case of an impurity ion-implanted oxide semiconductor TFT in an example of the related art. An interlayer insulating film 311 and a lower insulating layer 312 are stacked on a substrate (not shown). The oxide semiconductor TFT includes an oxide semiconductor portion 302 located above the lower insulating layer 312. The oxide semiconductor TFT has a top-gate structure and includes a gate electrode portion 301 located above the oxide semiconductor portion 302. An upper insulating layer 313 is provided between the oxide semiconductor portion 302 and the gate electrode portion 301. The portion of the upper insulating layer 313 located between the gate electrode portion 301 and the oxide semiconductor portion 302 corresponds to the gate insulating portion.

[0096] In Figure 8 the state shown, impurity ion implantation is performed so as to generate low-resistance regions 304 and 305 in the oxide semiconductor portion 302. The region sandwiched between the low-resistance region 304 and the low-resistance region 305 in the in-plane direction is a channel region 303 having a high resistance.

[0097] Figure 8 Schematically shows the concentration distribution of the implanted impurity ions in the stacking direction. Figure 8 The impurity concentration distribution in the example of

[0098] The resistances of the n-type low-resistance regions 304 and 305 depend on the concentration of oxygen defects generated in the oxide semiconductor portion 302 due to damage caused by impurity ion implantation. In a structure in which the impurity concentration has a peak 321 in the oxide semiconductor portion 302 as shown in Figure 8 , the value ΔL is too large, resulting in a short channel in the oxide semiconductor TFT. When viewed from the plane, the value ΔL is the length of the overlapping region between the low-resistance region and the gate electrode portion 301 (the distance from the end of the gate electrode portion 301 to the end of the low-resistance region located below the gate electrode portion 301). When the value ΔL is 0, the channel length L is equal to the length of the gate electrode portion 301.

[0099] For a low-temperature polycrystalline silicon TFT, the resistance of the p-type low-resistance low-temperature polycrystalline silicon portion depends on the concentration of impurities held in the low-temperature polycrystalline silicon portion. Therefore, the impurity concentration distribution is controlled to have a peak in the low-temperature polycrystalline silicon portion. Examples of the impurities can be boron (B) or phosphorus (P). However, as described above, implanting impurity ions into the oxide semiconductor damages the oxide semiconductor layer, thereby generating a low-resistance region. Therefore, the position showing the peak of the impurity concentration can be selected more flexibly compared to implanting impurity ions into low-temperature polycrystalline silicon.

[0100] One embodiment of this specification controls the impurity concentration distribution such that the peak of the impurity concentration is located outside the oxide semiconductor layer, for example, above, below, or both above and below the oxide semiconductor layer. Therefore, the value ΔL in the oxide semiconductor portion can be made small.

[0101] Figure 9A An example of the impurity concentration distribution in the oxide semiconductor TFT and its vicinity in one embodiment of this specification is shown. Figure 9A The circuit structure in Figure 3 is the same as the example of the circuit structure shown in Figure 9A . It does not include some elements in the structure example in Figure 3 . The following description applies to the CMOS circuit described with reference to Figure 5 .

[0102] Figure 9AThe impurity concentration distribution in it has only one peak 331. The peak concentration of the impurity can be between 1E18 atoms / cc (number of atoms per cubic centimeter) and 1E21 atoms / cc. The peak 331 of the impurity concentration is located within the interlayer insulating film 112 under the oxide semiconductor portion 113. The interlayer insulating film 112 is an example of the lower insulating layer. The position of the peak 331 of the impurity concentration can be adjusted by controlling the acceleration voltage of the impurity ions. The impurity concentration can be adjusted by controlling the amount of the impurity. In one example, the distance in the stacking direction between the position of the peak 331 of the impurity concentration and the center of the oxide semiconductor portion 113 is greater than the thickness of the oxide semiconductor portion 113.

[0103] Figure 9A The structural example in it includes not only the oxide semiconductor TFT 142 but also the low-temperature polycrystalline silicon TFT 141 located below the oxide semiconductor TFT 142. For the low-temperature polycrystalline silicon TFT 141, the concentration distribution of the impurity is controlled such that the peak of the impurity concentration is located within the low-temperature polycrystalline silicon portion. The concentration distribution of the impurity can be adjusted by controlling the acceleration voltage of the impurity ions.

[0104] By terminating the dangling bonds of the low-temperature polycrystalline silicon with hydrogen, the low-temperature polycrystalline silicon TFT 141 can have more suitable characteristics. Therefore, a certain insulating layer, such as the interlayer insulating film 108, can be made of silicon nitride containing hydrogen. At the same time, in the case of manufacturing the circuit on a flexible polyimide substrate, a silicon nitride layer is provided to prevent moisture diffusion.

[0105] Figure 9A The structural example shown has a peak of the impurity concentration in the interlayer insulating film 112 located below the oxide semiconductor portion 113. Using an insulator different from silicon nitride, such as silicon oxide, for the interlayer insulating film 112 reduces the diffusion of hydrogen from the silicon nitride layer located below the interlayer insulating film 112 to the oxide semiconductor portion. In particular, using boron (B) as the impurity achieves a higher effect of reducing hydrogen diffusion. The boron-rich interlayer insulating film 112 further exhibits a high tolerance to impact.

[0106] Figure 9B Examples of the measured concentration distribution of boron in the IGZO TFT and its vicinity in the embodiments of this specification are provided. Figure 9B It includes the concentration distribution 702 of boron and the distribution 701 of the intensity of the signal caused by indium. The peak of the intensity of the signal caused by indium corresponds to the position of the depth of the IGZO film. The point 703 in the concentration distribution 702 of boron is the peak of the signal caused by noise, rather than the concentration peak.

[0107] Therefore, Figure 9BExamples of measurement results of an embodiment in which the peak of the boron concentration is located below the IGZO film are provided. From these measurement results, it can be seen that when the peak of the boron concentration is located below the IGZO film, the diffusion of hydrogen from a film (e.g., a silicon nitride layer) located below the peak position to the IGZO film can be reduced to stabilize the characteristics of the short-channel TFT.

[0108] Figure 9C Measurement results of an oxide semiconductor TFT in an embodiment of this specification are provided. The horizontal axis represents the gate voltage, and the vertical axis represents the drain current. Figure 9C Measurement results on a short-channel TFT with a gate length L of 2 μm are shown. Figure 9C It is shown that the oxide semiconductor TFT in this embodiment can operate normally even as a short-channel TFT.

[0109] Figure 10A An example of the impurity concentration distribution in and around an oxide semiconductor TFT in another embodiment of this specification is shown. Figure 10A The circuit structure in Figure 3 is the same as the example of the circuit structure shown in Figure 10A does not include Figure 3 some elements in the example of the structure in Figure 5 The following description applies to the CMOS circuit described with reference to

[0110] Figure 10A The impurity concentration distribution in

[0111] Figure 10A has only one peak 332. The peak of the impurity concentration can be between 1E18 atoms / cc and 1E21 atoms / cc. The peak 332 of the impurity concentration is located in the insulating layer 117 above the oxide semiconductor portion 113. The insulating layer 117 is an example of an upper insulating layer. The position of the peak 332 of the impurity concentration can be adjusted by controlling the acceleration voltage of the impurity ions. The concentration of the impurity can be adjusted by controlling the amount of the impurity. In one example, the distance in the stacking direction between the position of the peak 332 of the impurity concentration and the center of the oxide semiconductor portion 113 is greater than the thickness of the oxide semiconductor portion 113.

[0112] Reference Figure 9A and Figure 10AThe described structural example has only one peak in the impurity concentration. The impurity concentration in another structural example may have multiple peaks (maxima). All the peaks are located outside the oxide semiconductor portion.

[0113] Figure 10B An example of the impurity concentration distribution having two peaks is shown. There are two peaks in the impurity concentration distribution 333; one is located within the interlayer insulating film 112 and the other is located within the insulating layer 117. This structure reduces the adverse effects of the layers above and below the oxide semiconductor portion on the oxide semiconductor. By implanting impurity ions twice at different acceleration voltages, an impurity concentration distribution having two peaks can be obtained.

[0114] In Figure 3 、 Figure 5 、 Figure 9A 、 Figure 10A and Figure 10B In the examples shown, the gate insulating portion of each TFT is part of an insulating layer covering the entire display region. In another example, the gate insulating portion can be fabricated by forming a gate insulating layer and then etching the gate insulating layer. The insulating material for the gate insulating portion can be different from the insulating material for the upper insulating layer (e.g., interlayer insulating film) around the gate insulating portion. The low-resistance region is in direct contact with the upper insulating layer.

[0115] Carrier density distribution

[0116] Next, the carrier density distribution in the in-plane direction of the oxide semiconductor layer is described. The in-plane direction is the direction parallel to the main plane of the substrate and perpendicular to the stacking direction. First, the relationship between the carrier density and the dC / dV signal obtained by analyzing an n-type semiconductor using Scanning Capacitance Microscopy (SCM) is described. In the term dC / dV, C represents the capacitance of the local MOS generated between the conductive scanning probe and the oxide semiconductor, and V represents the voltage applied to the conductive scanning probe.

[0117] Figure 11 The relationship between the dC / dV signal obtained by SCM analysis of an n-type semiconductor and the carrier density is schematically shown. The horizontal axis represents the carrier density, and the vertical axis represents the dC / dV signal value. When the carrier density is between high density and low density, the dC / dV signal value is negative.

[0118] Each dC / dV signal value gradually decreases from low carrier density (N-) to high carrier density (N+), takes a minimum value at a specific carrier density, and then gradually increases. The carrier density at which the minimum value is taken depends on the material of the n-type semiconductor.

[0119] Figure 12 Shows the change in the dC / dV signal value in the oxide semiconductor layer in an embodiment of the present specification. IGZO is used as an example of the oxide semiconductor. Figure 12 Shows the change in the dC / dV signal value near the end of the top gate electrode portion of an oxide semiconductor TFT having a top gate structure.

[0120] The oxide semiconductor TFT includes an IGZO layer 402 disposed above the lower insulating layer 401, a gate insulating layer 403 disposed above the IGZO layer 402, and a top gate electrode portion 404 disposed above the gate insulating layer 403.

[0121] Figure 12 The graph in [ ] includes a top gate electrode signal 411 and a dC / dV signal value 413. As described above, the dC / dV signal value represents the carrier density. The horizontal axis represents the length along the channel, and the vertical axis represents the dC / dV signal value. The dC / dV signal value 413 includes a transition region 415 outside the top gate electrode portion 404 and a high carrier density region 416. The dC / dV signal value 413 gradually increases and approaches 0 from the end 405 of the top gate electrode portion 404 toward the center of the top gate electrode portion 404.

[0122] The high carrier density region 416 may be a region where the carrier density ranges from 1E19 / cc to 1E21 / cc. The transition region 415 is located between the high carrier density region 416 and the end 405 of the top gate electrode portion 404. The length of the transition region 415 may be between 0.2 μm and 2.5 μm.

[0123] The transition region is a region where the carrier density distribution in the IGZO changes from a low concentration to a high concentration in the direction from the end 405 of the top gate electrode portion 404 to the source / drain electrode portion. As Figure 12 shown, the dC / dV signal value takes the minimum value outside the top gate electrode portion 404, more specifically, within the transition region 415. The carrier density distribution having the transition region 415 starting from the end 405 of the top gate electrode portion 404 provides characteristics more suitable for the oxide semiconductor TFT.

[0124] Figure 13 Shows the change in the dC / dV signal value in the oxide semiconductor layer in another embodiment of the present specification. IGZO is used as an example of the oxide semiconductor. Figure 13 Shows the change in the dC / dV signal value near the end of the top gate electrode portion of an oxide semiconductor TFT having a top gate structure. The structure of this oxide semiconductor TFT is the same as that in the example of Figure 12 [ ].

[0125] Figure 13The curve graph in [it] includes a top gate electrode signal 451 and a dC / dV signal 453. The horizontal axis represents the length along the channel, and the vertical axis represents the dC / dV signal value. The dC / dV signal value 453 includes a transition region 455 outside the top gate electrode portion 404 and a high carrier density region 456. The dC / dV signal value 453 is substantially constant from the end 405 of the top gate electrode portion 404 toward the center of the top gate electrode portion 404.

[0126] The high carrier density region 456 may be a region where the carrier density is in the range from 1E19 / cc to 1E21 / cc. The transition region 455 is located between the high carrier density region 456 and the end 405 of the top gate electrode portion 404. The length of the transition region 455 may be between 0.2 μm and 2.5 μm.

[0127] The transition region is a region where the carrier density distribution of IGZO changes from a low concentration to a high concentration in the direction from the end 405 of the top gate electrode portion 404 toward the source / drain electrode portion. As Figure 13 shown, the dC / dV signal value takes the minimum value outside the top gate electrode portion 404, more specifically, within the transition region 455. The carrier density distribution having the transition region 455 starting from the end 405 of the top gate electrode portion 404 provides characteristics more suitable for the oxide semiconductor TFT. If a reference Figure 12 or Figure 13 the described carrier density distribution and a reference Figure 9A or Figure 10A the described impurity concentration distribution is established, either one is satisfactory.

[0128] As described above, embodiments of the present invention have been described; however, the present invention is not limited to the foregoing embodiments. Those skilled in the art can easily modify, add, or convert each element in the foregoing embodiments within the scope of the present invention. A part of the structure of one embodiment can be replaced with the structure of another embodiment, or the structure of one embodiment can be incorporated into the structure of another embodiment.

Claims

1. A thin film transistor substrate, comprising: An insulating substrate; And A conductor layer, the conductor layer including a top gate electrode portion of an oxide semiconductor thin film transistor; An oxide semiconductor layer, the oxide semiconductor layer being located below the top gate electrode portion and including a channel region of the oxide semiconductor thin film transistor; And An upper insulating layer, the upper insulating layer being located between the conductor layer and the oxide semiconductor layer, Wherein, the oxide semiconductor layer includes a low resistance region, and the resistance of the low resistance region is lower than the resistance of the channel region, Wherein, the low resistance region sandwiches the channel region in the in-plane direction of the insulating substrate and contains impurities that cause the resistance of the low resistance region to decrease, Wherein, the concentration distribution of the impurities that cause the resistance of the low resistance region to decrease has one or more peaks in the stacking direction, Wherein, the one or more peaks are located outside the oxide semiconductor layer, and Wherein, the distance between the position of the peak closest to the oxide semiconductor layer among the one or more peaks and the center of the oxide semiconductor layer in the stacking direction is greater than or equal to the thickness of the oxide semiconductor layer.

2. The thin film transistor substrate according to claim 1, wherein, One of the one or more peaks is located within the upper insulating layer.

3. The thin film transistor substrate according to claim 1, further comprising a lower insulating layer located below the oxide semiconductor layer, Among them, One of the one or more peaks is located within the lower insulating layer.

4. The thin film transistor substrate according to claim 3, wherein, The one or more peaks are a first peak and a second peak, One of the one or more peaks is the first peak, and The second peak is located within the upper insulating layer.

5. The thin-film transistor substrate according to claim 1, wherein, The impurity that causes the resistance to decrease is boron.

6. The thin film transistor substrate according to claim 3, further comprising: A polysilicon layer, the polysilicon layer being located below the lower insulating layer and including a channel region of a polysilicon thin film transistor; And A hydrogen-containing silicon nitride layer, the hydrogen-containing silicon nitride layer being located between the polysilicon layer and the lower insulating layer.

7. The thin film transistor substrate according to claim 1, Among them, Each of the low resistance regions includes a transition region located outside the end of the top gate electrode portion, and Wherein, the carrier density in the transition region increases as the distance between the transition region and the channel region increases.

8. The thin film transistor substrate according to claim 7, wherein, The dC / dV signal value obtained by scanning capacitance microscopy analysis of the transition region has a negative minimum value.

9. The thin film transistor substrate according to claim 7, further comprising: A lower insulating layer located below the oxide semiconductor layer, and A polysilicon layer, the polysilicon layer being located below the lower insulating layer and including a channel region of a polysilicon thin film transistor.

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