A splicing panel

Abstract

An embodiment of the present application discloses a splicing panel, which includes a first substrate and at least two second substrates. The first substrate includes a first base and a plurality of female conductive pads provided on the base; at least two second substrates are spliced and arranged on a first substrate, and there is a splicing seam between two adjacent second substrates; the second substrate includes a plurality of sub-conductive pads, the sub-conductive pads are located on at least one side of the second substrate and face the first substrate; the female conductive pads are arranged corresponding to the splicing seam, the female conductive pads include a first part and a second part, the first part is connected to one side of the second part, the first part is bound and connected to the sub-conductive pad of a second substrate, and the second part is bound and connected to the sub-conductive pad of another second substrate. In the present application, female conductive pads are provided on the first substrate, and a female conductive pad binds the sub-conductive pads in at least two second substrates at the same time to reduce the splicing seam.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a splicing panel. Background Art

[0002] In the process of researching and practicing the prior art, the inventors of this application found that existing splicing panels mostly directly splice display modules, and then connect multiple display modules in series through circuits to achieve the display function. However, the above series connection method results in a large seam between the display modules. Summary of the Invention

[0003] An embodiment of this application provides a splicing panel that can reduce the seam.

[0004] An embodiment of this application provides a splicing panel, which includes:

[0005] A first substrate, the first substrate includes a first base and a plurality of mother conductive pads disposed on the base; and

[0006] At least two second substrates, the at least two second substrates are spliced and disposed on the first substrate, and there is a seam between adjacent two of the second substrates; the second substrate includes a plurality of sub-conductive pads, the sub-conductive pads are located on at least one side of the second substrate and face the first substrate;

[0007] Wherein, the mother conductive pads are disposed corresponding to the seam, the mother conductive pads include a first part and a second part, the first part is connected to one side of the second part, the first part is bonded and connected to the sub-conductive pad of one of the second substrates, and the second part is bonded and connected to the sub-conductive pad of the other second substrate.

[0008] Optionally, in some embodiments of this application, the first substrate includes a plurality of setting areas, and one setting area corresponds to one second substrate; in one setting area, a plurality of the mother conductive pads are located on the periphery of the setting area; at least one of the mother conductive pads is shared by adjacent two setting areas, the first part is located in one setting area, and the second part is located in another setting area.

[0009] Optionally, in some embodiments of this application, the plurality of mother conductive pads include a plurality of first mother pads, a plurality of second mother pads, a plurality of third mother pads, and a plurality of fourth mother pads, the setting area includes a first side, a second side, a third side, and a fourth side that are connected end to end in sequence, the first side and the third side are oppositely disposed, and the second side and the fourth side are oppositely disposed;

[0010] A plurality of the first mother pads are correspondingly disposed on the first side, a plurality of the second mother pads are correspondingly disposed on the second side, a plurality of the third mother pads are correspondingly disposed on the third side, and a plurality of the fourth mother pads are correspondingly disposed on the fourth side.

[0011] Optionally, in some embodiments of the present application, the first substrate further includes a plurality of strip connection lines disposed on the same layer as the mother conductive pads. One of the first mother pads is correspondingly connected to one of the second mother pads through the connection line, and one of the third mother pads is correspondingly connected to one of the fourth mother pads through the connection line.

[0012] Optionally, in some embodiments of the present application, in a second substrate, a plurality of the sub-conductive pads include a first sub-pad and a second sub-pad, and the first sub-pad and the second sub-pad are disposed on opposite sides;

[0013] In a second substrate, the first sub-pad is bonded and connected to the first mother pad or the second mother pad, and the second sub-pad is bonded and connected to the third mother pad or the fourth mother pad;

[0014] The second substrate further includes a signal line, one end of the signal line is connected to the first sub-pad, and the other end of the signal line is connected to the second sub-pad.

[0015] Optionally, in some embodiments of the present application, in a second substrate, a plurality of the sub-conductive pads include a first sub-pad, a second sub-pad, a third sub-pad, and a fourth sub-pad; the first sub-pad and the third sub-pad are disposed on opposite sides, and the second sub-pad and the fourth sub-pad are disposed on opposite sides;

[0016] The second substrate further includes a plurality of connection lines disposed on the same layer as the sub-conductive pads. One of the first sub-pads is correspondingly connected to one of the second sub-pads through the connection line, and one of the third sub-pads is correspondingly connected to one of the fourth sub-pads through the connection line;

[0017] The first sub-pad is bonded and connected to the first mother pad, the second sub-pad is bonded and connected to the second mother pad, the third sub-pad is bonded and connected to the third mother pad, and the fourth sub-pad is bonded and connected to the fourth mother pad;

[0018] The second substrate further includes a signal line, one end of the signal line is connected to the first sub-pad, and the other end of the signal line is connected to the third sub-pad.

[0019] Optionally, in some embodiments of the present application, the signal line includes at least one of a scan line and a power signal line.

[0020] Optionally, in some embodiments of the present application, the second substrate further includes:

[0021] A thin film transistor structure layer is disposed on a side of the sub-conductive pad away from the first substrate. The thin film transistor structure layer includes a scanning line, and the scanning line is connected to the sub-conductive pad;

[0022] A light-emitting device is disposed on the thin film transistor structure layer.

[0023] Optionally, in some embodiments of the present application, the first substrate further includes a gate driving circuit, the gate driving circuit is located on at least one side of the first substrate, and the gate driving circuit is electrically connected to the mother conductive pad.

[0024] Optionally, in some embodiments of the present application, the splicing panel further includes a packaging adhesive, and the packaging adhesive is encapsulated between the first substrate and the second substrate.

[0025] Optionally, in some embodiments of the present application, the mother conductive pad and the sub-conductive pad are bound and connected by a conductive adhesive, or the mother conductive pad and the sub-conductive pad are bonded and connected.

[0026] An embodiment of the present application provides a splicing panel, which includes a first substrate and at least two second substrates. The first substrate includes a first base and a plurality of mother conductive pads disposed on the base; at least two second substrates are spliced and disposed on a first substrate, and there is a splicing seam between adjacent two second substrates; the second substrate includes a plurality of sub-conductive pads, and the sub-conductive pads are located on at least one side of the second substrate and face the first substrate;

[0027] Wherein, the mother conductive pad is disposed corresponding to the splicing seam. The mother conductive pad includes a first part and a second part. The first part is connected to one side of the second part. The first part is bound and connected to the sub-conductive pad of a second substrate, and the second part is bound and connected to the sub-conductive pad of another second substrate.

[0028] In the present application, a mother conductive pad is disposed on the first substrate, and a mother conductive pad binds the sub-conductive pads in at least two second substrates at the same time to reduce the splicing seam; in addition, since the gate driving circuit is electrically connected to the mother conductive pad and the sub-conductive pad is connected to the signal line, one or two gate driving circuits can be used to drive multiple second substrates, saving the gate driving circuit and the flip chip thin film, and further reducing the splicing seam. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0030] Figure 1 It is a schematic cross-sectional structure diagram of a splicing panel provided by the first embodiment of the present application;

[0031] Figure 2 It is a schematic structure diagram of the first substrate of the splicing panel provided by the first embodiment of the present application;

[0032] Figure 3 It is a schematic structure diagram of the second substrate of the splicing panel provided by the first embodiment of the present application;

[0033] Figure 4 It is a schematic top view structure diagram of the splicing panel provided by the first embodiment of the present application;

[0034] Figure 5 It is a schematic partial cross-sectional structure diagram of the splicing panel provided by the first embodiment of the present application;

[0035] Figure 6 It is a schematic cross-sectional structure diagram of a splicing panel provided by the second embodiment of the present application;

[0036] Figure 7 It is a schematic structure diagram of the first substrate of the splicing panel provided by the second embodiment of the present application;

[0037] Figure 8 It is a schematic structure diagram of the second substrate of the splicing panel provided by the second embodiment of the present application;

[0038] Figure 9 It is a schematic top view structure diagram of the splicing panel provided by the second embodiment of the present application;

[0039] Figure 10 It is a schematic partial cross-sectional structure diagram of the splicing panel provided by the second embodiment of the present application. Detailed implementation manners

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the drawings; and "inner" and "outer" refer to the outline of the device.

[0041] An embodiment of the present application provides a splicing panel, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0042] Please refer to Figure 1 , a first embodiment of the present application provides a splicing panel 100, which includes a first substrate 10 and at least two second substrates 20. At least two second substrates 20 are spliced and arranged on a first substrate 10. There is a splicing seam pf between two adjacent second substrates 20.

[0043] The first substrate 10 includes a first base 11 and a plurality of mother conductive pads md arranged on the base 11. The second substrate 20 includes a plurality of sub-conductive pads zd, and the sub-conductive pads zd are located on at least one side of the second substrate 20 and face the first substrate 10.

[0044] The mother conductive pads md are arranged corresponding to the splicing seam pf. The mother conductive pad md includes a first part md1 and a second part md2, and the first part md1 is connected to one side of the second part md2. The first part md1 is bound and connected to the sub-conductive pad zd of a second substrate 20. The second part md2 is bound and connected to the sub-conductive pad zd of another second substrate 20.

[0045] In the first embodiment of the present application, mother conductive pads md are arranged on the first substrate 10, and a mother conductive pad md is simultaneously bound to the sub-conductive pads zd in at least two second substrates 20 to reduce the splicing seam.

[0046] Optionally, the materials of the mother conductive pads md and the sub-conductive pads zd can each be metal oxides such as indium tin oxide and indium zinc oxide, and can also be metals, alloys, and compounds and their mixtures. For example, gold, silver, copper, tungsten, molybdenum, iron, aluminum, aluminum-silicon, aluminum-titanium, metal material nitrides, etc. can be used.

[0047] Optionally, please refer to Figure 2 , the first substrate 10 includes a plurality of setting areas 10a. One setting area 10a corresponds to one second substrate 20. In a setting area 10a, a plurality of mother conductive pads md are located on the periphery of the setting area 10a; at least one mother conductive pad md is shared by two adjacent setting areas 10a. The first part md1 is located in one setting area 10a, and the second part md2 is located in another setting area 10a.

[0048] Optionally, the shape of the setting area 10a can be one of regular polygons such as triangles, quadrilaterals, pentagons, and hexagons. The shapes of the setting areas 10a can be the same or different.

[0049] Among them, multiple mother conductive pads md are arranged on the sides of a polygon. Two adjacent setting areas 10a can share one side and the mother conductive pad md on that side; two adjacent setting areas 10a can also be arranged at intervals, and the mother conductive pad md is arranged at the adjacent side of the two setting areas 10a.

[0050] In this first embodiment, the setting area 10a is taken as a rectangle as an example for illustration, but it is not limited thereto.

[0051] The multiple mother conductive pads md include multiple first mother pads 121, multiple second mother pads 122, multiple third mother pads 123, and multiple fourth mother pads 124. The setting area 10a includes a first side a1, a second side a2, a third side a3, and a fourth side a4 that are connected end to end in sequence. The first side a1 and the third side a3 are arranged opposite to each other, and the second side a2 and the fourth side a4 are arranged opposite to each other.

[0052] The multiple first mother pads 121 are correspondingly arranged on the first side a1. The multiple second mother pads 122 are correspondingly arranged on the second side a2. The multiple third mother pads 123 are correspondingly arranged on the third side a3. The multiple fourth mother pads 124 are correspondingly arranged on the fourth side a4.

[0053] Optionally, the first side a1, the second side a2, the third side a3, and the fourth side a4 can be arranged in a clockwise direction or in a counterclockwise direction. In this first embodiment, the clockwise arrangement is taken as an example, but it is not limited thereto.

[0054] Optionally, the extending directions of the first mother pad 121 and the third mother pad 123 are the same; the extending directions of the second mother pad 122 and the fourth mother pad 124 are the same. The first mother pad 121 and the third mother pad 123 extend along the first direction x; the second mother pad 122 and the fourth mother pad 124 extend along the second direction y.

[0055] Optionally, the first direction x intersects with the second direction y. In this first embodiment, the first direction x is perpendicular to the second direction y for illustration.

[0056] The multiple setting areas 10a are arranged along the first direction x and the second direction y.

[0057] The multiple first mother pads 121 are arranged in columns along the second direction y; the multiple third mother pads 123 are arranged in columns along the second direction y; in the first direction x, a column of first mother pads 121 and a column of third mother pads 123 are arranged alternately.

[0058] The multiple second mother pads 122 are arranged in rows along the first direction x; the multiple fourth mother pads 124 are arranged in rows along the first direction x; in the second direction y, a row of second mother pads 122 and a row of fourth mother pads 124 are arranged alternately.

[0059] In this first embodiment, a plurality of first female pads 121, a plurality of second female pads 122, a plurality of third female pads 123, and a plurality of fourth female pads 124 are respectively arranged in the four-side regions of a setting area 10a, so that each side can be shared with another setting area 10a, achieving the purpose that one second substrate 20 can be spliced with 4 second substrates 20 at the same time.

[0060] Optionally, the first substrate 10 further includes a plurality of strip connecting lines lj arranged on the same layer as the female conductive pad md. A first female pad 121 is correspondingly connected to a second female pad 122 through the connecting line lj. A third female pad 123 is correspondingly connected to a fourth female pad 124 through the connecting line lj.

[0061] Please refer to Figure 3 , optionally, in a second substrate 20, a plurality of sub-conductive pads zd include a first sub-pad zd1 and a second sub-pad zd2, and the first sub-pad zd1 and the second sub-pad zd2 are arranged on opposite sides.

[0062] The second substrate 20 further includes a signal line xh. One end of the signal line xh is connected to the first sub-pad zd1, and the other end of the signal line xh is connected to the second sub-pad zd2.

[0063] Please refer to Figure 4 , in a second substrate 20, the first sub-pad zd1 is bound and connected to the first female pad 121 or the second female pad 122, and the second sub-pad zd2 is bound and connected to the third female pad 123 or the fourth female pad 124.

[0064] That is to say, the first sub-pad zd1 is bound and connected to the first female pad 121, and the second sub-pad zd2 is bound and connected to the third female pad 123; or, the first sub-pad zd1 is bound and connected to the second female pad 122, and the second sub-pad zd2 is bound and connected to the fourth female pad 124.

[0065] It should be noted that since the first female pad 121 and the second female pad 122 are electrically connected, the third female pad 123 and the fourth female pad 124 are electrically connected, and the first sub-pad zd1 and the first female pad 121 are electrically connected, and the second sub-pad zd2 and the third female pad 123 are electrically connected; and the signal line xh is connected between the first sub-pad zd1 and the second sub-pad zd2, so that all the female conductive pads md, the signal line xh, and all the sub-conductive pads zd transmit the same signal.

[0066] Furthermore, all the second substrates 20 can achieve the purpose of co-signal through the binding of the female conductive pads md and the sub-conductive pads zd.

[0067] Optionally, the signal line xh includes at least one of a scan line, a data line, and a power supply signal line. Optionally, the power supply signal line can be a vss signal line or a vdd signal line.

[0068] In this first embodiment, the signal line xh is taken as an example of the scanning line for illustration. Each scanning line xh is correspondingly connected to a first sub-pad zd1 and a second sub-pad zd2. Each first sub-pad zd1 is correspondingly bonded to a first mother pad 121, and each second sub-pad zd2 is correspondingly bonded to a third mother pad 123.

[0069] The first substrate 10 further includes a gate driving circuit 13, and the gate driving circuit 13 is disposed on the substrate 11. The gate driving circuit 13 is located on at least one side of the first substrate 10. The gate driving circuit 13 is electrically connected to the mother conductive pad md.

[0070] Since the gate driving circuit 13 is electrically connected to the mother conductive pad md, the gate driving circuit 13 can drive a plurality of second substrates 20, thereby saving a plurality of gate driving circuits 13 and a plurality of COF films, and further reducing the seam.

[0071] When the gate driving circuit 13 is located on one side of the first substrate 10, the splicing panel 100 is driven unidirectionally. When the gate driving circuit 13 is located on the opposite sides of the first substrate 10, the splicing panel 100 is driven bidirectionally.

[0072] Optionally, please refer to Figure 5 , the second substrate 20 further includes a thin film transistor structure layer 21 and a light emitting device 22. The thin film transistor structure layer 21 is disposed on the side of the sub-conductive pad zd away from the first substrate 10. The light emitting device 22 is disposed on the thin film transistor structure layer 21.

[0073] Optionally, the thin film transistor structure layer 21 includes thin film transistors, and the thin film transistors can be top-gate type, bottom-gate type or double-gate type thin film transistors.

[0074] The light emitting device 22 can be a micro light emitting diode (Micro-LED) device, a sub-millimeter light emitting diode (Mini-LED) device, an organic light emitting diode (OLED) device, a quantum dot light emitting diode (QLED) device or a nano light emitting diode device, etc.

[0075] Optionally, the thin film transistor structure layer 21 includes a first buffer layer 211, a second buffer layer 212, an active layer 213, a first insulating layer 214, a first metal layer 215, a second insulating layer 216, an interlayer dielectric layer 217, a second metal layer (not shown in the figure) and a planarization layer 218 that are sequentially stacked and covered on the sub-conductive pad zd.

[0076] Optionally, the first metal layer 215 includes a gate and a signal line xh. The signal line xh is a scanning line. The signal line xh is connected to the sub-conductive pad zd through a via. The second metal layer includes a data line, a source electrode and a drain electrode.

[0077] Optionally, the light-emitting device 22 includes an anode 221, a pixel definition layer 222, a light-emitting layer 223, and a cathode 224. The anode 221 is disposed on the flat layer 218. The pixel definition layer 222 covers the flat layer 218 and exposes the anode 221. The light-emitting layer 223 is disposed on the anode 221. The cathode 224 is disposed on the light-emitting layer 223.

[0078] Optionally, the mother conductive pad md and the son conductive pad zd are bonded and connected through a conductive adhesive 30.

[0079] In some embodiments, the mother conductive pad md and the son conductive pad zd are bonded and connected.

[0080] Optionally, the splicing panel 100 further includes a packaging adhesive 40. The packaging adhesive 40 is encapsulated between the first substrate 10 and the second substrate 20.

[0081] The setting of the packaging adhesive 40 prevents external water and oxygen from invading the mother conductive pad md and the son conductive pad zd, and has the effect of protecting the mother conductive pad md and the son conductive pad zd.

[0082] Please refer to Figure 6 , a second embodiment of the present application provides a splicing panel 100, which includes a first substrate 10 and at least two second substrates 20. The at least two second substrates 20 are spliced and disposed on a first substrate 10. There is a splicing seam pf between two adjacent second substrates 20.

[0083] The first substrate 10 includes a first base 11 and a plurality of mother conductive pads md disposed on the base 11. The second substrate 20 includes a plurality of son conductive pads zd, and the son conductive pads zd are located on at least one side of the second substrate 20 and face the first substrate 10.

[0084] The mother conductive pad md is disposed corresponding to the splicing seam pf. The mother conductive pad md includes a first portion md1 and a second portion md2, and the first portion md1 is connected to one side of the second portion md2. The first portion md1 is bonded and connected to the son conductive pad zd of a second substrate 20. The second portion md2 is bonded and connected to the son conductive pad zd of another second substrate 20.

[0085] In the second embodiment of the present application, the mother conductive pad md is disposed on the first substrate 10, and a mother conductive pad md is simultaneously bonded to the son conductive pads zd in at least two second substrates 20 to reduce the splicing seam. In addition, since the gate driving circuit 13 is electrically connected to the mother conductive pad md and the son conductive pad zd is connected to the signal line xh, one or two gate driving circuits 13 can be used to drive a plurality of second substrates 20, saving the gate driving circuit and the COF, and further reducing the splicing seam.

[0086] Optionally, the materials of the mother conductive pad md and the child conductive pad zd can each be metal oxides such as indium tin oxide and indium zinc oxide, and can also be metals, alloys, compounds, and their mixtures. For example, gold, silver, copper, tungsten, molybdenum, iron, aluminum, aluminum-silicon, aluminum-titanium, metal material nitrides, etc. can be used.

[0087] Optionally, the mother conductive pad md and the child conductive pad zd are bound and connected through a conductive adhesive 30.

[0088] In some embodiments, the mother conductive pad md and the child conductive pad zd are bonded and connected.

[0089] Optionally, please refer to Figure 7 , the first substrate 10 includes a plurality of setting areas 10a. One setting area 10a corresponds to one second substrate 20. In one setting area 10a, a plurality of mother conductive pads md are located on the peripheral side of the setting area 10a; at least one mother conductive pad md is shared by two adjacent setting areas 10a. The first part md1 is located in one setting area 10a, and the second part md2 is located in another setting area 10a.

[0090] Optionally, the shape of the setting area 10a can be one of the regular polygons such as a triangle, a quadrilateral, a pentagon, and a hexagon. The shapes of the setting areas 10a can be the same or different.

[0091] Among them, a plurality of mother conductive pads md are arranged on the sides of the polygon. Two adjacent setting areas 10a can share one side and the mother conductive pad md on that side; two adjacent setting areas 10a can also be arranged at intervals, and the mother conductive pad md is arranged at the adjacent sides of the two setting areas 10a.

[0092] In this second embodiment, the setting area 10a is taken as a rectangle as an example for illustration, but it is not limited thereto.

[0093] In the first substrate 10 of this second embodiment, a plurality of mother conductive pads md include a plurality of first mother pads 121, a plurality of second mother pads 122, a plurality of third mother pads 123, and a plurality of fourth mother pads 124. The setting area 10a includes a first side a1, a second side a2, a third side a3, and a fourth side a4 that are sequentially connected end to end. The first side a1 and the third side a3 are oppositely arranged, and the second side a2 and the fourth side a4 are oppositely arranged.

[0094] A plurality of first mother pads 121 are correspondingly arranged on the first side a1. A plurality of second mother pads 122 are correspondingly arranged on the second side a2. A plurality of third mother pads 123 are correspondingly arranged on the third side a3. A plurality of fourth mother pads 124 are correspondingly arranged on the fourth side a4.

[0095] Optionally, the first side a1, the second side a2, the third side a3, and the fourth side a4 can be arranged clockwise or counterclockwise. In this second embodiment, the clockwise arrangement is taken as an example, but it is not limited thereto.

[0096] Optionally, the first mother pad 121 and the third mother pad 123 extend in the same direction; the second mother pad 122 and the fourth mother pad 124 extend in the same direction. The first mother pad 121 and the third mother pad 123 extend along the first direction x; the second mother pad 122 and the fourth mother pad 124 extend along the second direction y.

[0097] Optionally, the first direction x intersects the second direction y. In this second embodiment, it is described that the first direction x is perpendicular to the second direction y.

[0098] It should be noted that, compared with the first embodiment, in this second embodiment, the connection line lj is arranged on the second substrate 20.

[0099] Please refer to Figure 8 , in a second substrate 20, a plurality of sub-conductive pads zd include a first sub-pad zd1, a second sub-pad zd2, a third sub-pad zd3, and a fourth sub-pad zd4. The first sub-pad zd1 is arranged on the opposite side of the third sub-pad zd3. The second sub-pad zd2 is arranged on the opposite side of the fourth sub-pad zd4.

[0100] The second substrate 20 further includes a plurality of connection lines lj arranged on the same layer as the sub-conductive pads zd. A first sub-pad zd1 is correspondingly connected to a second sub-pad zd2 through the connection line lj. A third sub-pad zd3 is correspondingly connected to a fourth sub-pad zd4 through the connection line lj.

[0101] Please refer to Figure 9 , the first sub-pad zd1 is bonded and connected to the first mother pad 121. The second sub-pad zd2 is bonded and connected to the second mother pad 122. The third sub-pad zd3 is bonded and connected to the third mother pad 123. The fourth sub-pad zd4 is bonded and connected to the fourth mother pad 124.

[0102] The second substrate 20 further includes a signal line xh. One end of the signal line xh is connected to the first sub-pad zd1, and the other end of the signal line xh is connected to the third sub-pad zd3.

[0103] In this second embodiment, the signal line xh is taken as an example of a scan line for description. Each scan line xh correspondingly connects a first sub-pad zd1 and a third sub-pad zd3. Each first sub-pad zd1 is correspondingly bonded to a first mother pad 121, and each third sub-pad zd3 is correspondingly bonded to a third mother pad 123.

[0104] The first substrate 10 further includes a gate driving circuit 13, and the gate driving circuit 13 is arranged on the base 11. The gate driving circuit 13 is located on at least one side of the first substrate 10. The gate driving circuit 13 is electrically connected to the mother conductive pad md.

[0105] Since the gate driving circuit 13 is electrically connected to the mother conductive pad md, the gate driving circuit 13 can drive multiple second substrates 20, thereby saving multiple gate driving circuits 13 and multiple COF films, and further reducing the seam.

[0106] When the gate driving circuit 13 is located on one side of the first substrate 10, the splicing panel 100 is driven unidirectionally. When the gate driving circuit 13 is located on the opposite side of the first substrate 10, the splicing panel 100 is driven bidirectionally.

[0107] Optionally, please refer to Figure 10 , the second substrate 20 further includes a thin film transistor structure layer 21 and a light emitting device 22. The thin film transistor structure layer 21 is disposed on a side of the sub-conductive pad zd away from the first substrate 10. The light emitting device 22 is disposed on the thin film transistor structure layer 21.

[0108] Optionally, the thin film transistor structure layer 21 includes thin film transistors, which can be top-gate, bottom-gate or double-gate thin film transistors.

[0109] The light emitting device 22 can be a micro light emitting diode (Micro-LED) device, a sub-millimeter light emitting diode (Mini-LED) device, an organic light emitting diode (OLED) device, a quantum dot light emitting diode (QLED) device or a nano light emitting diode device, etc.

[0110] Optionally, the thin film transistor structure layer 21 includes a first buffer layer 211, a second buffer layer 212, an active layer 213, a first insulating layer 214, a first metal layer 215, a second insulating layer 216, an interlayer dielectric layer 217, a second metal layer (not shown in the figure) and a planarization layer 218, which are sequentially stacked and covered on the sub-conductive pad zd and the connection line lj.

[0111] Optionally, the first metal layer 215 includes a gate and a signal line xh. The signal line xh is a scanning line. The signal line xh is connected to the sub-conductive pad zd through a via hole. The second metal layer includes a data line, a source electrode and a drain electrode.

[0112] Optionally, the light emitting device 22 includes an anode 221, a pixel definition layer 222, a light emitting layer 223 and a cathode 224. The anode 221 is disposed on the planarization layer 218. The pixel definition layer 222 covers the planarization layer 218 and exposes the anode 221. The light emitting layer 223 is disposed on the anode 221. The cathode 224 is disposed on the light emitting layer 223.

[0113] Optionally, the splicing panel 100 further includes a packaging adhesive 40. The packaging adhesive 40 is encapsulated between the first substrate 10 and the second substrate 20.

[0114] The setting of the encapsulating glue 40 prevents external water and oxygen from invading the mother conductive pad md and the child conductive pad zd, and has the effect of protecting the mother conductive pad md and the child conductive pad zd.

[0115] The above has introduced in detail a splicing panel provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A splicing panel, characterized in that, Comprising: A first substrate, the first substrate including a first base and a plurality of mother conductive pads disposed on the base; And At least two second substrates, the at least two second substrates being spliced and disposed on the first substrate, with a seam between adjacent two of the second substrates; the second substrate includes a plurality of sub-conductive pads, the sub-conductive pads being located on at least one side of the second substrate and facing the first substrate; Wherein, the mother conductive pads are disposed corresponding to the seams, the mother conductive pads include a first portion and a second portion, the first portion is connected to one side of the second portion, the first portion is bonded and connected to the sub-conductive pad of one of the second substrates, and the second portion is bonded and connected to the sub-conductive pad of the other second substrate; The first substrate includes a plurality of setting areas, one setting area corresponding to one second substrate; in one setting area, a plurality of the mother conductive pads are located on the periphery of the setting area; adjacent two setting areas share at least one of the mother conductive pads, the first portion is located in one setting area, and the second portion is located in another setting area; The plurality of mother conductive pads include a plurality of first mother pads, a plurality of second mother pads, a plurality of third mother pads and a plurality of fourth mother pads, the setting area includes a first side, a second side, a third side and a fourth side connected end to end in sequence, the first side and the third side are oppositely disposed, and the second side and the fourth side are oppositely disposed; The plurality of first mother pads are correspondingly disposed on the first side, the plurality of second mother pads are correspondingly disposed on the second side, the plurality of third mother pads are correspondingly disposed on the third side, and the plurality of fourth mother pads are correspondingly disposed on the fourth side; The first substrate further includes a plurality of strip connection lines disposed on the same layer as the mother conductive pads, one first mother pad is correspondingly connected to one second mother pad through the connection line, and one third mother pad is correspondingly connected to one fourth mother pad through the connection line; In each of the second substrates, the plurality of sub-conductive pads include a first sub-pad and a second sub-pad, the first sub-pad and the second sub-pad are disposed on opposite sides; In each of the second substrates, the first sub-pad is bonded and connected to the first mother pad or the second mother pad, and the second sub-pad is bonded and connected to the third mother pad or the fourth mother pad; The second substrate further includes a signal line, one end of the signal line is connected to the first sub-pad, and the other end of the signal line is connected to the second sub-pad; The first substrate further includes a gate driving circuit, the gate driving circuit is located on at least one side of the first substrate, and the gate driving circuit is electrically connected to the mother conductive pads.

2. The splicing panel according to claim 1, wherein The signal line includes at least one of a scan line and a power supply signal line.

3. The splicing panel according to claim 2, wherein, The second substrate further includes: A thin film transistor structure layer, the thin film transistor structure layer is disposed on the side of the sub-conductive pad away from the first substrate, the thin film transistor structure layer includes a scan line, and the scan line is connected to the sub-conductive pad; A light emitting device, the light emitting device is disposed on the thin film transistor structure layer.

4. The splicing panel according to claim 1, characterized in that, The spliced panel further includes a packaging adhesive, and the packaging adhesive is encapsulated between the first substrate and the second substrate.

5. A splicing panel, characterized in that, Comprising: A first substrate, the first substrate including a first base and a plurality of mother conductive pads disposed on the base; And At least two second substrates, the at least two second substrates being spliced and disposed on the first substrate, with a seam between adjacent second substrates; the second substrate includes a plurality of sub-conductive pads, the sub-conductive pads being located on at least one side of the second substrate and facing the first substrate; Wherein, the mother conductive pads are disposed corresponding to the seams, the mother conductive pads include a first portion and a second portion, the first portion is connected to one side of the second portion, the first portion is bonded and connected to the sub-conductive pad of one second substrate, and the second portion is bonded and connected to the sub-conductive pad of another second substrate; The first substrate includes a plurality of setting areas, one setting area corresponding to one second substrate; in one setting area, a plurality of the mother conductive pads are located on the periphery of the setting area; at least one of the mother conductive pads is shared by adjacent two setting areas, the first portion is located in one setting area, and the second portion is located in another setting area; The plurality of mother conductive pads include a plurality of first mother pads, a plurality of second mother pads, a plurality of third mother pads and a plurality of fourth mother pads, the setting area includes a first side, a second side, a third side and a fourth side connected end to end in sequence, the first side and the third side are oppositely disposed, and the second side and the fourth side are oppositely disposed; The plurality of first mother pads are correspondingly disposed on the first side, the plurality of second mother pads are correspondingly disposed on the second side, the plurality of third mother pads are correspondingly disposed on the third side, and the plurality of fourth mother pads are correspondingly disposed on the fourth side; In each second substrate, the plurality of sub-conductive pads include a first sub-pad, a second sub-pad, a third sub-pad and a fourth sub-pad; the first sub-pad and the third sub-pad are disposed on opposite sides, and the second sub-pad and the fourth sub-pad are disposed on opposite sides; The second substrate further includes a plurality of connection lines disposed on the same layer as the sub-conductive pads, a first sub-pad is correspondingly connected to a second sub-pad through the connection line, and a third sub-pad is correspondingly connected to a fourth sub-pad through the connection line; The first sub-pad is bonded and connected to the first mother pad, the second sub-pad is bonded and connected to the second mother pad, the third sub-pad is bonded and connected to the third mother pad, and the fourth sub-pad is bonded and connected to the fourth mother pad; The second substrate further includes a signal line, one end of the signal line is connected to the first sub-pad, and the other end of the signal line is connected to the third sub-pad; The first substrate further includes a gate driving circuit, the gate driving circuit is located on at least one side of the first substrate, and the gate driving circuit is electrically connected to the mother conductive pads.

6. The splicing panel according to claim 5, characterized in that, The signal line includes at least one of a scanning line and a power signal line.

7. The splicing panel according to any one of claims 5-6, characterized in that, The second substrate further includes: A thin film transistor structure layer, the thin film transistor structure layer is disposed on the side of the sub-conductive pad away from the first substrate, the thin film transistor structure layer includes a scanning line, and the scanning line is connected to the sub-conductive pad; A light emitting device, the light emitting device is disposed on the thin film transistor structure layer.

8. The splicing panel according to claim 5, wherein The splicing panel further includes encapsulating glue, and the encapsulating glue is encapsulated between the first substrate and the second substrate.

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