MOS Schottky diode structure

Abstract

This invention provides a MOS-type Schottky diode structure, comprising an N-type substrate layer disposed on a metal layer on the back of the cathode; an N-type epitaxial layer located on the N-type substrate layer; multiple MOS regions embedded on the upper surface of the N-type epitaxial layer; the multiple MOS regions being distributed along a first direction; and a metal anode contact layer covering the N-type epitaxial layer and the multiple MOS regions; wherein the top width of the MOS regions in the first direction is smaller than the bottom width of the MOS regions in the first direction, and the top of the MOS regions is close to the metal anode contact layer. This structure increases the bottom width of the MOS regions while simultaneously increasing the width of the Schottky regions, thereby reducing high-temperature leakage current and on-state voltage drop, improving the breakdown voltage and switching speed of the MOS-type Schottky diode, and ensuring that the depletion layers generated by each MOS region remain connected when a reverse voltage is applied to the MOS-type Schottky diode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a MOS type Schottky diode structure. BACKGROUND

[0002] In the prior art, when it is required to reduce the on-voltage drop of the MOS type Schottky diode, the technology adopted is to increase the width of the Schottky region of the MOS type Schottky diode.

[0003] The prior art has the following defects in reducing the on-voltage drop of the MOS type Schottky diode: after the width of the Schottky region is increased, the width of the MOS region will also be narrowed, and the narrowing of the width of the MOS region will cause the problems of reduced withstand voltage and increased high-temperature leakage current of the MOS type Schottky diode. SUMMARY

[0004] In view of the above problems, the purpose of the embodiments of the present application is to provide a MOS type Schottky diode structure to solve the problems of reduced withstand voltage and increased high-temperature leakage current caused by the prior art method of reducing the on-voltage drop of the MOS type Schottky diode.

[0005] In order to solve the above problems, the embodiments of the present application disclose a MOS type Schottky diode structure, comprising:

[0006] An N-type substrate layer arranged on the cathode back metal layer;

[0007] An N-type epitaxial layer located on the N-type substrate layer;

[0008] A plurality of MOS regions embedded on the upper surface of the N-type epitaxial layer; the plurality of MOS regions are distributed along a first direction;

[0009] A metal anode contact layer covering the N-type epitaxial layer and the plurality of MOS regions; the first width of the top of the MOS region in the first direction is less than the second width of the bottom of the MOS region in the first direction, the top of the MOS region is close to the metal anode contact layer, and the first direction is perpendicular to the thickness direction of the N-type epitaxial layer.

[0010] The embodiment of the present application includes the following advantages: the MOS type Schottky diode structure includes: an N type substrate layer arranged on a cathode back metal layer; an N type epitaxial layer located on the N type substrate layer; a plurality of MOS regions embedded on the upper surface of the N type epitaxial layer; the plurality of MOS regions are distributed along a first direction; a metal anode contact layer covering the N type epitaxial layer and the plurality of MOS regions; a first width of a top of the MOS region in the first direction is less than a second width of a bottom of the MOS region in the first direction, and the top of the MOS region is close to the metal anode contact layer, and the first direction is perpendicular to the thickness of the N type epitaxial layer. Since the first width of the top of the MOS region in the first direction is less than the second width of the bottom of the MOS region in the first direction, the bottom width of the MOS region is increased while the width of the Schottky region is increased, the high-temperature leakage current and the on-voltage drop are reduced, the withstand voltage and the switching speed of the MOS type Schottky diode are improved, and the depletion layer generated by each MOS region can still be connected when the MOS type Schottky diode is applied with a reverse voltage. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a structure schematic diagram of a MOS type Schottky diode structure embodiment of the present application;

[0012] Figure 2 is a structure schematic diagram of another MOS type Schottky diode structure embodiment of the present application;

[0013] Figure 3 is a structure schematic diagram of a MOS type Schottky diode with a strip-shaped MOS region of the present application;

[0014] Figure 4 is a structure schematic diagram of a MOS type Schottky diode with a fence-shaped MOS region of the present application;

[0015] Figure 5 is a structure schematic diagram of a MOS type Schottky diode with a circular MOS region of the embodiment of the present application;

[0016] Figure 6 is a structure schematic diagram of a MOS type Schottky diode with a square-shaped MOS region of the embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0018] REFERENCE Figure 1As shown in FIG. 1, which shows a structural schematic diagram of an embodiment of a MOS type Schottky diode structure of the present application, and can specifically include: an N-type substrate layer 01 disposed on a cathode back metal layer 07; an N-type epitaxial layer 03 located on the N-type substrate layer 01; since the carrier concentration of the N-type substrate layer 01 is higher than that of the N-type epitaxial layer 03, the N-type substrate layer 01 can be represented by N+, and the N-type epitaxial layer 03 can be represented by N-; a plurality of MOS regions 031 embedded on the upper surface of the N-type epitaxial layer 03; the plurality of MOS regions 031 are distributed along a first direction, and the first direction is perpendicular to the thickness direction of the N-type epitaxial layer 03; a metal anode contact layer 06 covering the N-type epitaxial layer 03 and the plurality of MOS regions 031; the first width of the top of the MOS region 031 in the first direction is less than the second width of the bottom of the MOS region 031 in the first direction, and the top of the MOS region 031 is close to the metal anode contact layer 06.

[0019] Since the first width of the top of the MOS region 031 in the first direction is less than the second width of the bottom of the MOS region 031 in the first direction, the bottom width of the MOS region 031 is increased while the width of the Schottky region (the spacing between the tops of two adjacent MOS regions 031) is increased, wherein the increase of the width of the Schottky region can achieve the reduction of the on-state voltage drop and the improvement of the switching speed, and the increase of the bottom width of the MOS region 031 can achieve the reduction of the high-temperature leakage current and the improvement of the withstand voltage of the MOS type Schottky diode, and when a reverse voltage is applied to the MOS type Schottky diode, the depletion layer generated by each MOS region 031 can still be connected due to the increase of the bottom width of the MOS region 031.

[0020] Optionally, the width of the MOS region in the first direction gradually increases along a second direction, wherein the second direction is the direction in which the metal anode contact layer 06 points to the cathode back metal layer 07, thereby forming a bottle-shaped structure, making the MOS region have a flat inclined surface structure, and ensuring the entire inclined surface in the second direction to be at the same potential when a voltage is applied, thereby ensuring the uniformity and stability of the MOS region structure performance.

[0021] Optionally, the first width can range from 1um to 5um, the difference between the second width and the first width can range from 1um to 2um, the height between the top and the bottom of the MOS region 031 can range from 1um to 3um, and the spacing between the tops of two adjacent MOS regions 031 in the plurality of MOS regions 031 can range from 3um to 8um. In this way, the on-state voltage drop can be reduced and the switching speed can be improved, and at the same time, the high-temperature leakage current can be reduced to the greatest extent and the withstand voltage of the MOS type Schottky diode can be improved.

[0022] In addition, as the concentration of the N-type epitaxial layer 03 increases, the on-voltage of the MOS Schottky diode decreases, the reverse leakage current increases, the characteristic on-resistance decreases, and the junction capacitance increases. To obtain the smallest characteristic on-resistance, on-voltage, and junction capacitance under the condition of meeting the withstand voltage, the concentration of the N-type epitaxial layer 03 can range from 1 x 10 15 cm -3 to 8 x 10 16 cm -3 , and the thickness can range from 10 um to 150 um.

[0023] Optionally, the concentration of the N-type substrate layer 01 can range from 1 x 10 18 cm -3 to 1 x 10 19 cm -3 , and the thickness can range from 300 um to 500 um, to ensure the thickness of the MOS Schottky diode base and the growth of the N-type epitaxial layer 03.

[0024] Optionally, the thickness of the metal anode contact layer 06 can range from 0.5 um to 1 um, and the thickness of the cathode back metal layer 07 can range from 1 um to 2 um. The metal anode contact layer 06 can include a Schottky barrier alloy metal layer, which can be made of one or more materials such as Ti or Ni or Pt, and then sputter annealed to form a Schottky barrier alloy metal layer with a thickness of 0.5 um to 1 um. The cathode back metal layer 07 can be made of one or more materials such as Ti or Ni or Ag, and then sputter annealed to form a cathode back metal layer 07 with a thickness of 1 um to 2 um.

[0025] Optionally, the MOS region 031 can include an oxide layer 04 and a polysilicon layer 05 on the oxide layer 04.

[0026] Optionally, a plurality of trenches are opened on the top surface of the N-type epitaxial layer 03, the first width of the opening of the trench in the first direction is less than the second width of the bottom of the trench in the first direction, the inner wall of the trench is subjected to oxidation treatment (or deposition process treatment) and photolithography treatment, only leaving the oxide layer 04 in the trench, and the thickness of the oxide layer 04 can range from 0.2 um to 0.5 um. Further, polysilicon is deposited on the oxide layer 04, reflowed, leveled, and subjected to photolithography treatment, only leaving the polysilicon layer 05 in the trench, forming the MOS region 031, wherein the thickness of the polysilicon layer 05 is determined by filling the trench.

[0027] Optionally, as Figure 2As shown, the MOS Schottky diode may also include an N-type epitaxial transition layer 02. Since the carrier concentration in the N-type epitaxial transition layer 02 is between that of the N-type substrate layer 01 and the N-type epitaxial layer 03, N can be used to represent the N-type epitaxial transition layer 02. The N-type epitaxial transition layer 02 is located between the N-type substrate layer 01 and the N-type epitaxial layer 03. That is, the doping concentration of the N-type epitaxial transition layer 02 is higher than that of the N-type epitaxial layer 03, but much lower than that of the N-type substrate layer 01. By setting the N-type epitaxial transition layer 02, the thickness of the N-type epitaxial layer 03 can be reduced, thereby reducing the on-resistance while meeting the diode's longitudinal withstand voltage requirements.

[0028] Optionally, such as Figure 2 As shown, the MOS Schottky diode may further include an anode metal layer 08 located on the metal anode contact layer 06. This anode metal layer 08 may be made of one or more materials selected from Al or Cu, and then subjected to metal sputtering annealing and reflow trench filling treatment to form the anode metal layer 08. The thickness of the anode metal layer 08 can be from 0.5 μm to 6 μm. In practical applications, the thickness of the anode metal layer 08 can be selected according to the arrangement of the wires. Preferably, the anode metal layer 08 has a thickness of 3 μm.

[0029] Optionally, the cross-sectional shape of the MOS region 031 perpendicular to the second direction can be strip-shaped, fence-shaped, circular, or square, etc., that is, along the embodiment of the present invention Figure 1 In the view along direction A, MOS region 031 can be strip-shaped, fence-shaped, circular, or square, etc., and this invention does not impose any limitations on this. See also Figure 3 This diagram illustrates a MOS-type Schottky diode according to an embodiment of the present invention, wherein the MOS region 031 is arranged in a stripe shape in a plane perpendicular to the second direction. (See attached diagram.) Figure 4 This diagram illustrates a MOS-type Schottky diode according to an embodiment of the present invention, wherein the MOS region 031 is arranged in a fence-like pattern in a plane perpendicular to the second direction. (See attached diagram.) Figure 5 This diagram illustrates a MOS-type Schottky diode according to an embodiment of the present invention, wherein the MOS region 031 is circularly distributed in a plane perpendicular to the second direction. (See attached diagram.) Figure 6 The diagram illustrates a MOS-type Schottky diode according to an embodiment of the present invention, wherein the MOS region 031 is distributed in a square shape in a plane perpendicular to the second direction.

[0030] Optionally, the N-type substrate layer 01, N-type epitaxial layer 03, and N-type epitaxial transition layer 02 in the MOS Schottky diode can be formed of silicon carbide, silicon, or other materials.

[0031] The MOS-type Schottky diode structure of this invention has the following advantages: The MOS-type Schottky diode structure includes: an N-type substrate layer disposed on a metal layer on the back of the cathode; an N-type epitaxial layer located on the N-type substrate layer; a plurality of MOS regions embedded on the upper surface of the N-type epitaxial layer; the plurality of MOS regions being distributed along a first direction; a metal anode contact layer covering the N-type epitaxial layer and the plurality of MOS regions; the top of the MOS region has a first width in the first direction that is smaller than the bottom width of the MOS region in the first direction, and the top of the MOS region is close to the metal anode contact layer. Because the top width of the MOS region in the first direction is smaller than the bottom width of the MOS region in the first direction, the bottom width of the MOS region is increased while the width of the Schottky region is increased, thereby reducing high-temperature leakage current and on-state voltage drop, improving the withstand voltage and switching speed of the MOS-type Schottky diode, and the depletion layers generated by each MOS region can still be connected when a reverse voltage is applied to the MOS-type Schottky diode.

[0032] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0033] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0034] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0035] The above provides a detailed description of a MOS-type Schottky diode structure provided by the present invention. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A MOS-type Schottky diode structure, characterized in that, include: An N-type substrate layer disposed on the metal layer on the back side of the cathode; An N-type epitaxial layer located on the N-type substrate layer; Multiple MOS regions are embedded in the upper surface of the N-type epitaxial layer; the multiple MOS regions are distributed along a first direction; the first direction is perpendicular to the thickness of the N-type epitaxial layer; A metal anode contact layer covering the N-type epitaxial layer and the plurality of MOS regions; the top of the MOS region has a first width in the first direction that is smaller than the bottom of the MOS region in the first direction that is a second width, and the top of the MOS region is close to the metal anode contact layer; The width of the MOS region gradually increases along the second direction from the first direction; the second direction is the direction from the metal anode contact layer to the back metal layer of the cathode.

2. The structure according to claim 1, characterized in that, The first width ranges from 1µm to 5µm.

3. The structure according to claim 2, characterized in that, The difference between the second width and the first width ranges from 1µm to 2µm.

4. The structure according to claim 1, characterized in that, The height between the top and bottom of the MOS region ranges from 1µm to 3µm.

5. The structure according to claim 1, characterized in that, The spacing between the tops of two adjacent MOS regions in the plurality of MOS regions ranges from 3µm to 8µm.

6. The structure according to claim 1, characterized in that, The concentration range of the N-type epitaxial layer is 1×10⁻⁶. 15 cm -3 Up to 8×10 16 cm -3 The thickness ranges from 10um to 150um.

7. The structure according to claim 1, characterized in that, The concentration range of the N-type substrate layer is 1×10⁻⁶. 18 cm -3 Up to 1×10 19 cm -3 The thickness ranges from 300um to 500um.

8. The structure according to claim 1, characterized in that, The thickness of the metal anode contact layer ranges from 0.5 μm to 1 μm, and the thickness of the cathode back metal layer ranges from 1 μm to 2 μm.

9. The structure according to claim 1, characterized in that, The MOS region includes an oxide layer and a polysilicon layer located on the oxide layer, the thickness of which ranges from 0.2 μm to 0.5 μm.

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