Power converter and its control circuit

Abstract

The present application provides a control circuit for a power converter. The power converter includes a switching circuit, the switching circuit including a first switching transistor and a second switching transistor. The control circuit includes: a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to input a reference signal, the second input terminal is used to input a feedback signal, and the output terminal is used to output a comparison signal; a minimum off-time generation circuit; an on-time generation circuit, which generates an on-time signal to control the first switching transistor and the second switching transistor, respectively; and a slope compensation circuit, which generates a slope compensation signal. The slope compensation signal is superimposed with the feedback signal and received by the first or second input terminal of the comparator. The slope compensation signal has a first slope peak value in steady state and a second slope peak value during a transient response period caused by a load current jump. The first slope peak value is smaller than the second slope peak value, and the change from the first slope peak value to the second slope peak value is independent of the DC bias setting of the slope compensation circuit.

Description

Technical Field

[0001] The present application mainly relates to power electronics technology, and in particular to a power converter and a control circuit thereof. Background Art

[0002] There are many control methods for power converters, such as voltage control, current control, hysteresis control, and constant on-time control. Among them, the constant on-time control method is widely used in power converters due to its excellent dynamic response speed and high light-load efficiency.

[0003] Constant on-time control offers excellent dynamic response speed and light-load efficiency, but it places high demands on the output voltage ripple shape. Large voltage ripple can adversely affect the load. Existing technologies typically address this issue by superimposing a slope compensation signal on the feedback signal or voltage reference. However, when the compensation amplitude is limited, the output voltage can oscillate during transient response.

[0004] Currently, a common approach to solving this problem is to introduce a DC bias that changes with the output current into the slope compensation signal. For example, the synchronous rectifier current of a Buck switching power supply circuit is used to generate the DC bias of the slope compensation signal. However, this approach will cause a large DC error and requires the addition of a very complex correction circuit for correction. In addition, when the circuit operating frequency is high and the sampling window is small, the sampling accuracy will be greatly affected.

[0005] Application Contents

[0006] The technical problem to be solved by the present application is to provide a power converter having a slope compensation circuit that does not rely on DC bias settings to increase the compensation amplitude, thereby achieving stability in the circuit's operating state.

[0007] To solve the above technical problems, the present application provides a control circuit for a power converter, the power converter including a switching circuit, the switching circuit including a first switching transistor and a second switching transistor, the switching circuit being configured to receive an input voltage and convert the input voltage into an output voltage, the control circuit including: a comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal being configured to input a reference signal, the second input terminal being configured to input a feedback signal, and the output terminal being configured to output a comparison signal; the feedback signal being derived based on the output voltage;

[0008] An on-time generating circuit generates an on-time signal, which is then passed through a driving circuit to generate a first control signal and a second control signal, respectively controlling the first switching transistor and the second switching transistor; and a slope compensation circuit generates a slope compensation signal. The slope compensation signal is superimposed on the feedback signal and received by the first or second input terminal of the comparator. The slope compensation signal has a first slope peak value in a steady state and a second slope peak value during a transient response to a load current jump. The first slope peak value is smaller than the second slope peak value, and the change from the first slope peak value to the second slope peak value is independent of the DC bias setting of the slope compensation circuit.

[0009] In one embodiment of the present application, the slope compensation circuit includes: a compensation capacitor having a first end and a second end, wherein the second end is grounded and the first end generates the slope compensation signal; and a compensation capacitor control circuit, wherein in a transient state, the compensation capacitor control circuit controls a charge and discharge circuit to change the peak value of the slope compensation signal from the first slope peak value to the second slope peak value.

[0010] In one embodiment of the present application, the compensation capacitor control circuit includes: a first constant current source having an input terminal and an output terminal, the input terminal being used to connect to a power supply voltage; a first switch having a first terminal, a second terminal, and a control terminal, the first terminal being coupled to the output terminal of the first current source, the control terminal being used to receive the first control signal, and the second terminal being connected to the first terminal of the compensation capacitor; a second switch having a first terminal, a second terminal, and a control terminal, the first terminal being coupled to the second terminal of the first switch, and the control terminal being used to receive the second control signal; a second constant current source having an input terminal and an output terminal, the input terminal being coupled to the second terminal of the second switch, and the output terminal being connected to a reference ground; a compensation capacitor having a first terminal and a second terminal, the first terminal being coupled to the second terminal of the first switch, and the second terminal being connected to the reference ground; wherein the output current of the first constant current source and the output current of the second constant current source are set so that in steady state, the initial value at the beginning of each cycle of the slope compensation signal is equal to the final value at the end.

[0011] In one embodiment of the present application, the slope compensation circuit further includes an initial value recovery circuit, which operates at the end of each working cycle so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

[0012] In one embodiment of the present application, the initial value recovery circuit acts at the end of each working cycle in a transient state, so that the slope compensation signal accelerates to approach the initial value.

[0013] In one embodiment of the present application, the initial value recovery circuit does not function at the end of each working cycle in a transient state.

[0014] In one embodiment of the present application, the initial value recovery circuit charges or discharges the compensation capacitor so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

[0015] In one embodiment of the present application, the initial value recovery circuit includes: a first power transistor having a first source, a first drain, and a first gate, the first source being connected to the second end of the first switch, and the first drain being connected to a reference ground or a power supply voltage; a second comparator having a first input, a second input, and an output, the first input receiving the cycle initial value of the slope compensation signal, and the output being connected to the first gate; a sampling control switch having a first end, a second end, and a control end, the first end being connected to the first source of the first power transistor, the second end being connected to the second input of the second comparator, and the control end receiving a sampling control signal, wherein the sampling control signal closes the sampling control switch at the end of a working cycle; and a holding capacitor having a first end and a second end, the first end being connected to the second end of the sampling control switch, and the second end being connected to the reference ground.

[0016] The present application also provides a power converter, comprising a switching circuit, the switching circuit including a first switching transistor and a second switching transistor, the switching circuit being configured to receive an input voltage and convert the input voltage into an output voltage; a control circuit including a comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal being configured to input a reference signal, the second input terminal being configured to input a feedback signal, and the output terminal being configured to output a comparison signal; the feedback signal being derived based on the output voltage; an on-time generation circuit generating an on-time signal, which generates a first control signal and a second control signal through a drive circuit, respectively controlling the first switching transistor and the second switching transistor; and a slope compensation circuit generating a slope compensation signal, the slope compensation signal being superimposed on the feedback signal and received by the first or second input terminal of the comparator, wherein the slope compensation signal has a first slope peak value in a steady state and a second slope peak value during a transient response period caused by a load current jump, the first slope peak value being smaller than the second slope peak value, and the change from the first slope peak value to the second slope peak value is independent of a DC bias setting of the slope compensation circuit.

[0017] Compared with the prior art, the present application has the following advantages: the power converter of the technical solution of the present application, while realizing a constant on-time control mode, provides a slope compensation circuit that is independent of the DC bias setting to increase the compensation amplitude, thereby avoiding output voltage oscillation when the circuit load jumps, and realizing stable operation of the power converter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are provided to provide a further understanding of the present application. They are incorporated into and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and, together with the present specification, serve to explain the principles of the present application. In the accompanying drawings:

[0019] Figure 1 Schematic diagram of the circuit structure of a power converter according to an embodiment of the present application.

[0020] Figure 2 2 is a schematic structural diagram of a slope compensation circuit according to an embodiment of the present application.

[0021] Figure 3A FIG. 1 is a schematic structural diagram of a slope compensation circuit according to an embodiment of the present application.

[0022] Figure 3B FIG. 1 is a waveform diagram of a sampling control signal of a slope compensation circuit according to an embodiment of the present application.

[0023] Figure 4 FIG. 1 is a schematic diagram of a slope compensation waveform of a power converter in steady-state operation according to an embodiment of the present application.

[0024] Figure 5 1 is a waveform diagram of a power converter when the load changes and the slope compensation signal amplitude variation range is fixed according to an embodiment of the present application.

[0025] Figure 6 3 is a waveform diagram of the slope compensation signal amplitude accumulation for compensation when the load of the power converter jumps according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the above-mentioned objectives, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0028] As used herein, unless the context clearly indicates otherwise, the terms "a," "an," "an," and / or "the" are not intended to refer to the singular but may include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements specifically identified, and these steps and elements do not constitute an exclusive list. A method or apparatus may also include other steps or elements.

[0029] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is solely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. Furthermore, while the terms used in this application are selected from commonly known and commonly used terms, some terms mentioned in this specification may have been selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant sections of this description. Furthermore, this application should be understood not only by the actual terms used, but also by the meaning implied by each term.

[0030] It should be understood that when a component is referred to as being “on another component,” “connected to another component,” “coupled to another component,” or “contacting another component,” it can be directly on, connected to, coupled to, or contacting the other component, or intervening components may be present. In contrast, when a component is referred to as being “directly on another component,” “directly connected to,” “directly coupled to,” or “directly contacting” another component, there are no intervening components. Similarly, when a first component is referred to as being “electrically in contact with” or “electrically coupled to” a second component, an electrical path exists between the first and second components that allows current to flow. This electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between the conductive components.

[0031] The embodiments of the present application describe a power converter and a control circuit and a control method thereof.

[0032] Figure 1 Schematic diagram of the circuit structure of a power converter according to an embodiment of the present application. Figure 1 Figure (a) shows the switching circuit included in the power converter. Figure 1 Figure (b) shows the control circuit of the power converter. Figure 1As shown in Figure (a), the switching circuit includes a first switching transistor M1 and a second switching transistor M2. In one embodiment, the first switching transistor M1 and the second switching transistor M2 each have a source, a gate, and a drain. The first switching transistor M1 and the second switching transistor M2 are connected in series. Specifically, the source of the first switching transistor M1 is connected to the drain of the second switching transistor M2, forming a node 101. The first end of the output inductor L1 is coupled to the node 101, the second end of L1 is connected to the first end of the output capacitor C1, and the second end of the output capacitor C1 is grounded.

[0033] Continuing to refer to Figure 1 Figure (a), the drain of the first switching transistor M1 in the switching circuit receives an input voltage VIN. The source of the second switching transistor is grounded. The gates of the first switching transistor M1 and the second switching transistor M2 are respectively used to receive a first control signal HSPWM and a second control signal LSPWM. The voltage on the first end of the output capacitor C1 is the output voltage VOUT. The types of the first switching transistor M1 and the second switching transistor M2 can be, for example, NMOS, or other types of transistors can be selected according to needs.

[0034] As Figure 1 As shown in Figure (b), in one embodiment, the control circuit of the power converter includes a comparator COM1, a logic circuit 102, a conduction time generation circuit, a minimum off-time generation circuit, and a ramp compensation circuit.

[0035] Referring to Figure 1 Figure (b), the comparator COM1 has a first input terminal, a second input terminal, and an output terminal. The first input terminal receives a reference signal VREF. The second input terminal receives a feedback signal VFB. The logic circuit 102 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the logic circuit is coupled to the output terminal of the comparator COM1 to receive a comparison signal. The second input terminal of the logic circuit is coupled to the output terminal of the minimum off-time generation circuit to receive a minimum off-time signal. The output terminal of the logic circuit 102 is coupled to the input terminal of the conduction time generation circuit. The output terminal of the conduction time generation circuit forms a conduction time signal PWM. The conduction time signal PWM generates a first control signal HSPWM and a second control signal LSPWM through a driving circuit (not shown in the figure). The first control signal HSPWM and the second control signal LSPWM respectively control the turn-on and turn-off of the first switching transistor M1 and the second switching transistor M2. The feedback signal VFB is obtained according to the output voltage VOUT. For example, VFB is the product of VOUT and a proportionality coefficient k, and the range of the proportionality coefficient k can be 0 < k ≤ 1. A specific implementation manner is, for example, that the output voltage VOUT obtains the feedback signal VFB through a voltage dividing resistor network.

[0036] The minimum off-time generation circuit overcomes the influence of parasitic capacitance of components in the circuit, such as the switch tube, and avoids the circuit turning on again before the output voltage has reached zero when the circuit is turned off, thereby avoiding the resulting circuit loss, interference from conduction and radiation, or damage to circuit components.

[0037] The slope compensation circuit generates a slope compensation signal VRAMP, which is received by the first or second input terminal of the comparator. Specifically, it can be connected to the VFB terminal of the comparator using positive slope compensation, or it can be connected to the VREF terminal of the comparator using reverse slope compensation. In reverse compensation, the slope peak refers to the lowest value of the falling section. The slope compensation circuit includes a compensation capacitor C2. Figure 1 In FIG. 5( b ), a first terminal of the compensation capacitor C2 is coupled to the second input terminal of the comparator, and a second terminal of the compensation capacitor C2 is grounded.

[0038] In one embodiment, logic circuit 102 includes an AND gate G1 and an RS flip-flop. The first and second inputs of AND gate G1 are coupled to the output of the comparator and the output of the minimum off-time generation circuit, respectively, to receive a comparison signal and a minimum off-time signal, respectively. The output of AND gate G1 is connected to the S port of the RS flip-flop. The Q terminal of the RS flip-flop is coupled to the input of the on-time generation circuit to provide an excitation signal. The R terminal of the RS flip-flop receives a reset signal. The reset signal can be either a synchronous signal or an asynchronous signal.

[0039] During circuit operation, when the voltage at the first input of the comparator is higher than the voltage at the second input, the comparator output is set high, i.e., the comparison signal is at a high level. When the output of the minimum off-time generation circuit is also at a high level, the output of AND gate G1 is also set high. The RS flip-flop receives an excitation signal at its S terminal, generating an output signal at its Q terminal, which is coupled to the input of the on-time generation circuit, enabling the on-time timer. The output of the on-time generation circuit forms an on-time signal PWM. The on-time signal PWM then passes through the driver circuit to generate a first control signal HSPWM and a second control signal LSPWM, which respectively control the on and off states of the first switch M1 and the second switch M2, thereby achieving power conversion. In one embodiment, the on-time is inversely proportional to the amplitude of the input voltage VIN and directly proportional to the amplitude of the output voltage VOUT. This ensures that the switching frequency of the switching circuit remains substantially constant under varying input voltage VIN and output voltage VOUT conditions.

[0040] The comparator's second input voltage includes the feedback voltage VFB and the slope compensation voltage (i.e., slope compensation signal) VRAMP. When there is no slope compensation signal VRAMP, the constant on-time control method has better dynamic response speed and light-load efficiency, but also has higher requirements on the shape of the output voltage ripple. When the ESR (Equivalent Series Resistance) of the output capacitor is very small, the ripple on the output capacitor C1 and the current I L Compared with the inductor, the phase lags by 90°, so the output voltage cannot reflect the inductor current I in time. L When the first control signal HSPWM is at a high level (the on-time signal PWM is also at a high level), the inductor current I L However, due to the aforementioned 90° phase lag, the output voltage VOUT cannot establish itself in a timely manner, and the feedback voltage VFB cannot rise either. Consequently, it is possible that after the current on-period of the HSPWM signal has expired, VFB may still be lower than VREF. In this case, an unnecessary additional PWM signal is activated, resulting in uneven PWM signal intervals and instability. Therefore, a slope compensation signal VRAMP is added to the feedback signal VFB to improve circuit stability, or it can be subtracted from VREF to improve circuit stability.

[0041] The slope compensation signal VRAMP is a periodic signal, and its period is the same as the PWM signal period. Each period can be called a duty cycle. The amplitude of the VRAMP signal can vary within a fixed range. For example, the waveform of the slope compensation signal VRAMP is a periodic sawtooth wave. In this case, the slope compensation signal VRAMP is as follows: Figure 4 As shown in Figure (a). Figure 4 FIG. 1 is a schematic diagram of a slope compensation waveform of a power converter in steady-state operation according to an embodiment of the present application. Figure 4 Figure (b) is a waveform diagram of the feedback signal VFB superimposed on the slope compensation signal VRAMP. Figure 4 Figure (c) is the waveform of the on-time signal PWM. Figure 4 In Figure (d), we can see the inductor current I L The waveform and output current I OUT The waveform of I OUT is the load current. I OUT The waveform is related to the load characteristics. For example, if the load operation mode is intermittent constant current mode, the load current I OUT It fluctuates between different values. At the same time, when in constant current mode, the load current value is also relatively stable.

[0042] The aforementioned slope compensation method effectively ensures circuit stability during steady-state operation of the power converter circuit. However, during load changes, the output voltage VOUT drops significantly. If the slope compensation signal VRAMP is limited to a fixed range, the phase lag of the output voltage VOUT cannot be corrected, resulting in output voltage oscillation and circuit instability. Figure 5 1 is a waveform diagram of a power converter when the load changes and the slope compensation signal amplitude variation range is fixed according to an embodiment of the present application. Figure 5 Figure (c) is the waveform of the on-time signal PWM. Figure 5 Figure (a) is the waveform of the VRAMP slope compensation signal. Figure 5 Figure (b) is the waveform of the output voltage VOUT. Figure 5 As can be seen in Figure (b), the output voltage VOUT shows an obvious oscillation waveform. Figure 5 The middle (d) figure shows the output current I OUT The waveform of the inductor current I L waveform.

[0043] In some embodiments of the present application, in order to improve the circuit stability of a power converter with a constant on-time control mode during steady-state operation and load jump, the slope compensation circuit includes a compensation capacitor C2 and a compensation capacitor control circuit, wherein in a transient state, the compensation capacitor control circuit controls the charge and discharge circuit to change the peak value of the slope compensation signal from a first slope peak value to a second slope peak value.

[0044] Figure 2 FIG. 1 is a schematic diagram of the structure of a slope compensation circuit according to an embodiment of the present application. Figure 2 As shown, the compensation capacitor control circuit of the slope compensation circuit includes a first constant current source I1, a first switch S1, a second constant current source I2, and a second switch S2. The first constant current source I1 has an input and an output, with the input connected to a power supply voltage Vs. The first switch S1 has a first terminal, a second terminal, and a control terminal. The first terminal is connected to the output of the first constant current source I1. The control terminal is configured to receive a first control signal HSPWM. The second terminal of the first switch S1 is coupled to the first terminal of the compensation capacitor C2. The second terminal of the compensation capacitor C2 is connected to a reference ground. The second switch S2 has a first terminal, a second terminal, and a control terminal. The first terminal of S2 is coupled to the second terminal of the first switch S1, that is, to the first terminal of the compensation capacitor C2. The control terminal of S2 receives a second control signal LSPWM. The second terminal of S2 is connected to the first terminal of the second constant current source I2. The second terminal of the second constant current source I2 is connected to the reference ground. A slope compensation signal VRAMP is generated at the first terminal of the compensation capacitor C2.

[0045] In one embodiment, the output current of the first constant current source and the output current of the second constant current source are set so that in a steady state, the initial value of the slope compensation signal at the beginning and the final value at the end of each cycle are equal.

[0046] Specifically, when the on-time signal PWM is high (i.e., when the first control signal HSPWM in the power converter's switching circuit is high), the control terminal of the first switch S1 closes upon receiving this control signal, and the first constant current source I1 then charges the compensation capacitor C2. Correspondingly, when the PWM signal is low and the control signal LSPWM of the second switch M2 is high, the control terminal of the second switch S2 closes upon receiving this control signal, and the compensation capacitor C2 is discharged through the second current source I2. By configuring the parameters of constant current sources I1 and I2, the charge and discharge of the compensation capacitor C2 within a single cycle can be equal during steady-state operation.

[0047] In some embodiments, the slope compensation circuit further includes an initial value recovery circuit. The initial value recovery circuit operates at the end of each operating cycle, allowing the slope compensation signal to be restored to a preset initial value at the end of each operating cycle in steady state. Specifically, the initial value recovery circuit may be activated when the difference between "VFB + VRAMP" (i.e., the feedback signal VFB superimposed on the slope compensation signal VRAMP) and the reference signal VREF reaches a predetermined threshold and shut down at the end of VRAMP's operating cycle. Alternatively, the circuit may be turned on for a fixed period of time before being turned off.

[0048] In one embodiment, the initial value recovery circuit also operates at the end of each operating cycle during transient conditions, accelerating the slope compensation signal VRAMP toward the initial value. As previously mentioned, the end of each operating cycle can refer to the initial value recovery circuit being activated when the difference between "VFB + VRAMP" (i.e., the feedback signal VFB superimposed on the slope compensation signal VRAMP) and the reference signal VREF reaches a set threshold and shutting down at the end of VRAMP's operating cycle. Alternatively, the initial value recovery circuit can be turned off after being on for a fixed period of time. During transient conditions, the initial value recovery circuit in the power converter's control circuit can help VRAMP quickly return to a steady-state state after the transient response reaches its peak, avoiding the slow process of reducing VRAMP's amplitude by simply using the capacitor's charge and discharge cycles. In another embodiment, the initial value recovery circuit does not operate at the end of each operating cycle during transient conditions. The end of each operating cycle can specifically refer to the period from the difference between "VFB + VRAMP" and the reference signal VREF reaching a set threshold to the end of VRAMP's operating cycle.

[0049] Figure 3A FIG. 1 is a schematic diagram of the structure of a slope compensation circuit according to an embodiment of the present invention, including the specific structure of the initial value recovery circuit. Figure 3A As shown, in some embodiments, the initial value recovery circuit includes a sample-and-hold circuit and a control circuit to adjust the charging current of the first constant current source I1 and / or the discharging current of the second constant current source I2. The initial value recovery circuit charges or discharges the compensation capacitor so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

[0050] Specifically, the initial value recovery circuit may include a first power transistor M3, a second comparator COM2, a sampling control switch Sc, and a holding capacitor C3. The first power transistor M3 has a first source, a first drain, and a first gate. The first source of M3 is connected to the second end of the first switch S1, that is, to the first end of the compensation capacitor C2. The first drain of M3 is connected to the reference ground or the power supply voltage Vs. The second comparator COM2 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second comparator COM2 receives the cycle initial value VSTART of the slope compensation signal during steady-state operation. The output terminal of COM2 is connected to the first gate of the first power transistor M3. The positive and negative polarity of the first input terminal and the second input terminal of the comparator can be set according to actual needs.

[0051] The sampling control switch Sc has a first terminal, a second terminal, and a control terminal. The first terminal of the sampling control switch Sc is connected to the first source of the first power transistor M3. The second terminal of the sampling control switch Sc is connected to the second input terminal of the second comparator COM2. The control terminal of the sampling control switch Sc receives a sampling control signal (Sample Control). In one embodiment, the sampling control signal closes the sampling control switch at the end of the duty cycle. The holding capacitor C3 has a first terminal and a second terminal. The first terminal of C3 is connected to the second terminal of the sampling control switch Sc. The second terminal of C3 is connected to the reference ground GND.

[0052] Figure 3B FIG. 1 is a waveform diagram of a sampling control signal (Sample Control) of a slope compensation circuit according to an embodiment of the present application. Figure 3BAs shown, during steady-state operation of the power converter, the sampling control signal (Sample Control) is set to a high level at the end of each operating cycle of the slope compensation signal VRAMP, for example, when the difference between the value of "VFB + VRAMP" and the reference signal VREF reaches a set threshold. Assuming its duration is Td, it is equivalent to a narrow pulse. The high level can also last until the end of the operating cycle. During the narrow pulse formed by the high level, the sampling control switch Sc is closed. In other words, the sampling control signal causes the sampling control switch Sc to close at the end of the operating cycle. The second comparator COM2 compares the voltage VSTART at the first input terminal with the sampled voltage value received at the second input terminal. If the sampled voltage value received at the second input terminal is greater than VSTART, the first power transistor M3 is turned on, and the value of VRAMP continues to decrease until it reaches the initial value VSTART of the slope compensation signal VRAMP during steady-state operation.

[0053] When the load of the power converter jumps, the slope compensation circuit of the technical solution of the present application can accumulate the slope compensation signal VRAMP, rather than being limited by the maximum amplitude and fluctuating within a fixed amplitude range, thereby compensating for the phase lag of the output voltage ripple, ensuring that the power converter circuit still has good stability when the load jumps. At this time, the waveform of VRAMP is still a sawtooth waveform, but the amplitude can be accumulated. At the same time, when the load jumps, after an adjustment process, the value of VRAMP can still be restored to the pre-set initial value, which can be specifically the same value as the cycle initial value VSTART during steady-state operation. At this time, the output voltage VOUT also returns to the steady-state value after adjustment. In addition, the structure of the compensation capacitor control circuit in the technical solution of the present application does not require the setting of a DC bias circuit, which simplifies the circuit structure.

[0054] Figure 6 3 is a waveform diagram of the slope compensation signal amplitude accumulation for compensation when the load of the power converter jumps according to an embodiment of the present application. Figure 6 Figure (c) is a waveform diagram of the on-time signal PWM. Figure 6 Figure (a) is a waveform diagram of the VRAMP slope compensation signal. The slope compensation signal has a first slope peak value PV1 when in steady state, and a second slope peak value PV2 during transient response. For example, Figure 6 Indicated in Figure (a). Figure 6 Figure (b) is the waveform of the output voltage VOUT. Figure 6 The middle (d) figure shows the output current I OUT The waveform of the inductor current I L The waveform of Figure 6As can be seen in Figure (b), the output voltage VOUT shows no obvious oscillation. After the power converter's dynamic load changes, the output voltage VOUT returns to a stable state through adjustment of the on-time signal PWM and compensation by VRAMP.

[0055] The present application also provides a power converter, comprising a switch circuit and a control circuit. The structures of the switch circuit and the control circuit are as described above.

[0056] The power converter of the technical solution of the present application realizes a constant on-time control mode. At the same time, the cumulative compensation of the slope compensation signal formed by the slope compensation circuit that does not rely on the DC bias setting to increase the compensation amplitude can ensure that the power converter circuit can still operate stably when the circuit load jumps, thereby avoiding the oscillation of the output voltage.

[0057] This application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic associated with at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0058] Similarly, it should be noted that, in order to simplify the description of this application and thus facilitate understanding of one or more embodiments of the application, the foregoing description of the embodiments of this application sometimes combines multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the subject matter of this application requires more features than those recited in the claims. In fact, the features of an embodiment may be fewer than all the features of the individual embodiments disclosed above.

[0059] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions can be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the scope of the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A control circuit for a power converter, the power converter comprising a switching circuit, the switching circuit comprising a first switching transistor and a second switching transistor, the switching circuit being configured to receive an input voltage and convert the input voltage into an output voltage, the control circuit comprising: a comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to input a reference signal, the second input terminal is used to input a feedback signal, and the output terminal is used to output a comparison signal; The feedback signal is obtained according to the output voltage; A conduction time generating circuit generates a conduction time signal, which is passed through a driving circuit to generate a first control signal and a second control signal, respectively controlling the first switch tube and the second switch tube; as well as A slope compensation circuit is configured to generate a slope compensation signal, wherein the slope compensation signal is superimposed on the feedback signal and received by the first or second input terminal of the comparator, wherein the slope compensation signal has a first slope peak value in a steady state, and has a second slope peak value during a transient response period caused by a load current jump, wherein the first slope peak value is smaller than the second slope peak value, and the change from the first slope peak value to the second slope peak value is independent of the DC bias setting of the slope compensation circuit, and the slope compensation circuit includes an initial value recovery circuit, wherein the initial value recovery circuit includes: a first power transistor having a first source, a first drain, and a first gate, wherein the first source is connected to the The second terminal of the first switch, the first drain is connected to a reference ground or a power supply voltage; the second comparator has a first input terminal, a second input terminal, and an output terminal, the first input terminal receives the cycle initial value of the slope compensation signal, and the output terminal is connected to the first gate; the sampling control switch has a first terminal, a second terminal, and a control terminal, the first terminal is connected to the first source of the first power transistor, the second terminal is connected to the second input terminal of the second comparator, and the control terminal receives a sampling control signal, wherein the sampling control signal closes the sampling control switch at the end of the working cycle; the holding capacitor has a first terminal and a second terminal, the first terminal is connected to the second terminal of the sampling control switch, and the second terminal is connected to the reference ground.

2. The control circuit according to claim 1, wherein: The slope compensation circuit includes: a compensation capacitor having a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal generates the slope compensation signal; The compensation capacitor control circuit controls the charge and discharge circuit to change the peak value of the slope compensation signal from the first slope peak value to the second slope peak value in a transient state.

3. The control circuit according to claim 2, characterized in that: The compensation capacitor control circuit includes: A first constant current source having an input end and an output end, wherein the input end is used to connect to a power supply voltage; a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the output terminal of the first current source, the control terminal is configured to receive the first control signal, and the second terminal is connected to the first terminal of the compensation capacitor; a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the first switch, and the control terminal is configured to receive the second control signal; a second constant current source having an input terminal and an output terminal, wherein the input terminal is coupled to the second terminal of the second switch, and the output terminal is connected to a reference ground; The output current of the first constant current source and the output current of the second constant current source are set so that in a steady state, an initial value of the slope compensation signal at the beginning and a final value at the end of each cycle are equal.

4. The control circuit according to claim 1, wherein: The initial value recovery circuit operates at the end of each working cycle, so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

5. The control circuit according to claim 4, characterized in that: The initial value recovery circuit acts at the end of each working cycle in a transient state, so that the slope compensation signal accelerates to approach the initial value.

6. The control circuit according to claim 4, characterized in that: The initial value recovery circuit does not function at the end of each working cycle in a transient state.

7. The control circuit according to claim 2, characterized in that: The initial value recovery circuit charges or discharges the compensation capacitor so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

8. A power converter comprising: A switching circuit, comprising a first switching transistor and a second switching transistor, configured to receive an input voltage and convert the input voltage into an output voltage; Control circuit, including: a comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is used to input a reference signal, the second input terminal is used to input a feedback signal, and the output terminal is used to output a comparison signal; the feedback signal is obtained according to the output voltage; A conduction time generating circuit generates a conduction time signal, which is passed through a driving circuit to generate a first control signal and a second control signal, respectively controlling the first switch tube and the second switch tube; as well as A slope compensation circuit generates a slope compensation signal, which is superimposed on the feedback signal and received by the first or second input terminal of the comparator. The slope compensation signal has a first slope peak value in a steady state, and has a second slope peak value during a transient response period caused by a load current jump. The first slope peak value is smaller than the second slope peak value, and the change from the first slope peak value to the second slope peak value is independent of the DC bias setting of the slope compensation circuit. The slope compensation circuit includes an initial value recovery circuit, which includes: a first power transistor having a first source, a first drain, and a first gate, wherein the first source a first terminal connected to the second terminal of the first switch, and the first drain connected to a reference ground or a power supply voltage; a second comparator having a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal receives a cycle initial value of the slope compensation signal; a sampling control switch having a first terminal, a second terminal, and a control terminal, wherein the first terminal is connected to the first source of the first power transistor, the second terminal is connected to the second input terminal of the second comparator, and the control terminal receives a sampling control signal, wherein the sampling control signal closes the sampling control switch at the end of a working cycle; a holding capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the second terminal of the sampling control switch, and the second terminal is connected to the reference ground.

9. The power converter according to claim 8, characterized in that The slope compensation circuit includes: a compensation capacitor having a first terminal and a second terminal, wherein the second terminal is grounded and the first terminal generates the slope compensation signal; The compensation capacitor control circuit controls the charge and discharge circuit to change the peak value of the slope compensation signal from the first slope peak value to the second slope peak value in a transient state.

10. The power converter according to claim 9, characterized in that The compensation capacitor control circuit includes: A first constant current source having an input end and an output end, wherein the input end is used to connect to a power supply voltage; a first switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the output terminal of the first current source, the control terminal is configured to receive the first control signal, and the second terminal is connected to the first terminal of the compensation capacitor; a second switch having a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the second terminal of the first switch, and the control terminal is configured to receive the second control signal; a second constant current source having an input terminal and an output terminal, wherein the input terminal is connected to the second terminal of the second switch, and the output terminal is coupled to a reference ground; The output current of the first constant current source and the output current of the second constant current source are set so that in a steady state, an initial value of the slope compensation signal at the beginning and a final value at the end of each cycle are equal.

11. The power converter according to claim 9, characterized in that The initial value recovery circuit operates at the end of each working cycle, so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

12. The power converter according to claim 11, wherein: The initial value recovery circuit acts at the end of each working cycle in a transient state, so that the slope compensation signal accelerates to approach the initial value.

13. The power converter according to claim 11, wherein: The initial value recovery circuit does not function at the end of each working cycle in a transient state.

14. The power converter according to claim 11, wherein: The initial value recovery circuit charges or discharges the compensation capacitor so that the slope compensation signal can be restored to a preset initial value at the end of each working cycle in a steady state.

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