Amplifier compensation circuit and method

Abstract

Various examples relate to a frequency-compensated amplifier circuit including a first multi-stage amplifier including a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node. A first feedback path between the first amplifier input node and the first amplifier output node includes a feedback resistor. A second feedback path between the first amplifier output node and the first amplifier intermediate node includes a first capacitor and a portion of the feedback resistor. A first switch circuit can be electrically coupled to the first capacitor and the feedback resistor. The first switch circuit can have a first state in which the first capacitor is coupled to a first tap point of the feedback resistor and the portion of the feedback resistor has a first value. The first switch circuit can also have a second state in which the first capacitor is coupled to a second tap point of the feedback resistor and the portion of the feedback resistor has a second value different from the first value.

Description

[0001] Claiming priority

[0002] This application claims priority to U.S. Provisional Application Serial No. 63 / 132298, filed on December 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This document is generally applicable to, but not limited to, amplifier circuits, especially amplifier circuits with variable bandwidth compensation. Background Technology

[0004] The ability of a voltage feedback amplifier to accurately amplify time-varying signals is limited by the amplifier's open-loop unity-gain bandwidth, or gain-bandwidth product (GBW), or slew rate. GBW is the product of the amplifier's closed-loop gain and its bandwidth, and is a constant. Therefore, an amplifier configured for relatively low gain will have a relatively large bandwidth, just as an amplifier configured for relatively high gain will have a relatively small bandwidth. The bandwidth decrease resulting from increasing gain degrades amplifier performance. In some amplifier circuits, the gain is configurable. The user can select the desired gain, for example, by changing the value of the gain resistor. However, in doing so, the user may also harmfully alter the amplifier's bandwidth. Attached Figure Description

[0005] In the accompanying drawings, which are not necessarily drawn to scale, similar numbers may describe similar parts in different views. Similar numbers with different letter suffixes may represent different instances of similar components. The accompanying drawings illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0006] Figure 1 This is a diagram illustrating an example of a bandwidth-compensated amplifier circuit that includes multiple stages of amplifiers.

[0007] Figure 2 It is shown Figure 1 A diagram showing an example of a small-signal model of an amplifier circuit.

[0008] Figure 3 It is shown Figure 1 and 2 A diagram illustrating an example arrangement of a multistage amplifier circuit, which communicates with control circuitry to provide a switch selection signal to a switching circuit to modify the bandwidth of the amplifier circuit.

[0009] Figure 4 This demonstrates that it can be executed by control circuitry to configure, for example... Figures 1-3 A flowchart illustrating an example of the bandwidth processing flow for amplifier circuits such as amplifier circuits.

[0010] Figure 5is a diagram illustrating one example of an instrumentation amplifier circuit utilizing bandwidth compensation as described herein.

[0011] Figure 6 is a diagram illustrating one example of an instrumentation amplifier circuit utilizing bandwidth compensation with an arrangement utilizing Figure 5 is a diagram illustrating one example of an instrumentation amplifier circuit utilizing bandwidth compensation with an arrangement utilizing

[0012] Figure 7 is a flowchart illustrating one example of a process flow that can be performed using an amplifier circuit coupled to receive a sensor input signal from a sensor.

[0013] Figure 8 two plots indicating bandwidth versus gain for an amplifier circuit, for example, are shown.

[0014] Figure 9 is a diagram illustrating one example of a bandwidth-compensated amplifier circuit including a buffer compensation capacitor.

[0015] Figure 10 is a diagram illustrating another example of a bandwidth-compensated amplifier circuit including a multi-stage amplifier.

[0016] Figure 11 is a block diagram illustrating a hardware architecture of a computing device in which a set or sequence of instructions can be executed to cause the machine to perform any one of the methods discussed herein. DETAILED DESCRIPTION

[0017] The various examples described herein are directed to frequency-compensated amplifier circuits and methods of using frequency-compensated amplifier circuits. An amplifier circuit includes a multi-stage amplifier including a first stage and a second stage. An input node of the multi-stage amplifier is at an input of the first stage. An output node of the multi-stage amplifier is at an output of the second stage. An intermediate node of the multi-stage amplifier is between the first stage and the second stage.

[0018] The multi-stage amplifier can be arranged with a first feedback path and a second feedback path. The first feedback path is between the output node and the input node and affects a closed loop gain of the multi-stage amplifier device and includes a feedback resistor electrically coupled between the input node and the output node. A gain resistor can be electrically coupled between the input node and ground. The closed loop gain of the multi-stage amplifier device can be based on values of the feedback resistor and the gain resistor, as described in greater detail herein.

[0019] The second feedback path, including the compensation capacitor and a portion of the feedback resistor, sets the bandwidth of the multi-stage amplifier, stabilizes the amplifier, and limits the loss of bandwidth at higher gains. Due to the Miller effect, the capacitance of the compensation capacitor will be larger than its physical capacitance by a factor related to the gain and feedback factor β of the amplifier stage between the intermediate node and the output node, as shown herein, in relation to the portion of the feedback resistor and the gain resistor in the second feedback path. By incorporating a portion of the feedback resistor into the second feedback path, the Miller effect becomes adaptive, depending on the closed loop gain of the multi-stage amplifier device, as described in more detail herein. As a result, the bandwidth of the multi-stage amplifier device also becomes adaptive, limiting the loss of bandwidth at higher closed loop gain values.

[0020] The second feedback path, including the compensation capacitor and a portion of the feedback resistor, sets the bandwidth of the multi-stage amplifier, stabilizes the amplifier, and limits the loss of bandwidth at higher gains. Due to the Miller effect, the capacitance of the compensation capacitor will be larger than its physical capacitance by a factor related to the gain and feedback factor β of the amplifier stage between the intermediate node and the output node, as shown herein, in relation to the portion of the feedback resistor and the gain resistor in the second feedback path. By incorporating a portion of the feedback resistor into the second feedback path, the Miller effect becomes adaptive, depending on the closed loop gain of the multi-stage amplifier device, as described in more detail herein. As a result, the bandwidth of the multi-stage amplifier device also becomes adaptive, limiting the loss of bandwidth at higher closed loop gain values.

[0021] Using a switch circuit to vary the portion of the feedback resistor incorporated into the second feedback path can allow for greater bandwidth expansion while maintaining stability. For example, the phase margin of the multi-stage amplifier depends on the closed loop gain of the multi-stage amplifier circuit and the impedance of the second feedback path including the compensation capacitor and the portion of the feedback resistor. Thus, if the portion of the feedback resistor included in the second feedback loop remains constant, the compensation capacitor can be selected to have a value large enough to produce a suitably large phase margin over all desired closed loop gains. However, a larger compensation capacitor can result in a decrease in bandwidth. Thus, making the portion of the feedback resistor in the second feedback loop configurable can allow for the use of a smaller compensation capacitor. In this way, instability (e.g., due to a low phase margin) caused by a lower compensation capacitor can be corrected by varying the portion of the feedback resistor in the second feedback loop. In this way, a lower compensation capacitor can be selected to achieve a higher bandwidth, while the portion of the feedback resistor included in the second feedback loop is varied to achieve suitable stability.

[0022] In various examples, the amplifier circuit can also include a control circuit configured to generate a switch selection signal that configures the switch circuit to optimize the multi-stage amplifier circuit for different closed loop gains. For example, the control circuit can receive an indication of the closed loop gain of the multi-stage amplifier circuit and / or other inputs described herein. The indication can be programmed by another component, communicated by another component, sensed or otherwise determined by the control circuit. Based on the closed loop gain, the control circuit selects an appropriate switch selection signal that will configure the switch circuit to switch a portion of the feedback resistance in the second feedback path, where the portion is optimized for the indicated closed loop gain. In some examples, the portion of the feedback resistance switched into the second feedback path is optimized to, for example, maximize the bandwidth of the amplifier circuit for a given gain while maintaining stability. In other examples, different states of the switch circuit can position taps of the feedback resistance to provide multiple different bandwidths (e.g., for a given gain).

[0023] In some examples, the amplifier circuit includes a control circuit configured to change a bandwidth of the multi-stage amplifier circuit during use by changing a portion of the feedback resistance included in the second feedback path. Consider an example where the multi-stage amplifier circuit is used to amplify a sensor signal generated by a sensor. It can be desirable to turn off the amplifier circuit between samples of the sensor signal. Thus, the multi-stage amplifier circuit is powered up to sample the sensor signal. During a first period of time after power up, the control circuit configures the switch circuit to produce a first wide bandwidth. During a second period of time, after a start-up transient has stabilized, the control circuit reconfigures the switch circuit to produce a second, narrower bandwidth for sampling the sensor signal. The wider bandwidth during the first period can result in the start-up transient stabilizing more quickly, which means that there can not be a long wait time after power up to sample the sensor signal. This can reduce power consumption because the amplifier circuit can not need to be powered up at a single bandwidth. The narrower bandwidth during the second period can also tend to reduce wideband noise during the measurement.

[0024] Figure 1is a diagram illustrating one example of a bandwidth-compensated amplifier circuit 100 including a multi-stage amplifier 102. The multi-stage amplifier 102 includes a stage 103 and a stage 105. The stage 103 includes an input node 116. In this example, the stage 103 is a differential stage, and the input node includes an inverting input of the stage 103 (indicated with a “-”) and a non-inverting input of the stage 103 (indicated with a “+”). An intermediate node 118 is between the stage 103 and the stage 105. The intermediate node in this example includes an output of the stage 103 and one or more inputs of the stage 105. In this example, the stage 105 is also a differential stage, and the intermediate node 118 includes the output of the stage 103, an inverting input of the stage 105 (indicated with a “-”), and a non-inverting input of the stage 105 (indicated with a “+”). An output node 120 includes an output of the stage 105.

[0025] The amplifier circuit 100 is arranged in a non-inverting configuration. An input signal 104 is provided at the inverting input of the stage 103 at the input node 116. The output of the stage 103 is provided to the inverting input of the stage 105. An output signal 106 is at the output of the stage 105. The non-inverting input of the stage 105 is electrically coupled to ground 122. A first feedback path 110 is shown between the output node 120 and the input node 116. In this example, the first feedback path 110 is electrically coupled between the stage 105 output and the stage 103 non-inverting input. The first feedback path 110 includes a feedback resistor R F , which in this example is indicated by two component parts R FA and R FB . In this example, the two parts of R F are arranged in series, such that the total feedback resistance is the sum of the resistances R FA and R FB . The first feedback path 110 provides a feedback signal derived from the output node 120 at the input node 116 based on the feedback resistor R F and the gain resistor R G .

[0026] The amplifier 100 also includes a second feedback path 112 electrically coupled between the output node 120 and the intermediate node 118. The second feedback path 112 includes a compensation capacitor Cc and a portion of a feedback resistor R F . The second feedback path 112 provides a feedback signal derived from the output node 120 at the intermediate node 118 based on the compensation capacitor Cc and the portion R F of the feedback resistor R G and the gain resistor R FA . For example, the feedback factor β of the second feedback path 112 can depend on the feedback resistor R F (including R FA and R FB ) and the portion R G of the gain resistor R FA .As shown in the following equation [9].

[0027] exist Figure 1 In the middle, the portion of the feedback resistor included in the second feedback path 112 is composed of R FA This indicates that the portion of the feedback resistor not included in the second feedback path is represented by R. FB Indicated. Switching circuit 114 is coupled to select feedback resistor R. F Part of R FA and R FB For example, the feedback resistor R F This can include tap point 108. (Partial R) FA It can be the feedback resistor R between output node 106 and switching circuit 114. F The part, and part R FB It can be a switching circuit 114 and a gain resistor R G The feedback resistance R between F part.

[0028] Switching circuit 114 can be configured to correspond to the feedback resistor R. F The different states of tap 108 at different positions. The different states of switch circuit 114 can be correlated with the feedback resistor R. F The location of tap 108 is related to the position of the tap. For example, the switching circuit 114 can be configured to position tap 108 closer to the gain resistor R. G The state to increase R FA Partial resistance and reduced R FB Partial resistance. Similarly, the switching circuit 114 can be configured to different states that position the tap point 108 closer to the output node 120 to reduce R. FA Partial resistance and increase R FB Partial resistance. The state of switch circuit 114 can be controlled by a selection signal (in... Figure 1 The selection is represented by SELECT, where the value of the switch selection signal determines the state of the switch circuit.

[0029] Switching circuit 114 and tap 108 can be implemented in any suitable manner. In some examples, switching circuit 114 is or includes a multiplexer or multiplexer. The multiplexer may include an output coupled to compensation capacitor Cc and electrically coupled to feedback resistor R. F Multiple inputs at different locations on the circuit. The value of the switch selection signal configures the multiplexer to electrically couple the compensation capacitor Cc to the feedback resistor R. F One of the locations is on the [top / bottom]. The location where the compensation capacitor Cc is electrically coupled is tap point 108, and it is at the feedback resistor R. F The position determination part R on FAand R FB The resistor. In another example, the switching circuit 114 includes electrical coupling to a compensation capacitor Cc and a feedback resistor R. F The sliding contact. Tap point 108 is where the sliding contact is electrically coupled to the feedback resistor R. F The location of the switches. In addition to or instead of these, other switch arrangements can be used.

[0030] The closed-loop gain of amplifier circuit 100 is determined by feedback resistor R. F and gain resistor R G The gain resistor R is determined. G Electrically coupled to the feedback resistor R F Between ground 122 and input 116. The signal feedback between output node 120 and input node 116 can be controlled by feedback resistor R. F (For example, R) FA +R FB ) and gain resistor R G To set, for example, as given in equation [1]:

[0031]

[0032] exist Figure 1 The closed-loop gain of amplifier circuit 100 in the non-inverting configuration shown can be given by equation [2]:

[0033]

[0034] In an example where amplifier circuit 100 is arranged in an inverting configuration (e.g., input 104 is provided at the input of the inverting input of stage 103), the gain will be given as in equation [3]:

[0035]

[0036] The second feedback path 112 can be used as an adaptive Miller compensation circuit, where the Miller effect changes the effective capacitance of the compensation capacitor Cc based on the closed-loop gain of the amplifier circuit 100. The effective capacitance of the compensation capacitor Cc can be adjusted by the factor given by the following equation [4]:

[0037]

[0038] The Miller effect alters the effective capacitance of the compensation capacitor Cc, potentially increasing the closed-loop 3dB bandwidth of amplifier circuit 100 by a factor given by the following equation [5]:

[0039]

[0040] In equation [5], A2 is the gain between the intermediate node 118 and the output node 120 of the multistage amplifier 102. β1 is the feedback coefficient of the first feedback path 110.

[0041] In some examples, the switching circuit 114 is configured to move along the gain resistor R G Locate tap point 108. In this example, the second feedback path 112 will include all feedback resistors R. F and part of the gain resistor R G The bandwidth extension of this arrangement will be given by equation [6], where R GA The gain resistor R is part of the second feedback path 112. G Part of R GB It is the gain resistor R G The portion outside the second feedback path 112. In some examples, a switching circuit similar to switch circuit 114 is used, R GA and R GB The value can be variable. Figure 5 and Figure 6 An example of this arrangement with switching circuits 530A and 530B is shown.

[0042]

[0043] Figure 2 It is shown Figure 1 A diagram illustrating an example of a small-signal model of amplifier circuit 100. Figure 2 In the example, the multistage amplifier 102 has a single-ended first stage gm1, but those skilled in the art will recognize that the discussion herein can also be applied to different first stages. Furthermore, any voltage feedback amplifier is configured using either non-inverting or inverting operation (e.g., the input amplifier of the three operational amplifier instrumentation amplifier described herein). A single output stage gm2 is shown. However, the present disclosure is not limited to any particular number of amplification and / or output stages. Because the output stage gm2 inverts the signal polarity, the inverting and non-inverting nodes of the first stage gm1 correspond to the inverting and non-inverting inputs of the feedback amplifier, respectively.

[0044] The benefits of the compensation technique according to this disclosure are analyzed below. For simplicity, this analysis assumes that the feedback amplifier does not drive large external capacitors. It also assumes that the amplifier's internal parasitic capacitances (such as...) Figure 2 The values ​​of C1 and C2 shown in the equations are much smaller than the compensation capacitor Cc, therefore consideration of the internal parasitic capacitances C1 and C2 is omitted. However, those skilled in the art will understand that these assumptions are used to explain the following concepts more clearly, and that this disclosure can be used with circuits driving large capacitors and / or amplifiers with non-negligible internal parasitic capacitances, or otherwise deviate from the assumptions inherent in the equations herein.

[0045] In Figure 2 the example arrangement, the loop gain at direct current (DC) is given by the product of A1, A2 and β, where A1 is the gain between the input node 116 and the intermediate node 118. The values of A1, A2 and β are given by the following equations [7], [8] and [9]:

[0046] A1 = g m1 r o1 [7]

[0047] A2 = g m2 r o2 [8]

[0048]

[0049] In equations [7] and [8], g m1 and g m2 are the transconductances of the gm1 and gm2 stages, while r o1 and r o2 are the output impedances of the gm1 and gm2 stages (denoted by RO1 and RO2 in Figure 2 ). β2 is the feedback coefficient of the feedback path 112. Due to the Miller effect, the equivalent capacitance generated by the compensation capacitor Cc is greater than Cc and is given by equation

[10] :

[0050] C eq = (1 + k) C c

[10]

[0051] In equation

[10] , k is the voltage gain across the compensation capacitor Cc.

[0052] The Miller effect causes the capacitance at the first terminal of a capacitor to appear larger than it actually is if the voltage at the second terminal varies in the opposite direction to the voltage at the first terminal. Depending on the value of the equivalent capacitance, the transfer function of the loop gain has a dominant pole f o and a unity gain bandwidth f u given by equations

[11] and

[12] :

[0053]

[0054] f u = A1A2β1·

[14]

[0055] Substituting this value of k into equations

[11] and

[13] shows that the dominant pole f o and the closed loop 3dB bandwidth f c are given by equations

[15] and

[16] :

[0056]

[0057]

[0058] Therefore, the additional dependence on the feedback coefficient β increases the bandwidth of the amplifier circuit 100 compared to the circuit that omits the second feedback path 112. Furthermore, as given in equation [8] above, changing the feedback resistor R included in the second feedback path... F The resistance of some parts also changes the bandwidth of amplifier circuit 100.

[0059] Figure 1 The amplifier circuit 100 in the illustrated arrangement can provide certain benefits regarding bandwidth and stability. For example, a lower value for the compensation capacitor Cc can correspond to a higher bandwidth value. Consider an example where the feedback resistor R... F Part of R FA and R FB It is fixed (e.g., switching circuit 114 is omitted) and the gain is programmable (e.g., R...). G (This is optional and / or can be modified via a switching circuit). In this arrangement, the compensation capacitor Cc can be selected to a sufficiently large value to stabilize the amplifier circuit 100 at the level determined by R. G The highest expected gain is set. However, recalling equations

[15] and

[16] above, a higher value of the compensation capacitor Cc corresponds to a lower bandwidth. Therefore, the stability trade-off at high gain may be a lower bandwidth at low gain.

[0060] use Figure 1 The arrangement is modified by switching circuit 114 to change the feedback resistor R. FA and R FB The value of provides another way to change the bandwidth of the amplifier circuit (e.g., besides changing the compensation capacitor Cc). This allows for the selection of a smaller Cc value. At high gain, this can be achieved by selecting the feedback resistor portion R. FA and R FB The value of Cc is used to achieve stability, thereby reducing bandwidth for a given lower value of Cc. At lower gain, a lower Cc value may allow for a wider bandwidth.

[0061] Figure 3 It is shown Figure 1 and Figure 2 Figure 300 shows an example arrangement of a multi-stage amplifier circuit 100, which communicates with a control circuit 302 to provide a switch selection signal (SELECT) to a switching circuit 114 to modify the bandwidth of the amplifier circuit 100. Figure 3 In the example, switch circuit 114 is a multiplexer, and the switch selection signal is the input of the multiplexer that selects the input of the multiplexer. The multiplexer input determines the feedback resistor R.F the position of the tap point 108 on the resistor R FA and R FB values. However, any suitable switch arrangement or mechanism for setting R FA and R FB values can be used.

[0062] The control circuit 302 shows two example inputs, a gain measurement input 304, a gain input 306. The control circuit 302 can include any combination of the inputs 304, 306 or other inputs not shown in FIG. 3. Figure 3

[0063] The gain measurement input 304 receives a measurement of gain (e.g., the closed loop gain of the amplifier circuit 100). The measurement of gain can be provided by another component, such as a processor or sensor, and / or measured by the control circuit. For example, the gain measurement input 304 can be or based on a voltage and / or current at the amplifier circuit 100. The control circuit 302 can measure the voltage or other value in the amplifier circuit 100 to derive the corresponding gain.

[0064] The gain input 306 receives a signal indicative of the gain of the amplifier circuit 100. For example, the amplifier circuit 100 can have a programmable gain. The gain input 306 can receive an indication of the gain to be programmed to the amplifier circuit 100. In some examples, the control circuit 302 is configured to also set the gain of the amplifier circuit 100, e.g., as described herein with respect to Figure 5 and Figure 6 .

[0065] Another example way of providing inputs to the control circuit 302 is through pin binding. Pin binding can involve connecting one or more pins of an integrated circuit that includes the control circuit 302 to a particular voltage, such as ground or a supply voltage Vcc. The pin binding configuration indicates to the control circuit 302 a desired bandwidth or gain. In some examples, grounding a specified pin or pins can indicate a low bandwidth with corresponding values for the feedback resistance portions R FA and R FB . Connecting a specified pin or pins to the supply voltage Vcc can indicate a higher bandwidth, again with corresponding values for the feedback resistance portions R FA and R FB .

[0066] ​The control circuit 302 can include any suitable hardware or software for determining the switch selection signals for the switch circuit 114 based on one or more of the inputs 304, 306. For example, the control circuit 302 can include one or more logic gates, flip-flops, or other logic components to convert one or more of the inputs 304, 306 into corresponding switch selection signals to the switch circuit 114.

[0067] In some examples, the control circuit 302 also provides a signal to a shutdown or sleep input (SD) 310 of the amplifier circuit 100. The SD input 310, when asserted, can cause the amplifier circuit to enter a sleep or shutdown mode, thereby reducing power consumption. In this way, the control circuit 302 can selectively turn the amplifier circuit 100 off or on, for example, as described herein with respect to the process flow of Figure 7 It will be understood that the logic of the SD input 310 can be arranged in any suitable way. In some examples, providing a“high” voltage to the SD input 310 causes the amplifier circuit 100 to enter a shutdown state, while providing a“low” voltage causes the amplifier circuit 100 to enter a powered on or operational state. In other examples, providing a“low” voltage to the SD input 310 causes the amplifier circuit 100 to enter a shutdown state, while providing a“high” voltage causes the amplifier circuit 100 to enter a powered on or operational state. Other arrangements are also contemplated.

[0068] Figure 4 is a flowchart illustrating one example of a process flow 400 that can be performed by the control circuit 302 to configure the bandwidth of an amplifier circuit, such as the amplifier circuit 100 of Figures 1-3 At operation 402, the control circuit 302 receives a gain value indicative of a gain of the amplifier circuit 100. The gain value can be measured (e.g., the gain measurement input 304) or received via the gain input 306 as described herein.

[0069] At operation 404, the control circuit 302 derives a bandwidth condition for the gain value indicated at operation 402. The bandwidth condition can be indicative of a desired bandwidth of the amplifier circuit. In some examples, the bandwidth condition is or includes a value of a fraction of the feedback resistances R FA and R FB In other examples, the bandwidth condition is or includes a value of the switch selection signals provided to the switch circuit 114. In some examples, the control circuit 302 determines a bandwidth condition that is optimized for the selected gain. For example, the control circuit 302 can be configured to configure the amplifier circuit 100 for the highest bandwidth that provides suitable stability for a given gain. At operation 406, the control circuit 302 provides the switch selection signals to the switch circuit 114 to achieve the bandwidth condition determined at operation 404.

[0070] Figure 5is a diagram illustrating one example of an instrumentation amplifier circuit 500 that utilizes bandwidth compensation as described herein. The amplifier circuit 500 includes a first multi-stage amplifier 502A and a second multi-stage amplifier 502B. The amplifiers 502A, 502B include respective stages 503A, 503B and stages 505A, 505B. The stages 503A, 503B include input nodes 516A, 516B and are differential stages that include a non-inverting input, an inverting input, a non-inverting output, and an inverting output. Intermediate nodes 518A, 518B are located between the stages 503A, 503B and the stages 505A, 505B. In this example, the non-inverting outputs of the stages 503A, 503B are electrically coupled to the non-inverting inputs of the stages 505A, 505B and grounded via respective capacitors Cg. The inverting outputs of the stages 503A, 503B are electrically coupled to the inverting inputs of the stages 505A, 505B. The outputs of the respective stages 503A, 503B are at output nodes 520A, 520B.

[0071] The amplifiers 502A, 502B are coupled with first feedback paths 510A, 510B and second feedback paths 512A, 512B, respectively. As shown, the first feedback paths 510A, 510B are located between the respective output nodes 520A, 520B and the respective input nodes 516A, 516B. In this example, the first feedback paths 510A, 510B are between the outputs of the stages 505A, 505B and the respective inverting inputs of the stages 503A, 503B. The two first feedback paths 510A include respective feedback resistors R F , each of which includes two portions, R FA , and a second portion R FB . In this example, the two portions of R F are arranged in series such that the total feedback resistance R F is the sum of the resistances R FA and R FB .

[0072] The second feedback paths 512A, 512B are electrically coupled between the respective output nodes 520A, 520B and the respective intermediate nodes 518A, 518B. The second feedback paths 512A, 512B include respective compensation capacitors Cc and portions R F of feedback resistors R FA . Switching circuits 514A, 514B set the values of the portions R F and R F of the feedback resistors R FA by positioning respective tap points 508A, 508B on the feedback resistors R FB in response to switch selection signals (indicated by “S” in Figure 5 .

[0073] The closed-loop gain of amplifiers 502A and 502B can be determined by the gain resistor R. G and feedback resistor R FA and R FB Confirmed, as described in this article. As shown in the figure, the gain resistor R... G Electrical coupling at each feedback resistor R F In some examples, circuit 500 can be arranged in a chip or other package, allowing the designer to add an external gain resistor R. G .exist Figure 5 In this example, additional gain switching circuits 530A and 530B are provided to selectively switch the gain resistor R. G A portion of the signal is coupled into the corresponding first feedback paths 510A, 510B to affect the closed-loop gain of the amplifier circuit 500. Gain switching circuits 530A, 530B can be implemented in any suitable manner, for example, as described herein with respect to switching circuits 114, 514A, 514B. The selection signal for the switching circuits can be provided externally and / or determined by the control circuitry described herein.

[0074] exist Figure 5 In the example, amplifiers 502A and 502B together form the first stage. The gain of the first stage is given by the following formula

[17] :

[0075]

[0076] In equation

[17] , R F It is the feedback resistor part R FA and R FB The sum of . R Gactual It is the gain resistor R G Part of it is switched to the corresponding feedback path 510A, 510B via switching circuits 530A, 530B.

[0077] The additional amplifier 532 provides the output stage. For example, the closed-loop gain of the output stage can be determined by resistors R1, R2, and R3, as shown in the following formula

[18] :

[0078]

[0079] In some examples, R1 can be equal to R2, such that the gain of the second stage, including amplifier 532, is consistent with the differential gain of the first stage given by equation

[17] .

[0080] In some examples, Figure 5The arrangement can omit the output stage, which includes amplifier 532 and resistors R1 and R2. Instead, output nodes 520A and 520B can be electrically coupled to provide the outputs of each multistage amplifier 502A and 502B to one or more other components. For example, output nodes 502A and 502B can be electrically coupled to an analog-to-digital converter (ADC) or one or more other suitable components.

[0081] Figure 6 It shows the use of Figure 5 A diagram of an example of a bandwidth-compensated instrumentation amplifier circuit 600. Figure 6 The inverting input (V) coupled to amplifier circuit 600 is also shown. IN+ ) and non-inverting input (V IN- Example sensor 604. Sensor 604 can be any suitable sensor, including, for example, a temperature sensor, an optical sensor, a Wheatstone bridge sensor, etc. In some examples, sensor 604 measures bioelectric potential. For example, sensor 604 may include electrodes attached to a human or other type of animal body. The input to amplifier circuit 600 can be an electrode or derived from an electrode.

[0082] In addition, Figure 6 In the example, the switch selection signals of switching circuits 514A, 514B and 530A, 530B are coupled to control circuit 602. Control circuit 602 can be configured similarly to... Figure 3 The control circuit 602 is arranged in a manner similar to control circuit 302. Control circuit 602 can be configured to provide switch selection signals to switch circuits 514A, 514B to determine the feedback resistor R included in the respective second feedback paths 512A, 512B. F Part of R FA and R FB The control circuit 602 may also be coupled to provide switch selection signals to the switching circuits 530A, 530B to set the gain of the first stage including amplifiers 502A, 502B. In some examples, the control circuit 602 also receives a power supply voltage 606, which can be selectively supplied to the amplifier circuit 600 to power on or off the amplifier circuit 600.

[0083] Control circuitry 602 includes one or more inputs (INPUT) for instructing control circuitry 602 how to set the gain and / or bandwidth of the instrumentation amplifier device. In some examples, the inputs include an indication of the desired gain. Control circuitry 602 can determine the switch selection signals for switching circuits 530A, 530B based on the INPUT to set the gain of amplifier circuitry 600. Control circuitry can also determine the switch selection signals for switching circuits 514A, 514B based on the desired gain, as described herein, to set the bandwidth of amplifier circuitry 600.

[0084] Figure 7 is a flowchart illustrating one example of a process flow 700 that can be performed using an amplifier circuit coupled to receive a sensor input signal from a sensor. Any of the amplifier circuits described herein can be used to perform process flow 700. Process flow 700 can begin with an amplifier circuit in a powered-off state. In some examples, a supply voltage Vcc is removed from the amplifier when the amplifier is in the powered-off state. In other examples, the amplifier circuit supports a shutdown or sleep state in which a supply voltage is provided, but power consumption is reduced. As described herein, such a state can be induced by providing an appropriate signal at a shutdown or sleep input of the amplifier circuit, such as the SD input 310 of the Figure 3

[0085] At operation 702, the control circuit powers up the amplifier circuit. In examples in which the amplifier circuit is shut down by removal of a supply voltage, powering up the amplifier circuit can include applying the supply voltage. In examples in which the control circuit shuts down the amplifier circuit by providing a signal at a shutdown or sleep input, powering up the amplifier circuit can include providing a signal at the shutdown or sleep input to cause the amplifier circuit to enter a powered-up or active mode.

[0086] When powering up the amplifier circuit, the sensor, amplifier, capacitance, inductance, or other circuit components can tend to produce certain transient signals. In certain examples, the output of the amplifier circuit can not provide an accurate representation of the sensor when transients are present. At operation 704, the control circuit configures the amplifier to have a first bandwidth. The control circuit can modify the bandwidth of the amplifier circuit, for example, as described herein. The first bandwidth can be a wide bandwidth selected to allow transient signals to decay quickly. In some examples, the first bandwidth can be optimized to minimize the settling time of transients. For example, the first bandwidth can be too wide to optimize for measuring the sensor output signal of the sensor. The first bandwidth can be achieved, for example, by sacrificing the phase margin of the amplifier circuit. In some examples, the order of operations 702 and 704 can be exchanged. The control circuit can configure the amplifier to have the first bandwidth before the amplifier circuit is powered up. In some examples, the first bandwidth can be a default bandwidth that the control circuit configures upon power up.

[0087] At operation 706, the control circuit can wait. The amount of time that the circuit waits can be based on the expected decay time of the transient signals. In some examples, the control circuit monitors the output of the amplifier circuit and waits until the output no longer shows artifacts caused by transients.

[0088] ​In operation 708, the control circuit configures the bandwidth of the amplifier circuit to a second bandwidth. The second bandwidth can be less than the first bandwidth and can optimize the bandwidth and noise of the circuitry used with the sensor. In operation 710, the amplifier circuit receives the sensor signal as input and provides an output indicating the amplified sensor signal. In some examples, the output of the amplifier circuit is sampled and stored or otherwise processed. In operation 712, the control circuit powers off the amplifier circuit. This may include, for example, removing power from the amplifier circuit and / or providing an appropriate signal at a shutdown or sleep input, as described herein. The power-off at operation 712 can occur after the output of the amplifier circuit has been sampled.

[0089] It should be understood that process flow 700 or parts thereof can be repeated. For example, control circuitry can execute process flow 700 at suitable periodic intervals to capture periodic readings from the sensor. Any suitable time period can be used, including one sample per millisecond, one sample per second, one sample per five minutes, one sample per hour, etc. In other examples, process flow 700 can be executed as needed. For example, amplifier circuitry can be used in conjunction with a process flow that requires sampling of the sensor when a condition occurs. When the condition occurs, the control circuitry executes process flow 700. In some examples, the control circuitry tests the condition and executes process flow 700 when the condition is detected. In other examples, the condition is tested by a separate processor or computing device hardware architecture, such as regarding... Figure 10 The architecture described is 1000. When a condition is detected, a separate processor instructs the control circuitry to execute process flow 700.

[0090] Because the first bandwidth is wider than the second bandwidth, operating the amplifier circuit according to process 700 can shorten the total power-on time of the amplifier circuit. For example, if the amplifier circuit operates only at the second bandwidth, the circuit may need to be powered on for a longer period to allow transients to stabilize before the amplifier circuit's output is sampled. Furthermore, in some examples, relative to... Figure 7 Operating the amplifier in the described manner allows for capturing the sensor signal with a narrower bandwidth, which tends to reduce high bandwidth noise. For example, without the bandwidth variation described in process flow 700, designers can be prompted to select the amplifier circuit bandwidth based on a trade-off between transient settling time and high bandwidth noise in the sensor signal. Using process flow 700 allows the circuit to select a bandwidth suitable for the low settling time during power-up (operations 704 and 706) and different bandwidths suitable for low-noise sensor operation (operations 708 and 710).

[0091] Figure 8 Two graphs, 802 and 804, are shown, indicating, for example, the bandwidth versus gain of an amplifier circuit. Graph 802 shows the relationship between bandwidth and gain. Figure 5circuit 500 is similar but arranged with the bandwidth and gain of the amplifier circuit electrically coupled to the compensation capacitor of the output stage 120. In this arrangement, the feedback resistor R F is not in the second feedback path. The second curve 804 illustrates the bandwidth and gain of the amplifier circuit 500 of Figure 5 . As shown, the bandwidth and gain of the curve 802 follows the conventional arrangement with constant GBW. The modification includes a portion of the feedback resistor R F in the second feedback path, as shown by the curve 804, optimizes the bandwidth and stability at different gains. As shown, Figure 8 compared to the comparative amplifier circuit (curve 802), the arrangement of Figure 5 provides superior bandwidth (curve 804).

[0092] Figure 9 is a diagram illustrating one example of a bandwidth-compensated amplifier circuit 900 including a buffered compensation capacitor. The amplifier circuit 900 is arranged in a similar manner to the amplifier circuit 100 of Figure 1 . In the example of Figure 9 , a buffer 902 is located in the second feedback path 912. The buffer 902 can be constructed of any suitable material or component. In some examples, the buffer 902 is a unity-gain buffer amplifier, including an operational amplifier with negative feedback or other suitable differential amplifier. The buffer 902 is directed from the output node 120 to the intermediate node 118. In this arrangement, the buffer 902 can prevent any feedforward current between the intermediate node 118 and the output node 120. This can further improve the settling time of the amplifier circuit 900 when powered on.

[0093] Figure 10 is a diagram illustrating another example of a bandwidth-compensated amplifier circuit 1000 including a multi-stage amplifier. Figure 10 The example bandwidth-compensated amplifier circuit 1000 of Figure 1 may be similar to the bandwidth-compensated amplifier circuit 100 of Figure 10 . However, Figure 1 the circuit 1000 of F includes a second feedback path 1012 that includes a portion R GA of the feedback resistor R GA and the gain resistor. A switch circuit 1014 can be configured to states in which the compensation capacitor is electrically coupled to a tap point 1008 at the gain resistor, such that the gain resistor is divided into R GA and R GB . In some examples, the switch circuit 1014 can have one or more states in which the compensation capacitor is electrically coupled to a tap point on the gain resistor, such as the tap point 1008, and one or more states in which the compensation capacitor is electrically coupled to a tap point on the feedback resistor, such as the tap point 1010.the tap point 108.

[0094] Figure 11 is a block diagram illustrating a computing device hardware architecture 1100 in which a set or sequence of instructions can be executed to cause a machine to perform any one of the methods discussed herein. For example, the architecture 1100 can describe one or more processors or other computing devices that can be used to implement the control circuit 302, 602 or to perform the process flows 400 and 700 described herein. The architecture 1100 can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the architecture 1100 can operate in the capacity of a server or a client machine in server-client network environments, or it can act as a peer machine in peer-to-peer (or distributed) network environments. The architecture 1100 can be implemented in an embedded system, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, a network switch, a network bridge, or any machine capable of executing a set or sequence of instructions that specify actions to be taken by that machine.

[0095] The example architecture 1100 includes a processor unit 1102 having at least one processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU) or both, a processor core, a computational node). The architecture 1100 also can include a main memory 1104 and a static memory 1106, which communicate with each other via a link 1108 (e.g., a bus). The architecture 1100 can further include a video display unit 1110, an input device 1112 (e.g., a keyboard), and a UI navigation device 1114 (e.g., a mouse). In some examples, the video display unit 1110, input device 1112, and UI navigation device 1114 are incorporated into a touch screen display. The architecture 1100 can additionally include a storage device 1116 (e.g., a drive unit), a signal generation device 1118 (e.g., a speaker), a network interface device 1120, and one or more sensors (not shown), such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor.

[0096] In some examples, the processor unit 1102 or another suitable hardware component can support hardware interrupts. In response to a hardware interrupt, the processor unit 1102 can pause its processing and execute an ISR, e.g., as described herein.

[0097] The storage device 1116 includes a machine-readable medium 1122 on which is stored one or more sets of data structures and instructions 1124 (e.g., software) embodying or utilized by any one or more of the methodologies or functions described herein. The instructions 1124 can also reside, completely or at least partially, within the main memory 1104, within static memory 1106, and / or within the processing unit 1102 during execution thereof by the architecture 1100, the main memory 1104, the static memory 1106, and the processing unit 1102 also constituting machine-readable media.

[0098] Executable instructions and machine-storage media

[0099] The various memories (i.e., 1104, 1106, and / or the memory of the processing unit 1102) and / or the storage device 1116 can store one or more sets of instructions and data structures (e.g., the instructions 1124) embodying or utilized by any one or more of the methodologies or functions described herein. These instructions, when executed by the processing unit 1102, cause various operations to implement the disclosed examples.

[0100] As used herein, the terms "machine-storage medium," "device-storage medium," and "computer-storage medium" (collectively referred to as "machine-storage media") mean the same thing and can be used interchangeably. The terms refer to a single or multiple storage devices and / or media (e.g., a centralized or distributed database, and / or associated caches and servers) that store executable instructions and / or data structures. Thus, the terms "machine-storage media," "computer- storage media," and "device-storage media" should be understood to include, be carious to, single or multiple storage devices and storage media such as machine storage media, optical and magnetic media, including propagation media. As a non-limiting example, examples of machine-storage media include non-volatile memory, such as semiconductor memory devices, e.g., Erasable Programmable Read-Only Memories (EPROM), Electrically Erasable Programmable Read-Only Memories (EEPROM), and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks. The terms "machine-storage media," "computer-storage media," and "device-storage media" specifically exclude carrier waves, modulated data signals, and other such media, at least some of which are covered under the term "signal medium" as discussed below.

[0101] Signal medium

[0102] The term "signal medium" or "transmission medium" shall be taken to include any form of modulated data signal, carrier wave, and so forth. The term "modulated data signal" means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal.

[0103] Computer-readable medium

[0104] The terms "machine-readable medium," "computer-readable medium," and "device readable medium" mean the same thing and are used interchangeably in this disclosure. The terms are defined to include a machine-storage medium and a carrier wave. Accordingly, the terms include both storage devices / media and carrier waves.

[0105] The instructions 1124 can further be transmitted or received using a transmission medium via the network interface device 1120 utilizing any one of a number of well-known transfer protocols (e.g., hypertext transfer protocol (HTTP)). Examples of communication networks include a local area network (LAN), a wide area network (WAN), the Internet, mobile telephone networks, plain old telephone service (POTS) networks, and wireless data networks (e.g., Wi-Fi, 3G, 4G long term evolution (LTE) / LTE-A, 5G, or WiMAX networks).

[0106] Various notes and examples

[0107] Example 1 is a frequency-compensated amplifier circuit, comprising: a first multi-stage amplifier including a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node; a first feedback path between the first amplifier input node and the first amplifier output node, the first feedback path including a feedback resistor; a gain resistor electrically coupled with the feedback resistor; a second feedback path between the first amplifier intermediate node and an amplifier output node, the second feedback path including a first capacitor and a resistive portion; and a first switch circuit electrically coupled to the first capacitor and the feedback resistor, the first switch circuit having a plurality of states including: a first state in which the first capacitor is coupled to a first tap point and the resistive portion has a first value; and a second state in which the first capacitor is coupled to a second tap point and the resistive portion has a second value different from the first value.

[0108] In Example 2, the subject matter of Example 1 optionally includes a control circuit configured to selectively set the first switch circuit to the first state or the second state.

[0109] In Example 3, the subject matter of Example 2 optionally includes the control circuit configured to use an indication of a gain of the amplifier circuit to select the first state or the second state of the first switch circuit.

[0110] In Example 4, the subject matter of any one or more of Examples 1-3 optionally includes a gain switch circuit electrically coupled to the first amplifier input node and the gain resistance, the gain switch circuit having a first state in which the first amplifier input node is coupled to a first tap point of the gain resistance and a second state in which the first amplifier input node is coupled to a second tap point of the gain resistance different from the first tap point.

[0111] In Example 5, the subject matter of any one or more of Examples 1-4 optionally includes a second multi-stage amplifier including a second amplifier input node, a second amplifier output node, and a second amplifier intermediate node, a third feedback path between the second amplifier input node and the second amplifier output node, the third feedback path including a second feedback resistance, a fourth feedback path between the second amplifier output node and the second amplifier intermediate node, the fourth feedback path including a second capacitor and a second resistance portion, a second switch circuit electrically coupled to the second capacitor and the second feedback resistance, the second switch circuit having a first state in which the second capacitor is coupled to a third tap point and the second resistance portion has a third value, the second switch circuit further having a second state in which the second capacitor is coupled to a fourth tap point and the second resistance portion has a fourth value different from the third value, and a differential amplifier, the first amplifier output node electrically coupled to a non-inverting input of the differential amplifier and the second amplifier output node electrically coupled to an inverting input of the differential amplifier.

[0112] In Example 6, the subject matter of Example 5 optionally includes the gain resistance electrically coupled between the feedback resistance and the second feedback resistance.

[0113] In Example 7, the subject matter of any one or more of Examples 1-6 optionally includes a control circuit configured to perform operations comprising: powering on the amplifier circuit; configuring the first switch circuit to a first state to set a bandwidth of the amplifier circuit to a first bandwidth value; and after waiting for a first time period, configuring the first switch circuit to a second state to set the bandwidth of the amplifier circuit to a second bandwidth value less than the first bandwidth value.

[0114] In Example 8, the subject matter of Example 7 optionally includes the operations further comprising powering off the amplifier circuit after waiting for a second time period.

[0115] In Example 9, the subject matter of any one or more of Examples 1-8 optionally includes the input node of the first multi-stage amplifier electrically coupled to a sensor.

[0116] In Example 10, the subject matter of any one or more of Examples 1-9 optionally include that the first amplifier intermediate node includes a second stage non-inverting input and a second stage inverting input, the second feedback path being between the output node and the first stage inverting input.

[0117] In Example 11, the subject matter of any one or more of Examples 1-10 optionally include that the second feedback path further includes a buffer directed from the output node to the intermediate node.

[0118] In Example 12, the subject matter of any one or more of Examples 1-11 optionally include that the first tap point is a tap point of the feedback resistance.

[0119] In Example 13, the subject matter of any one or more of Examples 1-12 optionally include that the second tap point is a tap point of the gain resistance.

[0120] Example 14 is a method of operating an amplifier, the amplifier including a first feedback path, the first feedback path including: a feedback resistance electrically coupled between an amplifier input node and an amplifier output node; a gain resistance electrically connected with the feedback resistance; and a second feedback path between a first amplifier intermediate node and the amplifier output node, the second feedback path including a capacitor and a resistance portion, the method including: configuring a first switch circuit from a first state in which the capacitor is coupled to a first tap point and the resistance portion has a first value to a second state in which the capacitor is coupled to a second tap point and the resistance portion has a second value different from the first value; providing a first feedback signal derived from the amplifier output node to the amplifier input node via the first feedback path; and providing a second feedback signal derived from the amplifier output node to the amplifier intermediate node via the second feedback path.

[0121] In Example 15, the subject matter of Example 14 optionally includes using a gain of the amplifier to select a first portion of the feedback resistance to be coupled to the second feedback path.

[0122] In Example 16, the subject matter of any one or more of Examples 14-15 optionally include configuring a gain switch circuit to switch the first portion of the gain resistance to the first feedback path.

[0123] In Example 17, the subject matter of any one or more of Examples 14-16 optionally include powering on the amplifier; and after waiting a first time period, configuring the first switch circuit to electrically couple a second portion of the feedback resistance into the second feedback path, the second portion of the feedback resistance being less than the first portion of the feedback resistance.

[0124] In example 18, the subject matter of example 17 optionally includes receiving a sensor input signal from a sensor at the amplifier input node; and powering off the amplifier upon receiving the sensor input signal.

[0125] In example 19, the subject matter of any one or more of examples 17-18 optionally includes that the second node is a first amplifier output node.

[0126] Example 20 is a frequency-compensated amplifier system, comprising: a first multi-stage amplifier including a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node; a first feedback path between the first amplifier input node and the first amplifier output node, the first feedback path including a feedback resistor; a second feedback path between the first amplifier output node and the first amplifier intermediate node, the second feedback path including a first capacitor and a resistor portion; means for modifying the resistor portion of the second feedback path; means for providing a first feedback signal derived from the amplifier output node to the amplifier input node via the first feedback path; and means for providing a second feedback signal derived from the amplifier output node to the amplifier intermediate node via the second feedback path.

[0127] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the application can be practiced. These embodiments are also referred to as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0128] To the extent usage of terms does not naturally correspond with the way those terms are used herein, the usage herein shall control.

[0129] In this document, the terms“a” or“an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of“at least one” or“one or more.” In this document, the term“or” is used to refer to a nonexclusive or, such that“A or B” includes“A but not B,”“B but not A,” and“A and B,” unless otherwise indicated. In this document, the terms“including” and“comprising” are used as the plain-English equivalents of the respective terms“including” and“comprising.” Also, in the following claims, the terms“including” and“comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms“first,”“second,”“third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0130] Unless context dictates otherwise, geometric terms, such as“parallel,”“perpendicular,”“circular,” or“square,” are not intended to require absolute mathematical precision. Rather, such geometric terms allow for variations due to manufacturing or equivalent functionality. For example, if an element is described as“circular” or“substantially circular,” this description is still encompassed by a component that is not a perfect circle (e.g., a component that is slightly oval or polygonal).

[0131] The term“circuitry” can include specialized hardware components, general-purpose microprocessors, digital signal processors, or other processor circuits that can be structured alone or in combination, like using firmware or software.

[0132] Any one or more of the techniques (e.g., methodologies) discussed herein can be performed on a machine. In various embodiments, the machine can operate as a standalone device or can be connected (e.g., networked) to other machines. In a networked deployment, the machine can operate in the capacity of a server machine, a client machine, or both in server-client network environments. In an example, the machine can act as a peer machine in peer-to-peer (P2P) (or other distributed) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a network router, switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term“machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein, such as cloud computing, software as a service (SaaS), other computer cluster configurations.

[0133] As described herein, examples can include, or can operate by, logic or a number of components, or mechanisms. A circuit set is a collection of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). A circuit set member can be an individual circuit implementing the circuit set or a collection of circuits implementing the circuit set. Members of the circuit set can be fixed, variably connected, or dynamically connected. A circuit set includes members that can operate independently, or collectively, to manipulate information. In an example, hardware of the circuit set can be immutably designed to carry out a specific operation (e.g., hardwired). In an example, the hardware of the circuit set can include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) including a physical storage medium of the computer-readable medium. In an example, the computer-readable medium of the circuit set can be a machine-readable storage medium (e.g., magnetic) having stored, non-transitory instructions, with the execution units of the hardware of the circuit set acting to communicate with the computer-readable medium by varying the connection, e.g., transistors, of the physical components. In an example, the computer-readable medium of the circuit set can be a machine-readable storage medium (e.g., optical) having stored, non-transitory instructions, with the execution units of the hardware of the circuit set acting to communicate with the computer-readable medium by varying the connection, e.g., transistors, of the physical components. In an example, a machine -readable storage medium of a circuit set can be a physical storage medium that is non-transitory, with the computer-readable medium of the circuit set acting to communicate with the computer-readable medium by varying the magnetic storage of the physical storage medium. In an example, the computer-readable medium of the circuit set can be a machine-readable storage medium (e.g., solid state memory) having stored, non-transitory instructions, with the execution units of the hardware of the circuit set acting to communicate with the computer-readable medium by varying the connection, e.g., transistors, of the physical components. Thus, in an example, a circuit set component can include means for performing any of the operations described herein. Accordingly, all combinations of circuit set components described herein can be implemented.

[0134] Particular implementations of the system and method described herein can involve the use of machines (e.g., computer systems) that include hardware processors (e.g., central processing units (CPUs), graphics processing units (GPUs), hardware processor cores, or any combination thereof), main memory, and static memory, some or all of which can communicate with one another over an interlink (e.g., bus). The machines can also include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, the display unit, input device, and UI navigation device can be a touch screen display. The machines can additionally include a storage device (e.g., drive unit), a signal generation device (e.g., a speaker), a network interface device, and one or more sensors, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machines can include an output controller, such as a serial (e.g., universal serial bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

[0135] The storage device can include a machine-readable medium on which is stored one or more sets of instructions or data structures (e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions can also reside, completely or at least partially, within the main memory, static memory, or hardware processor during execution thereof by the machine. In one example, one or any combination of the hardware processor, the main memory, the static memory, or the storage device can constitute machine-readable media.

[0136] While the machine-readable medium can include a single medium, the term“machine-readable medium” can include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) configured to store the one or more instructions.

[0137] The term“machine-readable medium” can include any medium that is capable of storing, encoding, or carrying instructions for execution by a machine and that cause the machine to perform any one or more of the techniques of the present disclosure, or that is capable of storing, encoding or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples can include solid-state memories, and optical and magnetic media. In one example, a massed machine-readable medium includes a machine-readable medium with a plurality of particles having invariant (e.g., rest) mass. Accordingly, massed machine-readable media are not transitory propagating signals. Specific examples of massed machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., Electrically Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0138] The instructions can further be transmitted or received using a transmission medium via the network interface device utilizing any one of a number of transfer protocols (e.g., frame relay, internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks can include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), mobile telephone networks (e.g., cellular networks), Plain Old Telephone (POTS) networks, and wireless data networks (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards known as Wi-Fi®, IEEE 802.16 family of standards known as WiMax®), and IEEE 802.15.4 family of standards, a Long Term Evolution (LTE) network, code division multiple access (CDMA) network, a Bluetooth® network, a ZigBee® network, and / or the like. ​The network interface device(s) can include one or more physical jack(s) (for example, Ethernet, coaxial, or phone jacks) or one or more antenna(es) to connect to communications networks. In an example, the network interface device(s) can include multiple antenna(s) to communicate using Multiple Input Multiple Output (MIMO) techniques. The term "transmission medium" shall be taken to include any intangible medium that is capable of storing, encoding or carrying the instructions for execution by a machine, and includes digital or analog communications signals or other intangible medium to facilitate communication of such software.

[0139] The method examples described herein can be machine or computer- implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level languages code, or the like. Such code can include computer readable instructions for performing various methods. The code can form portions of computer program products. Further, in an example, the code can be tangibly embodied in one or more volatile or non-volatile, tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disk drives, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, RAM, ROM, etc.

[0140] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b) and allows the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together or described in a single embodiment for the purpose of streamlining the disclosure. This should not be interpreted as intending that the claimed subject matter requires more features than are expressly identified in the description. Rather, the subject matter described herein can be practiced with less than all of the features of a particular disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the application should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A frequency compensated amplifier circuit, comprising: a first multi-stage amplifier including a first amplifier input node, a first amplifier output node, and a first amplifier intermediate node; a first feedback path between the first amplifier input node and the first amplifier output node, the first feedback path including a feedback resistor; a gain resistor electrically coupled with the feedback resistor; a second feedback path between the first amplifier intermediate node and the first amplifier output node, the second feedback path including a first capacitor and a resistive portion; and a first switch circuit electrically coupled to the first capacitor and the feedback resistor, the first switch circuit having a plurality of states including: a first state in which the first capacitor is coupled to a first tap point and the resistive portion has a first value; and a second state in which the first capacitor is coupled to a second tap point and the resistive portion has a second value different from the first value.

2. The amplifier circuit of claim 1, further comprising a control circuit configured to selectively set the first switch circuit to the first state or the second state.

3. The amplifier circuit of claim 2, the control circuit configured to use an indication of the gain of the amplifier circuit to select the first state or the second state of the first switch circuit.

4. The amplifier circuit of claim 1, further comprising a gain switch circuit electrically coupled to the first amplifier input node and the gain resistor, the gain switch circuit having: a first state in which the first amplifier input node is coupled to a first tap point of the gain resistor; and a second state in which the first amplifier input node is coupled to a second tap point of the gain resistor different from the first tap point.

5. The amplifier circuit of claim 1, further comprising: a second multi-stage amplifier including a second amplifier input node, a second amplifier output node, and a second amplifier intermediate node; a third feedback path between the second amplifier input node and the second amplifier output node, the third feedback path including a second feedback resistor; a fourth feedback path between the second amplifier output node and the second amplifier intermediate node, the fourth feedback path including a second capacitor and a second resistive portion; a second switch circuit electrically coupled to the second capacitor and the second feedback resistor, the second switch circuit having a first state in which the second capacitor is coupled to a third tap point and the second resistive portion has a third value, the second switch circuit further having a second state in which the second capacitor is coupled to a fourth tap point and the second resistive portion has a fourth value different from the third value; and a differential amplifier, the first amplifier output node electrically coupled to a non-inverting input of the differential amplifier, the second amplifier output node electrically coupled to an inverting input of the differential amplifier.

6. The amplifier circuit of claim 5, the gain resistor electrically coupled between the feedback resistor and the second feedback resistor. ​ 7. The amplifier circuit of claim 1, further comprising a control circuit configured to perform operations comprising: powering on the amplifier circuit; configuring the first switch circuit to a first state to set a bandwidth of the amplifier circuit to a first bandwidth value; and after waiting for a first time period, configuring the first switch circuit to a second state to set the bandwidth of the amplifier circuit to a second bandwidth value less than the first bandwidth value.

8. The amplifier circuit of claim 7, the operations further comprising powering off the amplifier circuit after waiting for a second time period.

9. The amplifier circuit of claim 1, an input node of the first multi-stage amplifier is electrically coupled to a sensor.

10. The amplifier circuit of claim 1, the first amplifier intermediate node comprises a second stage non-inverting input and a second stage inverting input, the second feedback path is between the first amplifier output node and the second stage inverting input.

11. The amplifier circuit of claim 1, the second feedback path further comprises a buffer oriented from the first amplifier output node to the first amplifier intermediate node.

12. The amplifier circuit of claim 1, the first tap point is a tap point of the feedback resistance.

13. The amplifier circuit of claim 1, the second tap point is a tap point of the gain resistance.

14. A method of operating an amplifier, the amplifier comprising a first feedback path, the first feedback path comprising: a feedback resistance electrically coupled between an amplifier input node and an amplifier output node; a gain resistance electrically connected with the feedback resistance; and a second feedback path between a first amplifier intermediate node and the amplifier output node, the second feedback path comprising a capacitor and a resistance portion, the method comprising: configuring a first switch circuit from a first state in which the capacitor is coupled to a first tap point and the resistance portion has a first value to a second state in which the capacitor is coupled to a second tap point and the resistance portion has a second value different from the first value; providing a first feedback signal derived from the amplifier output node to the amplifier input node via the first feedback path; and providing a second feedback signal derived from the amplifier output node to an amplifier intermediate node via the second feedback path.

15. The method of claim 14, further comprising using a gain of the amplifier to select a first portion of a feedback resistance to be coupled into the second feedback path.

16. The method of claim 14, further comprising configuring a gain switch circuit to switch the first portion of the gain resistance into the first feedback path.

17. The method of claim 14, further comprising: powering on the amplifier; and after waiting for a first time period, configuring the first switch circuit to electrically couple a second portion of the feedback resistance into the second feedback path, the second portion of the feedback resistance being less than the first portion of the feedback resistance.

18. The method of claim 17, further comprising: receiving a sensor input signal from a sensor at the amplifier input node; and after receiving the sensor input signal, powering off the amplifier.

19. A frequency compensated amplifier system, comprising: a first multi-stage amplifier comprising a first amplifier input node, a first amplifier output node and a first amplifier intermediate node; a first feedback path between the first amplifier input node and the first amplifier output node, the first feedback path comprising a feedback resistor; a second feedback path between the first amplifier output node and the first amplifier intermediate node, the second feedback path comprising a first capacitor and a resistor portion; means for configuring a first switching circuit from a first state in which a capacitor is coupled to a first tap point and the resistor portion has a first value, to a second state in which the capacitor is coupled to a second tap point and the resistor portion has a second value different from the first value; means for providing a first feedback signal derived from the amplifier output node to the amplifier input node via the first feedback path; and means for providing a second feedback signal derived from the amplifier output node to the amplifier intermediate node via the second feedback path. ​

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