Variable gain amplifier with cross-coupled switch arrangement

Abstract

This disclosure relates to a variable gain amplifier with a cross-coupled switching arrangement. An example VGA includes a transistor arrangement having multiple transistors configured to implement one or more gain step circuits for the VGA, and a cross-coupled switching arrangement having multiple switches configured to selectively change the coupling of at least some of the transistor terminals (depending on whether the given gain step circuit should be ON or OFF). Using a cross-coupled switching arrangement advantageously allows all transistors to always be ON during operation and the coupling of some transistor terminals to achieve in-phase current flow through the various transistors to apply maximum gain or to achieve subtraction to apply minimum gain. Such a VGA can be inherently broadband, enabling highly linear broadband operation without resorting to significant trade-offs with other performance parameters.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to variable gain amplifiers. Background Technology

[0002] A variable gain amplifier (VGA) is an electronic amplifier whose gain depends on a control voltage. VGAs have many applications, including radio frequency (RF) communications, ultrasound, radar, remote sensing, audio compression, amplitude modulation, and synthesizers.

[0003] An ideal characteristic of VGAs is their ability to maintain a substantially constant phase response over a wide range of gain values. Achieving this behavior in real-world VGAs is far more complex, requiring the resolution of numerous challenges in maintaining a constant phase response, often at the expense of other performance parameters such as gain, bandwidth, or noise. Several factors can influence the cost, quality, and robustness of a VGA. Physical constraints such as space / surface area, as well as regulations, can further restrict VGA requirements or specifications. Therefore, trade-offs and ingenuity are essential, and there is always a desire to improve upon VGAs by providing a substantially constant phase response over a wide gain range. Summary of the Invention

[0004] According to one aspect of this disclosure, a variable gain amplifier (VGA) is provided, comprising: a transistor arrangement including a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal; and a switch arrangement, wherein: the transistor arrangement includes a first portion and a second portion, each portion being associated with a corresponding differential input terminal for receiving a corresponding differential input signal, the plurality of transistors of the transistor arrangement including a first transistor and a second transistor in each portion, and the switch arrangement being configured to operate the first and second transistors of each portion in a first mode or a second mode, wherein: in the first mode, a second terminal of the second transistor of the first portion is coupled to the differential input terminal associated with the first portion, and a second terminal of the second transistor of the second portion is coupled to the differential input terminal associated with the second portion; and in the second mode, a second terminal of the second transistor of the first portion is coupled to the differential input terminal associated with the second portion, and a second terminal of the second transistor of the second portion is coupled to the differential input terminal associated with the first portion.

[0005] According to another aspect, a variable gain amplifier (VGA) is provided, comprising: a transistor arrangement including a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal; and a switching arrangement, wherein: the transistor arrangement includes a first portion and a second portion, each portion being associated with a corresponding differential output terminal for providing a corresponding differential output signal, the plurality of transistors of the transistor arrangement including a first transistor and a second transistor in each portion, and the switching arrangement being configured to operate the first and second transistors of each portion in a first mode or a second mode, wherein: in the first mode, a first terminal of a second transistor of the first portion is coupled to a differential output terminal associated with the first portion, and a first terminal of a second transistor of the second portion is coupled to a differential output terminal associated with the second portion; and in the second mode, a first terminal of a second transistor of the first portion is coupled to a differential output terminal associated with the second portion, and a first terminal of a second transistor of the second portion is coupled to a differential output terminal associated with the first portion.

[0006] According to another aspect, a variable gain amplifier (VGA) is provided, comprising: a transistor arrangement including a plurality of transistors; and a switching arrangement, wherein: the transistor arrangement includes a first portion and a second portion, the plurality of transistors of the transistor arrangement including a first transistor and a second transistor in each portion, and the switching arrangement is configured to operate the first and second transistors of each portion in a first mode or a second mode, wherein, for each portion: in the first mode, the current through the second transistor of that portion is added to the current through the first transistor of that portion, and in the second mode, the current through the second transistor of that portion is subtracted from the current through the first transistor of that portion. Attached Figure Description

[0007] To gain a more complete understanding of this disclosure and its features and advantages, reference is made to the following description in conjunction with the accompanying drawings, wherein like reference numerals denote like parts, wherein:

[0008] Figure 1 Schematic diagrams of antenna arrangements according to some embodiments of the present disclosure are provided, wherein one or more VGAs with cross-coupled switch arrangements can be implemented;

[0009] Figure 2A and 2B Circuit diagrams of the ON and OFF states of a VGA having a transistor arrangement implemented using N-type transistors and a cross-coupled switch arrangement implemented on the input side, according to some embodiments of the present disclosure, are provided respectively.

[0010] Figure 3A and 3BCircuit diagrams of the ON and OFF states of a VGA having a transistor arrangement implemented using P-type transistors and a cross-coupled switch arrangement implemented on the input side, according to some embodiments of the present disclosure, are provided respectively.

[0011] Figure 4A and 4B Circuit diagrams of the ON and OFF states of a VGA having a transistor arrangement implemented using N-type transistors and a cross-coupled switch arrangement implemented on the output side, according to some embodiments of the present disclosure, are provided respectively.

[0012] Figure 5A and 5B Circuit diagrams of the ON and OFF states of a VGA having a transistor arrangement implemented using P-type transistors and a cross-coupled switch arrangement implemented on the output side, according to some embodiments of the present disclosure, are provided respectively.

[0013] Figure 6 Circuit diagrams of a VGA having multiple gain step circuits and an example cross-coupled switch arrangement according to some embodiments of the present disclosure are provided.

[0014] Figure 7 A schematic diagram of an RF device is provided, wherein one or more VGAs with a cross-coupled switch arrangement can be implemented according to some embodiments of the present disclosure;

[0015] Figure 8 A block diagram of an illustrative example data processing system according to some embodiments of the present disclosure is provided. This example data processing system can be configured to implement or control operation of at least a portion of a VGA having a cross-coupled switch arrangement. Detailed Implementation

[0016] Overview

[0017] The systems, methods, and apparatuses disclosed herein are innovative in several ways, but none of them alone is responsible for all the desired properties disclosed herein. Details of one or more implementations of the subjects described in this specification are set forth in the following description and figures.

[0018] To describe the VGA with cross-coupled switch arrangement presented herein, it may be helpful to first understand the phenomena that may occur in systems using VGAs. The following basic information can be considered as the basis for a proper interpretation of this disclosure. Such information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0019] As mentioned above, VGA can be used in a variety of applications. For example, VGA can be used in radio systems. Typically, radio systems are systems that transmit and receive signals in the form of electromagnetic waves in the RF range of approximately 3 kHz to 300 GHz. Radio systems are commonly used for wireless communication, with cellular / wireless mobile technology being a prominent example.

[0020] In the context of radio systems, an antenna is a device that acts as an interface between radio waves propagating wirelessly through space and an electric current moving in a metallic conductor, used in conjunction with a transmitter or receiver. During transmission, the radio transmitter can supply current to the antenna's terminals, and the antenna can radiate the energy of that current as radio waves. During reception, the antenna may intercept some of the power of the radio waves to generate a current at its terminals, which may then be amplified by the receiver. Antennas are an essential component of all wireless equipment, used in radio broadcasting, broadcast television, two-way radio, communication receivers, radar, mobile phones, satellite communications, and other devices.

[0021] An antenna with a single antenna element typically broadcasts a radiation pattern that radiates equally in all directions of the spherical wavefront. A phased array antenna (often also called a "phased array") generally refers to a group of antennas (where each antenna is typically called an "antenna element") designed to concentrate electromagnetic energy in a specific direction, thereby generating a main beam. Phased arrays offer many advantages over single-antenna systems, such as high gain, the ability to perform directional control, and simultaneous communication. Therefore, phased arrays are increasingly used in numerous different applications, such as mobile technology, cellular phones and data, Wi-Fi technology, automotive radar, and aircraft radar.

[0022] Each individual antenna element of a phased array can radiate in a spherical pattern; however, multiple such antenna elements can collectively generate a wavefront (often called the "master beam") in a specific direction through constructive and destructive interference. That is, by carefully controlling the phase of the signals wirelessly transmitted by the different antenna elements, the radiation patterns of the different antenna elements can be constructively interfered in the desired direction, generating the master beam in that direction, while simultaneously causing destructive interference in several other directions outside the master beam direction. Therefore, phased arrays typically include phase-shifting modules (often also called "phase shifters") to control the phase of the signals radiated by the different antenna elements.

[0023] In the aforementioned phased array, the accuracy of the main beam direction is highly dependent on the relative phase accuracy between different antenna elements. Unfortunately, carefully controlling the phase of the signal radiated by different antenna elements is not easy, and phase errors can occur for various reasons. Phase errors can cause deviations between the main beam direction and the target direction, which can significantly affect the operation of the phased array, for example, leading to a decrease in gain and linearity performance. One reason why careful phase control is challenging is that VGAs used for power control and gain calibration in the phased array can introduce phase errors if they do not have a constant phase response over a wide range of gain values ​​due to process variations and mismatches. The challenge becomes even more severe if VGAs are used near the end of the phased array receiver chain, where they can become a major factor in receiver nonlinearity. The challenges are further exacerbated by the millimeter-wave spectrum of fifth-generation (5G) wireless communication systems, as achieving a constant phase response becomes more difficult as the operating frequency of VGAs increases, and when VGAs are implemented using transistors based on submicron complementary metal-oxide-semiconductor (CMOS) technology, the low breakdown voltage of such transistors limits the linearity achievable by the VGAs.

[0024] Traditional VGA architectures have not always exhibited sufficiently low phase errors across different gain states, especially at millimeter-wave frequencies. Conventional techniques for minimizing gain-state phase errors typically involved trade-offs between gain, bandwidth, linearity, and VGA noise. Furthermore, these techniques often relied on implementing additional circuit components, such as resistors, which made them less immune to process variations and mismatches. Moreover, traditional techniques often required large voltage swings across some circuit elements, making them less suitable for deep submicron CMOS technologies.

[0025] Various embodiments of this disclosure provide systems and methods aimed at improving one or more of the aforementioned challenges by providing a VGA with a cross-coupled switch arrangement. In one aspect of this disclosure, an example VGA is configured to receive a differential input signal and provide an output signal based on the differential input signal and a target gain. The VGA includes a transistor arrangement and a cross-coupled switch arrangement. The transistor arrangement includes a plurality of transistors configured to form one or more gain step circuits of the VGA, and the cross-coupled switch arrangement includes a plurality of switches configured to selectively change the coupling of at least some of the transistor terminals depending on whether a given gain step circuit should be in an on state (i.e., applying the maximum gain of the gain step circuit to generate the output signal from the stage) or an off state (i.e., applying the minimum gain of the gain step circuit to generate the output signal from the stage). Appropriate control signals can be used to provide an indication to the cross-coupled switch arrangement regarding whether a given gain step circuit should be in an on or off state. The use of a cross-coupled switch arrangement advantageously allows all transistors to remain on throughout VGA operation (i.e., allowing the transistors of the gain step circuit to conduct current) and modulates the coupling of some transistor terminals to achieve / implement in-phase addition of the currents flowing through the various transistors to apply the maximum gain of a given gain step circuit or in-phase subtraction of the currents to apply the minimum gain of that gain step circuit. Such a VGA can be inherently broadband because it guarantees that the capacitance of all VGA nodes is substantially constant regardless of the gain state of the different gain step circuits, thus achieving highly linear broadband operation without significant trade-offs in other performance parameters to achieve a constant phase response. These and other advantages will become clear from the further description of various embodiments of VGAs with cross-coupled switch arrangements presented herein.

[0026] This document provides some description of VGAs with cross-coupled switch arrangements, with reference to wireless communication technologies, particularly phased arrays, as this is where such VGAs may be particularly useful, especially for millimeter-wave spectrum systems for 5G communications and / or transistors implemented using deep submicron technologies. However, in general, various embodiments of VGAs with cross-coupled switch arrangements as described herein are applicable to 5G communication systems operating at frequencies other than millimeter-wave frequencies (e.g., for spectrum below 6 GHz), wireless communication systems using technologies other than 5G (e.g., LTE systems), and systems outside of wireless communication systems (e.g., cable communication systems, ultrasound, radar, remote sensing, audio compression, amplitude modulation, and synthesizers).

[0027] The precise design of the VGA with cross-coupled switch arrangement described herein can be implemented in many different ways, all of which are within the scope of this disclosure.

[0028] In one example of a design variant according to various embodiments of this disclosure, each transistor in a given VGA transistor arrangement with a cross-coupled switch arrangement may be individually selected to employ a field-effect transistor (FET), such as a metal-oxide-semiconductor (MOS) technology transistor (e.g., where the various transistors may be N-type MOS (NMOS) or P-type MOS (PMOS) transistors), a bipolar junction transistor (BJT) (e.g., where the various transistors may be NPN or PNP transistors), or a combination of one or more FETs and one or more BJTs. In view of this, in the following description, references are sometimes made to the first, second, and third terminals of the transistors in the VGA transistor arrangement presented herein. If the transistor is a BJT, the term “first terminal” of the transistor is used to refer to the collector terminal, and if the transistor is an FET, it is used to refer to the drain terminal; if the transistor is a BJT, the term “second terminal” of the transistor is used to refer to the emitter terminal, and if the transistor is an FET, it is used to refer to the source terminal; if the transistor is a BJT, the term “third terminal” of the transistor is used to refer to the base, and if the transistor is an FET, it is used to refer to the gate terminal. The terminology remains the same regardless of whether the transistor of a given technology is an N-type transistor (e.g., an NPN transistor if the transistor is a BJT, and an NMOS transistor if the transistor is a FET) or a P-type transistor (e.g., a PNP transistor if the transistor is a BJT, and a PMOS transistor if the transistor is a FET).

[0029] In another example, across various embodiments, a choice can be made regarding whether the transistors of a given VGA with a cross-coupled switch arrangement are implemented as N-type transistors (e.g., NMOS or NPN transistors) or as P-type transistors (e.g., PMOS or PNP transistors). While N-type transistors may inherently be faster than P-type transistors, P-type transistors may offer other advantages in certain deployment scenarios. In other examples of design variations, across various embodiments, the type of transistor architecture can be chosen. For example, any transistors in the transistor arrangement described herein that are implemented as FETs can be planar transistors or non-planar transistors, such as FinFETs, nanowire transistors, or nanoribbon transistors.

[0030] In some implementations, one or more switches of the VGA cross-coupled switch arrangement described herein can be implemented as transistors. In such embodiments, one or more of the design variations described above with reference to the transistor arrangement of the VGA can also be applied to the transistors of the VGA cross-coupled switch arrangement.

[0031] For illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementations. However, it will be apparent to those skilled in the art that this disclosure may be practiced without specific details, or / and may be practiced only by some of the aspects described. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrative implementation. The innovations described herein may be embodied in a variety of different ways, for example, as defined and covered by the claims or selected examples.

[0032] In the following description, reference is made to the accompanying drawings, wherein the same reference numerals or reference letters may denote elements that are identical or functionally similar. For convenience, if there exists a set of figures designated with different letters, for example... Figure 2A-2B In this case, such a set can be referred to as, for example, "Figure 2" without using letters.

[0033] The accompanying drawings illustrate, by way of illustration, possible embodiments. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure. For example, the elements shown in the figures are not necessarily drawn to scale. Furthermore, some embodiments may include more elements than a subset of those shown in the drawings and / or the accompanying drawings. Additionally, some embodiments may combine any suitable combination of features from two or more drawings. Therefore, the following detailed description of the drawings should not be construed as limiting.

[0034] The description may use the phrases “in one embodiment” or “in an embodiment,” each of which may refer to one or more of the same or different embodiments. Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object merely indicates that different instances of the same object are referred to, and does not imply that the objects so described must be in a given order in time, space, rank, or any other way. Furthermore, for the purposes of this disclosure, the phrase “A and / or B” or the symbol “A / B” refers to (A), (B), or (A and B), while the phrase “A, B, and / or C” refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). As used herein, the symbol “A / B / C” refers to (A, B, and / or C). The term “between,” when used for a range of measurements, includes the ends of the range of measurements.

[0035] The illustrative embodiments are described using terminology commonly used by those skilled in the art to convey the essence of their work to others skilled in the art. For example, the term "connection" refers to a direct electrical connection between connected things without any intermediate devices / components, while the term "coupling" refers to a direct electrical connection between connected things, or an indirect connection via one or more passive or active intermediate devices / components. In another example, the term "circuit" refers to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. Sometimes, the term "circuit" may be omitted in this specification (e.g., Figure 2A-2B The VGA circuit 200 shown in this specification may be referred to as "VGA 200" or the like. Where used, the terms "substantially," "approximately," "probably," etc., may be used generally to refer to within + / -20% of the target value, for example, within + / -10% of the target value, based on the context of a particular value as described herein or known in the art.

[0036] As those skilled in the art will understand, various aspects of this disclosure, particularly aspects of a VGA having a cross-coupled switch arrangement as described herein, can be embodied in various ways—e.g., as a method, system, computer program product, or computer-readable storage medium. Therefore, aspects of this disclosure can take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may be collectively referred to herein as a “circuit,” “arrangement,” “module,” or “system.” At least some of the functions described in this disclosure can be implemented as algorithms executed by one or more hardware processing units (e.g., one or more microprocessors) of one or more computers. In various embodiments, different steps and portions of steps of any method described herein may be executed by different processing units. Furthermore, aspects of this disclosure can take the form of a computer program product contained in one or more computer-readable media, preferably non-transitory, having computer-readable program code embodied thereon (e.g., stored thereon). In various embodiments, such a computer program may, for example, be downloaded (updated) to various devices and systems (e.g., various components and arrangements of components of a radio frequency device or phased array system, and / or its controllers, etc.) or stored at the time of manufacture of these devices and systems.

[0037] Example antenna device

[0038] Figure 1 Schematic diagrams of antenna arrangements 100 (e.g., phased array systems / devices) according to some embodiments of the present disclosure are provided, wherein one or more VGAs with cross-coupled switch arrangements can be implemented. Figure 1As shown, system 100 may include antenna array 110, beamformer array 120, and up / down converter (UDC) circuit 140.

[0039] Generally, antenna array 110 may include one or more, typically multiple antenna elements 112 (to avoid confusion in the figures, ...). Figure 1 (Only one of them is indicated by reference numerals in the figures). In various embodiments, antenna element 112 may be a radiating element or a passive element. For example, antenna element 112 may include a dipole, an open waveguide, a slotted waveguide, a microstrip antenna, etc. In some embodiments, antenna element 112 may include any suitable element configured to wirelessly transmit and / or receive RF signals. Although some embodiments shown in this figure illustrate a number of antenna elements 112, it should be understood that these embodiments can be implemented with an array of any number of two or more antenna elements. Furthermore, while this disclosure may discuss certain embodiments as one type of antenna array, it should be understood that the embodiments disclosed herein can be implemented with different types of antenna arrays, such as time-domain beamformers, frequency-domain beamformers, dynamic antenna arrays, antenna arrays, passive antenna arrays, etc.

[0040] Similarly, beamformer array 120 may include one or more, typically multiple beamformers 122 (to avoid confusion in the figures, ...). Figure 1 (Only one of them is indicated by reference numerals in the figures). Beamformer 122 can be viewed as a transceiver (e.g., a device that can transmit and / or receive signals, in this case, RF signals) that feeds antenna element 112. In some embodiments, a single beamformer 122 of beamformer array 120 corresponds one-to-one with a single antenna element 112 of antenna array 110 (i.e., different beamformers 122 are associated with different antenna elements 112). In other embodiments, more than one beamformer 122 may be associated with a single antenna element 112; for example, if such an antenna element is a dual-polarized antenna element, two beamformers 122 may be associated with a single antenna element 112.

[0041] In some implementations, each beamformer 122 may include a switch 124 to switch the path from the corresponding antenna element 112 to the receiver or transmitter. Although not explicitly stated... Figure 1 As specifically shown, but in some embodiments, each beamformer 122 may also include another switch to switch the path from a signal processor (also not shown) to a receiver or transmitter path. Figure 1As shown, in some embodiments, the transmitter (TX) path of each beamformer 122 may include a phase shifter 126 and an amplifier 128, while the receiver (RX) path may include a phase adjuster 130 and an amplifier 132. The phase shifter 126 may be configured to adjust the phase of the RF signal (TX signal) to be transmitted by the antenna element 112, and the amplifier 128 may be configured to adjust the amplitude of the TX signal to be transmitted by the antenna element 112. Similarly, the phase shifter 130 and the amplifier 132 may be configured to adjust the RF signal (RX signal) received by the antenna element 112 before providing the RX signal to further circuitry (e.g., UDC circuitry 140, a signal processor (not shown), etc.). Beamformer 122 can be considered as being in the “RF path” of antenna device 100 because the signal passing through beamformer 122 is an RF signal (i.e., the TX signal that can pass through beamformer 122 is an RF signal that has been upconverted from a lower frequency (e.g., from intermediate frequency (IF) or from baseband) by UDC circuit 140, while the RX signal that can pass through beamformer 122 is an RF signal that has not yet been downconverted to a lower frequency (e.g., to IF or baseband) by UDC circuit 140).

[0042] although Figure 1 The diagram shows a switch (i.e., switch 124) for switching from the transmitter path to the receiver path, but in other embodiments of the beamformer 122, other components, such as a duplexer, may be used. Furthermore, although... Figure 1 One embodiment is shown in which beamformer 122 includes phase shifters 126, 130 (also referred to as “phase adjusters”) and amplifiers 128, 132; however, in other embodiments, any beamformer 122 may include additional components to adjust the amplitude and / or phase of the TX and / or RX signals. In yet another embodiment, one or more of the beamformers 122 may not include phase shifters 126 and / or 130, since the desired phase adjustment may alternatively be performed in other parts of the RX or TX path (e.g., in the digital domain).

[0043] Turning to the details of the UDC circuit, typically, the UDC circuit 140 may include up-converter and / or down-converter circuitry; that is, in various embodiments, the UDC circuit 140 may include 1) an up-converter circuit but no down-converter circuitry, 2) a down-converter circuit but no up-converter circuitry, or 3) both up-converter and down-converter circuitry. Figure 1 As shown, the downconverter circuit of UDC circuit 140 may include amplifier 142 and mixer 144, while the upconverter circuit of UDC circuit 140 may include amplifier 146 and mixer 148.

[0044] In some implementations, a single UDC circuit 140 can provide an up-converted RF signal to any of the beamformers 122 and / or receive an RF signal from any of the beamformers 122. Therefore, a single UDC circuit 140 can be associated with multiple beamformers 122 of the beamformer array 120 (e.g., it could be 48 beamformers 122 in the beamformer array 120 associated with 48 antenna elements 112 of the antenna array 110). This in Figure 1 The components connecting the beamformer array 120 and the UDC circuit 140 are schematically shown using dashed lines and dashed lines. That is, Figure 1 The dashed lines show that the downconverter circuit (i.e., amplifier 142) of UDC circuit 140 is connected to the RX path of two different beamformers 122, and the dashed lines also show that the upconverter circuit (i.e. amplifier 146) of UDC circuit 140 is connected to the TX path of two different beamformers 122.

[0045] The mixer 144 in the RX path of the UDC circuit 140 may have at least two inputs and one output. The two inputs of the mixer 144 include an input from the amplifier 142 and an input from the local oscillator (LO) 150. The mixer 144 may be configured to receive an RF RX signal from the RX path of one of the beamformers 122 at one of its inputs, after that signal has been amplified by the amplifier 142, and to receive an LO signal from the LO 150 at its other input. It then mixes these two input signals to downconvert the RF RX signal to a lower frequency (LF), generating an LF RX signal 156 (e.g., the LF RX signal may be an IF or a baseband signal). Therefore, the mixer 144 in the RX path of the UDC circuit 140 may be referred to as a "downconversion mixer". The LF RX signal 156 may be output from the mixer 144 at its output.

[0046] Similarly, mixer 148 in the TX path of UDC circuit 140 may have [at least] two inputs and one output. The two inputs of mixer 148 include an input from LO 150 and an LF TX signal 158 (i.e., a lower frequency TX signal; for example, LF TX signal 158 may be an IF or baseband signal). One output of mixer 148 is the output of amplifier 146. Mixer 148 may be configured to receive the LF TX signal 158 at its first input and the LO signal from LO 150 at its second input, and mix these two signals to upconvert the LF TX signal 158 to the desired RF frequency, generating an upconverted RF TX signal, which, after being amplified by amplifier 146, is provided to the TX path of one of beamformers 122. Therefore, mixer 148 in the TX path of UDC circuit 140 may be referred to as an "upconverter mixer." The upconverted RF TX signal may be output from the output of mixer 148.

[0047] As is known in communications and electronic engineering, the IF (interval frequency) is a frequency to which the carrier signal can be shifted as an intermediate step in transmission or reception. An IF signal is generated by mixing the carrier signal with a suitable frequency LO (loose-input) signal in a process called heterodyne, resulting in a difference frequency or beat frequency signal. Converting to IF can be useful for several reasons. One reason is that when using multi-stage filters, they can all be set to a fixed frequency, making them easier to build and tune. Another reason is that transistors at lower frequencies typically have higher gain, thus requiring fewer stages. Yet another reason is to improve frequency selectivity, as it may be easier to create a sharply selective filter at a lower, fixed frequency.

[0048] It should also be noted that although some descriptions provided herein refer to signals 156 and 158 as IF signals, these descriptions also apply to embodiments where signals 156 and 158 are baseband signals. In such embodiments, the mixing of mixers 144 and 148 can be zero-IF mixing (also known as "zero-IF conversion"), where the LO signal used to perform the mixing (i.e., the LO signal generated by LO 150) can have a center frequency in the RF RX / TX frequency band. It should also be noted that, although... Figure 1 The image shows a single LO (i.e., LO 150) providing LO signals to the RX path mixer 144 and the TX path mixer 148. In some embodiments, separate LOs can be used in the RX and TX paths. For example, in a frequency division duplex (FDD) implementation, LO signals of different frequencies can be used by the RX path mixer 144 and the TX path mixer 148 to downconvert and upconvert signals between the RF and LF paths, respectively.

[0049] In some embodiments, one or both of amplifiers 142, 146 may be a VGA, and one or both of amplifiers 142, 146 may be implemented as a VGA having a cross-coupled switch arrangement as described herein. In such embodiments, implementing amplifier 142 as a VGA may be particularly advantageous because amplifier 142 may be the last block in the receiver chain, and therefore has particularly high linearity requirements. In some such embodiments, amplifier 132 may be a low-noise amplifier (LNA) and amplifier 128 may be a power amplifier (PA).

[0050] In other embodiments, one or both of amplifiers 132, 128 may be a VGA, and one or both of amplifiers 132, 128 may be implemented as a VGA having a cross-coupled switch arrangement as described herein. In some such embodiments, amplifier 142 may be an LNA and amplifier 146 may be a PA.

[0051] Although not in Figure 1 As specifically shown, but in a further embodiment, the UDC circuit 140 may also include a balancer, for example, in each of the TX and RX paths, configured to mitigate the imbalance of in-phase and quadrature (IQ) signals due to mismatch. Furthermore, although in Figure 1 While not specifically shown in the text, in a further embodiment, corresponding filters can be implemented at the outputs of mixers 144 and 148 to filter out unwanted frequency components generated during mixing. Furthermore, although in Figure 1 While not specifically shown herein, in other embodiments, antenna device 100 may include further examples of a combination of antenna array 110, beamformer array 120, and UDC circuitry 140 as described herein.

[0052] Antenna device 100 can manipulate the electromagnetic radiation pattern of antenna array 110 in a specific direction, thereby enabling antenna array 110 to generate a main beam in that direction and sidelobes in other directions. The main beam of the radiation pattern is generated based on the phase construction of the transmitted radio frequency signal based on the phase of the transmitted signal. The sidelobe level can be determined by the amplitude of the RF signal transmitted by the antenna elements. Antenna device 100 can generate the desired antenna pattern by providing phase shifter settings for antenna elements 112, such as using the phase shifter of beamformer 122 and / or a phase shifter performed in the digital domain.

[0053] Example of a VGA with a cross-coupled switch arrangement

[0054] As described above, in various embodiments, the VGA with cross-coupled switch arrangement proposed herein can be implemented using N-type or P-type transistors. Furthermore, in various embodiments, the cross-coupled switch arrangement can be implemented on either the input or output side of the VGA. As used herein, if the cross-coupled switch arrangement is configured to change the coupling between some transistors (in particular, terminals referred to herein as the “second terminals” of certain transistors) and the differential input terminals of the VGA, the cross-coupled switch arrangement can be described as “implemented on the input side of the VGA.” On the other hand, if the cross-coupled switch arrangement is configured to change the coupling between some transistors (in particular, terminals referred to herein as the “first terminals” of certain transistors) and the differential output terminals of the VGA, the cross-coupled switch arrangement can be described as “implemented on the output side of the VGA.” Various examples of N-type or P-type transistors and cross-coupled switch arrangements implemented on the input or output side of a VGA with a single gain step circuit are shown in Figures 2-5. Figure 6 An example VGA with multiple gain step circuits is shown.

[0055] Generally, as used herein, the term "switch arrangement" (e.g., some cross-coupled switch arrangements 220 shown in this figure) can include any suitable switch arrangement (e.g., any suitable combination of switches) that allows ensuring the performance of the described switching functions. An example embodiment of the cross-coupled switch arrangement 220 is shown in... Figure 6 As shown below, various embodiments of this disclosure are not limited to this implementation.

[0056] Figure 2A and 2B Circuit diagrams of the ON and OFF states of a VGA 200 having a transistor arrangement 210 implemented using multiple N-type transistors and a cross-coupled switch arrangement 220 implemented on the input side, according to some embodiments of the present disclosure, are provided respectively.

[0057] As shown in Figure 2, the VGA 200 can have a differential architecture because its transistor arrangement 210 can have two parts—a first transistor arrangement part 210-1 (hereinafter referred to as "first part 210-1") and a second transistor arrangement part 210-2 (hereinafter referred to as "second part 210-2"), each part 210 including a plurality of transistors shown in Figure 2 within its respective dashed outline. The VGA 200 can be configured to receive differential input signals at the differential input terminals of the VGA, labeled as the first differential input terminal INP and the second differential input terminal INN. For example, in some embodiments, the first part 210-1 can receive a first input voltage V. INP The input signal is in the form of a bias voltage VB of transistor arrangement 210 and an input signal voltage V. IN (For example, V)INP =VB+V IN The second part 210-2 can receive the second input voltage V. INN The input signal is in the form of the second input voltage V. INN Based on bias voltage VB and signal voltage V IN (For example, V) INN =VB-V IN Therefore, each of the first and second parts 210-1 and 210-2 is associated with a corresponding (i.e., different) input terminal INP and INN for receiving the corresponding differential input signal.

[0058] In some implementations, VGA 200 can be configured to output differential output signals at the differential output terminals of the VGA, labeled as a first differential output terminal OUTP and a second differential output terminal OUTN. For example, in some embodiments, the first portion 210-1 can be configured to generate a first differential output current I. OUTP The second part 210-2 can be configured to generate a second differential output current I. OUTN Therefore, each of the first and second portions 210-1, 210-2 is associated with a corresponding (i.e., different) output terminal OUTP, OUTN, for receiving the corresponding differential output signal. Although not specifically shown in Figure 2 and other illustrations of the VGA with cross-coupled switch arrangement described herein, in some embodiments, the VGA 200 may also include a differential-to-single-ended transformer configured to convert the differential output signals of the first and second portions 210-1, 210-2 into single-ended outputs.

[0059] Figure 2A-2B The example shown illustrates an N-type transistor arrangement 210 as an N-type FET (e.g., an NMOS transistor), with the drain, source, and gate terminals of one of the transistors labeled D, S, and G for one of the transistors (i.e., transistor N0 for the first portion 210-1). For the other N-type transistors shown in this figure, these terminals are not labeled because the designation of the drain, source, and gate terminals of the illustrated transistor and all other N-type transistors conforms to accepted conventions for displaying FETs in circuit diagrams. Since in other embodiments, the VGA 200 may be implemented using an N-type BJT instead of an FET, the drain, source, and gate terminals of the various transistors of the VGA 200 will be described below as first, second, and third terminals, respectively, so that these descriptions can be understood as applicable to the corresponding collector, emitter, and base terminals of the BJT.

[0060] As shown in FIG2, details of the steering transistor arrangement 210 are provided. Each of the portions 210 may include an input transistor M1 and a pair of transistors, shown as the first transistor N. 11 Second transistor N 12 Each transistor can be coupled to the input transistor M1 as a cascode transistor. Also as shown in Figure 2, each section 210 may also include a shared transistor N0, which can also be coupled to the input transistor M1 of that section as a cascode transistor. The first and second transistors N0 of sections 210-1 and 210-2... 11 and N 12 This can be referred to as a "gain step circuit" for VGA 200, and in further embodiments of VGA 200, VGA 200 may contain multiple such gain step circuits. In other words, although only the first and second transistors N of the first portion 210-1 are shown in Figure 2... 11 and N 12 And the first and second transistors N in the second part 210-2 11 and N 12 In a single instance, but in other embodiments, VGA 200 may include the first and second transistors N of portions 210-1 and 210-2. 11 and N 12 Multiple instances, each coupled as described herein and individually controllable by switch arrangement 220 to operate in the first or second mode as described herein.

[0061] By inspection Figure 2A and 2B The differences between them can be seen in transistors N0 and N 11 The coupling of transistors M1 and M2 remains the same relative to each other, regardless of whether VGA 200 is ON or OFF. On the other hand, the coupling of transistor N12 depends on whether VGA 200 is ON or OFF, and this coupling can be changed by the cross-coupled switch arrangement 220.

[0062] More specifically, regarding the ON and OFF states of VGA 200, as shown in Figure 2, for each of section 210, transistors N0, N... 11 and N 12 The first terminal (e.g., the drain terminal) of each of them can be coupled to each other and together coupled to the corresponding differential output terminal of that section. Therefore, the transistors N0 and N of the first section 210-1... 11 and N 12 The first end of each of them can be coupled to the differential output terminal OUTP, while the transistors N0 and N in the second part 210-2 11 and N 12The first end of each of them can be coupled to the differential output terminal OUTN.

[0063] Furthermore, for each of portion 210, transistors N0 and N 11 The second terminals (e.g., source terminals) of each of these components can be coupled to each other and together coupled to the corresponding differential input terminals of that section via input transistor M1. Therefore, transistors N0 and N in the first section 210-1... 11 The second end of each of them can be coupled to the differential input terminal INP, while the transistors N0 and N in the second part 210-2 11 The first terminal of each of them can be coupled to the differential input terminal INN. Specifically, transistors N0 and N in the first part 210-1... 11 The second terminal of each of the transistors in the first part 210-1 can be coupled to the first terminal of the input transistor M1, and the third terminal (e.g., the gate terminal) of the input transistor M1 in the first part 210-1 can be coupled to the differential input terminal INP. Therefore, the first input voltage VINP can be configured to be applied to the third terminal of the input transistor M1 in the first part 210-1. Similarly, transistors N0 and N in the second part 210-2... 11 The second terminal of each of the following components can be coupled to the first terminal of the input transistor M1 in the second part 210-2, and the third terminal of the input transistor M1 in the second part 210-2 can be coupled to the differential input terminal INN. Therefore, the second input voltage V INN It can be configured to be applied to the third terminal of the input transistor M1 of the second part 210-2.

[0064] For the on and off states of VGA 200, the second terminal of transistor M1 of the first and second parts 210 can be coupled to ground (GND) voltage, marked GND in this figure, possibly via corresponding intermediate parts 230-1, 230-2, such as corresponding resistors.

[0065] Furthermore, for each of the 210 components, regarding the on and off states of VGA 200, transistors N0 and N... 11 and N 12 The third terminal of each of the two portions 210 can be coupled to each other and together to the bias voltage Vb. In some embodiments, the transistors N0 and N210 of the two portions 210 11 and N 12 They can be coupled to the same bias voltage Vb. In other embodiments, transistors N0 and N2 in the first and second portions 210-1 and 210-2 can be coupled to the same bias voltage Vb. 11 and N 12 At least some of them provide individual bias voltages.

[0066] The difference between the ON and OFF states of VGA 200 appears in transistor N in each section 210. 12 The second terminal is coupled. Therefore, the switch arrangement 220 is configured to operate the second transistor N of section 210 in either a first mode (corresponding to the ON state of VGA 200, as described below) or a second mode (corresponding to the OFF state of VGA 200, as described below). 12 .

[0067] In the first mode, the switch arrangement 220 is configured to switch the second transistor N of the first portion 210-1. 12 The second terminal is coupled to the differential input terminal INP associated with the first part 210-1 and the second transistor N of the second part 210-2 is coupled to the second transistor N. 12 The second end is coupled to the differential input terminal INN associated with the second part 210-2, such as Figure 2A As shown. In such a configuration, for each of parts 210, via transistor N 11 and N 12 The currents (e.g., alternating current) can be added in phase, thereby increasing the total current on the load (which can be coupled to the output of the VGA 200, for example, to the differential output terminal of the VGA 200). For example, in the first mode, through transistor N of the first part 210-1 11 and N 12 The currents can be added in phase, thereby increasing the total output current I. OUTP The output current I OUTP The transistors N0 and N in the first part 210-1 can be used as a basis (e.g., based on the sum) 11 and N 12 The current. In this context, with respect to transistors N0 and N in the first part 210-1 11 and N 12 DC current and transistors N0 and N in the first part 210-1 11 Compared to the sum of the alternating currents, the total output current I OUTP Described as "increase" (or "decrease", for the second mode), or, in relation to transistors N0 and N in the first part 210-1. 11 Compared to the alternating current, if the total output current I OUTP The AC section increases (or decreases, for the second mode) the total output current I. OUTP This can be described as an "increase" (or "decrease," for the second mode). Similarly, in the first mode, this is achieved through transistor N in the second part 210-2. 11 and N 12 The currents can be added in phase, thereby increasing the total output current I. OUTNThe output current I OUTN The transistors N0 and N2 flowing through the second part 210-2 can be based on (for example, based on the sum) 11 and N 12 The current. In this case, with transistors N0 and N in the second part 210-2 11 and N 12 DC current and the second part of transistor N0 and N in 210-2 11 Compared to the sum of the AC currents, the total output current I OUTN Described as "increase" (or "decrease", for the second mode), or, in relation to transistors N0 and N in the second part 210-2 11 Compared to the alternating current, if the total output current I OUTN The AC section increases (or decreases, for the second mode) the total output current I. OUTN This can be described as "increased" (or "decreased", for the second mode). Because the total output current increases, the gain increases, allowing transistors N in the first and second parts 210-1 and 210-2 to... 11 and N 12 The gain stepping circuit applies its maximum gain to the input signal, such as V. IN To generate output signal I OUT Therefore, the first mode corresponds to the on state of the VGA 200's gain stepping circuit.

[0068] In the second mode, the switch arrangement 220 is configured to switch the second transistor N of the first portion 210-1. 12 The second end is coupled to the differential input terminal INN associated with the second part 210-2, and the second transistor N of the second part 210-2 is coupled to the second transistor N. 12 The second end is coupled to the differential input terminal INP associated with the first part 210-1, such as Figure 2B As shown. Each section 210 has transistor N. 12 This cross-coupling between the second terminal and the differential input terminals of another portion is why switch arrangement 220 is called a "cross-coupled" switch arrangement. In such a configuration, for each of portions 210, power is supplied from the other portions via transistor N. 12 The current (e.g., AC current) can flow from transistors N0 and N through this section. 11 This is subtracted from the current, thus reducing the total current of that section. For example, in the second mode, the total output current I... OUTP The transistors N0 and N in the first part 210-1 can be used as a basis (e.g., based on the sum) 11 The current and the transistor N through the second part 210-2 12The current, where, due to the nature of the differential architecture of the VGA 200, the latter's current will flow from transistors N0 and N1 in the first part 210-1. 11 Subtract it from the current, thereby reducing the total output current I. OUTP Similarly, in the second mode, the total output current I... OUTN The transistors N0 and N in the second part 210-2 can be used as a basis (e.g., based on the sum) 11 The current and the transistor N through the first part 210-1 12 The current, where, due to the nature of the differential architecture of the VGA 200, the latter's current will flow from transistors N0 and N2 in the second part 210-2. 11 Subtract it from the current, thereby reducing the total output current I. OUTN Due to the decrease in total output current and the decrease in gain, the transistors N in the first and second parts 210-1 and 210-2... 11 and N 12 The gain step circuit applies its minimum gain to the input signal V. IN To generate output signal I OUT Therefore, the second mode corresponds to the off state of the VGA 200's gain stepping circuit.

[0069] In the design, to control the amount of gain increase or decrease provided by the gain stepping circuit in the first or second operating mode, the first and second transistors N 11 and N 12 The dimensions can be the same (i.e., they can be substantially the same size) because the increase in gain can be achieved by transistor N. 11 and N 12 The ratio between the cumulative size and the size of transistor N0 is determined. For example, if transistors N0 and N... 11 and N 12 If it's a FET, then its channel width will affect the amount of current conducted between its source and drain terminals. In the minimum gain state, the total AC current I... OUTP Or I OUTN It may be roughly equal to the current of the corresponding transistor N0, and in order to increase the gain, transistors N0 and N 11 and N 12 The alternating currents in the transistors will be added together. Therefore, transistor N 11 and N 12 The channel width of transistor N0 relative to the channel width of transistor N0 can determine the increase in AC current, and therefore the increase in gain. In another example, if transistors N0 and N... 11 and N 12Since it's a BJT, its emitter area will affect the amount of current conducted between its emitter and collector terminals. In the minimum gain state, the total AC current I... OUTP Or I OUTN It may be roughly equal to the current of the corresponding transistor N0, and in order to increase the gain, transistors N0 and N 11 and N 12 The alternating currents in the transistors will be added together. Therefore, transistor N 11 and N 12 The emitter area of ​​the transistor relative to the emitter area of ​​transistor N0 can determine the increase in AC current, and thus the increase in gain.

[0070] If more than one gain step circuit is implemented in the VGA 200 (not specifically shown in Figure 2), Figure 6 (As shown in the example), the differential input terminals INP and INN, the differential output terminals OUTP and OUTN, the input transistor M1 of the first and second portions 210, and the shared transistor N0 of the first and shared portions 210 can be common to all gain step circuits. On the other hand, the first and second transistors N0 of the first and second portions 210-1 and 210-2... 11 and N 12 This will be implemented once for each gain step circuit, and the switching circuit 220 will be configured to control the transistor N of the first and second parts 210-1, 210-2. 12 The second end is coupled to achieve the on or off state of the gain stepping circuit, as described in this article.

[0071] As described above, in both the on and off states of the VGA 200, all transistors in transistor arrangement 210 are turned on because they conduct current that contributes to the output current I. OUTP and I OUTN The current. No need to turn the cascode transistor N on and off. 11 and N 12Alternatively, by changing the DC current of the input transistor M1, regardless of the gain state of one or more gain step circuits of the VGA 200, it is advantageous to ensure a substantially constant capacitance at all VGA nodes, thereby achieving highly linear broadband operation without significant trade-offs in other performance parameters to achieve a constant phase response. This operation contrasts sharply with some conventional implementations where the cascode transistor of a single gain step circuit can be turned on or off by applying a corresponding control signal to the third terminal of such a transistor to achieve the on or off state of each gain step circuit. Therefore, another difference between the VGA 200 and such conventional implementations lies in which terminal of the cascode transistor is affected by the control signal indicating whether a given gain step circuit will operate in the ON or OFF state. That is, the switching arrangement 220 can be configured to receive a control signal that controls the gain state of each gain step circuit, and then the transistor N 12 The second terminal is coupled to the input of its own portion of the differential transistor arrangement of the VGA 200 to achieve ON-state operation, or coupled to the input of other portions of the differential transistor arrangement of the VGA 200 to achieve OFF-state operation. Therefore, in the VGA 200, a control signal indicating whether a given gain step circuit will operate in the ON or OFF state is effectively applied to transistor N in each portion 210. 12 The second terminal. A cross-coupled switch arrangement 220 as described herein is used, along with a pair of first and second transistors N implemented in each differential section 210. 11 and N 12 It provides inherently low phase error across gain states without requiring any phase compensation techniques.

[0072] Figure 3A and 3B Circuit diagrams are provided for the ON and OFF states of a VGA 300 having a transistor arrangement 310 implemented using P-type transistors and a cross-coupled switch arrangement 230 implemented on the input side, according to some embodiments of the present disclosure. The transistor arrangement 310 of the VGA 300 is similar to the transistor arrangement 210 of the VGA 200, except that each N-type transistor in the transistor arrangement 210 (i.e., transistors N0, N1, and N2 in the first and second portions 210-1 and 210-2) 11 N 12 M1) is replaced by a P-type transistor (e.g., a PMOS transistor) in transistor arrangement 310 (i.e., transistors N0 and N1 in the first and second portions 310-1 and 310-2). 11 N 12(M1 is a P-type transistor). The cross-coupled switch arrangement 220 used in VGA 300 can be substantially the same as the cross-coupled switch arrangement used in VGA 200, in terms of the transistor terminals that are configured to be coupled in the first and second operating modes.

[0073] In the P-type transistor embodiment of Figure 3, the description provided with reference to Figure 2 applies to the VGA 300, except that the N-type and P-type transistors are interchanged, and therefore the power supply and current directions are reversed (i.e., the second terminal of the input transistor M1 in each of the first and second portions 210 is not coupled to ground GND, but to the power supply voltage Vs). The names such as "first / drain terminal," "second / emitter terminal," and "third / gain terminal" remain unchanged. Reference letters D, S, and G are also shown for one of the example P-type FETs shown in Figure 3, indicating the transistor terminals of the example N-type FET shown in Figure 2. For brevity, a detailed description of Figure 3 is not provided, as it is essentially similar to the description in Figure 2 except for the changes in the labeling above. Specifically, similar to Figure 2, in the first mode of the VGA 300, the switch arrangement 220 is configured to connect the second transistor N of the first portion 310-1... 12 The second terminal is coupled to the differential input terminal INP associated with the first part 310-1, and the second transistor N of the second part 310-2 is coupled to the second transistor N. 12 The second end is coupled to the differential input terminal INN associated with the second part 310-2, as follows: Figure 3A As shown. Similarly to Figure 2, in the second mode of VGA 300, the switch arrangement 220 is configured to switch the second transistor N of the first portion 310-1. 12 The second end is coupled to the differential input terminal INN associated with the second part 310-2, and the second transistor N of the second part 310-2 is coupled to the second transistor N. 12 The second end is coupled to the differential input terminal INP associated with the first part 310-1, such as... Figure 3B As shown.

[0074] Figure 4A and 4B Circuit diagrams of the ON and OFF states of a VGA 400 according to some embodiments of the present disclosure are provided, wherein transistor arrangement 210 is implemented using N-type transistors, and cross-coupled switch arrangement 420 is implemented on the output side. The transistor arrangement 210 of the VGA 400 can be similar to the transistor arrangement used in the VGA 200, except that the second transistor N... 12The coupling method is as follows. The names “first / drain terminal,” “second / emitter terminal,” and “third / gain terminal,” etc., remain unchanged. Reference letters D, S, and G, indicating the transistor terminals of the example N-type FET shown in Figure 2, are also shown for one of the example N-type FETs shown in Figure 4.

[0075] Specifically, in the ON and OFF gain states of VGA 400, for each of the 210 portions of VGA 400, transistor N 12 The second terminal (e.g., the source terminal) is coupled to transistor N0 and N. 11 The second terminal is coupled to the corresponding differential input terminal of that section via input transistor M1. Therefore, in the VGA 400, transistors N0 and N1 of the first section 210-1... 11 and N 12 The second end of each of them can be coupled to the differential input terminal INP, while the transistors N0 and N in the second part 210-2 11 and N 12 The first end of each of them can be coupled to the differential input INN.

[0076] The difference between the ON and OFF states of VGA 400 appears in transistor N in each of section 210. 12 The coupling is in the first terminal (e.g., the drain terminal). For this purpose, the switch arrangement 420 is configured to operate the second transistor N of section 210 in either a first mode (corresponding to the ON state of VGA 400, as described below) or a second mode (corresponding to the OFF state of VGA 400, as described below). 12 .

[0077] In the first mode of VGA 400, switch arrangement 420 is configured to connect the second transistor N of the first part 210-1. 12 The first terminal is coupled to the differential output terminal OUTP associated with the first part 210-1, and the second transistor N of the second part 210-2 is coupled to the second transistor N. 12 The first end is coupled to the differential output terminal OUTN associated with the second part 210-2, as follows: Figure 4A As shown. In this configuration of VGA 400, for each of sections 210, via transistor N 11 and N 12 The currents (e.g., AC current) can be added in phase, thereby increasing the total current at the load (which can be coupled to the output of the VGA 400, for example, to the differential output terminal of the VGA 400), increasing the gain, and allowing the transistors N of the first and second portions 210-1 and 210-2 of the VGA 400 to... 11 and N 12The gain stepping circuit applies its maximum gain to the input signal V. IN To generate output signal I OUT This is similar to the description of VGA 200. Therefore, similar to VGA 200, the first mode of VGA 400 corresponds to the on state of the gain stepping circuit of VGA 400.

[0078] In the second mode of VGA 400, the switch arrangement 420 is configured to connect the second transistor N of the first part 210-1. 12 The first end is coupled to the differential output terminal OUTN associated with the second part 210-2, and the second transistor N of the second part 210-2 is coupled to the second transistor N of the second part 210-2. 12 The first end is coupled to the differential output terminal OUTP associated with the first part 210-1, such as Figure 4B As shown. In this configuration of the VGA 400, for each of sections 210, the signal is received from another section via transistor N. 12 The current (e.g., alternating current) can flow from transistors N0 and N through this section. 11 This is subtracted from the current, thereby reducing the total current of that section, reducing the gain, and allowing the transistors N in the first and second sections 210-1 and 210-2 of the VGA 400 to... 11 and N 12 The gain stepping circuit applies its minimum gain to the input signal V. IN To generate output signal I OUT This is similar to the description of VGA 200. Therefore, similar to VGA 200, the second mode of VGA 400 corresponds to the off state of the gain stepping circuit of VGA 400.

[0079] For the sake of brevity, a detailed description of Figure 4 is not provided, as it is essentially similar to the description of Figure 2, except for the changes mentioned above.

[0080] Figure 5A and 5B Circuit diagrams of the ON and OFF states of a VGA 500 according to some embodiments of the present disclosure are provided, wherein transistor arrangement 310 is implemented using P-type transistors and cross-coupled switch arrangement 420 is implemented on the output side.

[0081] The transistor arrangement 310 of VGA 500 can be similar to that of VGA 300, the difference being the second transistor N. 12The coupling method is as described below. The cross-coupled switch arrangement 420 used in the VGA 500 can be substantially the same as the cross-coupled switch arrangement used in the VGA 400, in terms of the transistor terminals configured to be coupled in the first and second operating modes. Names such as "first / drain terminal," "second / emitter terminal," and "third / gain terminal" are the same in Figure 5 and other figures. Reference letters D, S, and G are also shown to indicate the transistor terminals of the example N-type FET shown in Figure 2 for one of the example P-type FETs shown in Figure 5.

[0082] Specifically, in the ON and OFF gain states of VGA 500, for each of the portions 310 of VGA 500, transistor N 12 The second terminal (e.g., the source terminal) is coupled to transistor N0 and N. 11 The second terminal of each of them is coupled to the corresponding differential input terminal of that section via input transistor M1. Therefore, in the VGA 500, transistors N0 and N1 of the first section 310-1... 11 and N 12 The second end of each of them can be coupled to the differential input terminal INP, while the transistors N0 and N in the second part 310-2 11 and N 12 The first end of each of them can be coupled to the differential input INN.

[0083] The difference between the ON and OFF states of VGA 500 appears in transistor N in each of section 310. 12 The coupling is in the first terminal (e.g., the drain terminal). For this purpose, the switch arrangement 420 is configured to operate the second transistor N of section 310 in either a first mode (corresponding to the ON state of VGA 500, as described below) or a second mode (corresponding to the OFF state of VGA 500, as described below). 12 .

[0084] In the first mode of VGA 500, switch arrangement 420 is configured to connect the second transistor N of the first part 310-1. 12 The first terminal is coupled to the differential output terminal OUTP associated with the first part 310-1, and the second transistor N of the second part 310-2 is coupled to the second transistor N. 12 The first end is coupled to the differential output terminal OUTN associated with the second part 310-2, as follows: Figure 5A As shown. In this configuration of the VGA 500, for each of the 310 sections, via transistor N... 11 and N 12The currents (e.g., AC current) can be added in phase, thereby increasing the total current at the load (which can be coupled to the output of the VGA 500, for example, to the differential output terminal of the VGA 500), increasing the gain, and allowing the transistors N in the first and second portions 310-1, 310-2 of the VGA 500 to... 11 and N 12 The gain step circuit applies its maximum gain to the input signal V. IN To generate output signal I OUT This is similar to the description of VGA 400. Therefore, similar to VGA 400, the first mode of VGA 500 corresponds to the on state of the gain stepping circuit of VGA 500.

[0085] In the second mode of VGA 500, the switch arrangement 420 is configured to connect the second transistor N of the first part 310-1. 12 The first terminal is coupled to the differential output terminal OUTN associated with the second part 310-2, and as... Figure 5B As shown, the second transistor N of the second part 310-2 12 The first end is coupled to the differential output terminal OUTP associated with the first section 310-1. In this configuration of the VGA 500, for each section 310, power is supplied from the other section via transistor N. 12 The current (e.g., alternating current) can flow from transistors N0 and N through this section. 11 This is subtracted from the current, thereby reducing the total current of that section, reducing the gain, and allowing the transistors N in the first and second sections 310-1 and 310-2 of the VGA 500 to... 11 and N 12 The gain step circuit applies its minimum gain to the input signal V. IN To generate output signal I OUT Similar to the description of VGA 400, the second mode of VGA 500 corresponds to the OFF state of the gain stepping circuit of VGA 500.

[0086] For the sake of brevity, a detailed description of Figure 5 is not provided, as it is substantially similar to the description of the aforementioned figures, except for the changes in the labels above.

[0087] Figure 6 Circuit diagrams of a VGA 600 having multiple gain stepping circuits 602-1 to 602-K and an example cross-coupled switch arrangement 620 according to some embodiments of the present disclosure are provided. Figure 6 The example shown is the same as Figure 2A-2BThe example shown is similar in that it uses N-type transistors in transistor arrangement 210 and implements switch arrangement 620 on the input side. Therefore, switch arrangement 620 is an example implementation of the switch arrangement 220 described above. Figure 6 As shown, when K gain step circuits 602 are used (where K can be any positive integer, for example, K can be greater than 1), then each gain step circuit 602 includes first and second transistors N for each differential portion of the transistor arrangement 210. 11 and N 12 The specified pairs (i.e., each gain step circuit 602 may include a total of 4 transistors). Transistors N0 and M1 are then coupled to each of the gain step circuits 602 as described herein (in other words, shared among multiple gain step circuits 602).

[0088] The switch arrangement 620 describes a scenario where, in some embodiments, a set of four switches for each gain step circuit 602 can be used to selectively configure each gain step circuit to operate in a first mode (i.e., ON state) or a second mode (i.e., OFF state). For example, for switch arrangement 620, gain step circuit 602-1 can be configured to operate in the first mode for each of the differential portions 210-1, 210-2 when switch s1 is closed and switch s2 is open. Alternatively, gain step circuit 602-1 can be configured to operate in the second mode when switch s1 is open and switch s2 is closed for each of the differential portions 210-1, 210-2. In other embodiments, other switch arrangements are contemplated, all of which are within the scope of this disclosure.

[0089] Examples of radio frequency devices and systems

[0090] In some implementations, the VGA with cross-coupled switch arrangement described herein can include various RF devices and systems used in wireless communications. For illustrative purposes only, example RF devices may include any VGA with the cross-coupled switch arrangement described herein. Figure 7 The following is illustrated and described. However, in general, VGAs having the cross-coupled switch arrangement as described herein can be included in other devices and systems, all of which are within the scope of this disclosure.

[0091] Figure 7 This is a block diagram of an example RF device 2200 (e.g., an RF transceiver) according to some embodiments of the present disclosure, wherein one or more VGAs with cross-coupled switch arrangements can be implemented.

[0092] Typically, RF device 2200 can be any device or system capable of supporting wireless transmission and / or reception of signals in the form of electromagnetic waves within the RF range of approximately 3 kHz to approximately 300 GHz. In some embodiments, RF device 2200 can be used for wireless communication, for example, in a base station (BS) or user equipment (UE) device of any suitable cellular wireless communication technology (e.g., GSM, WCDMA, or LTE). In yet another example, RF device 2200 can be used as, or in a BS or UE device of, for example, millimeter-wave wireless technology (e.g., 5G wireless) (i.e., high-frequency / short-wavelength spectrum, for example, frequencies in the range of approximately 20 to 60 GHz, corresponding to wavelengths in the range of approximately 5 to 15 millimeters). In yet another example, RF device 2200 can be used for wireless communication using Wi-Fi technology (e.g., the 2.4 GHz band, corresponding to approximately 12 cm wavelength, or the 5.8 GHz band, spectrum, corresponding to approximately 5 cm wavelength), for example in Wi-Fi-enabled devices such as desktop computers, laptops, video game consoles, smartphones, tablets, smart TVs, digital audio players, automobiles, printers, etc. In some implementations, the Wi-Fi-enabled device can be, for example, a node in a smart system configured to communicate with other nodes, such as a smart sensor. In another example, RF device 2200 can be used for wireless communication using Bluetooth technology (e.g., the band from approximately 2.4 to approximately 2.485 GHz, corresponding to approximately 12 cm wavelength). In other embodiments, RF device 2200 can be used to transmit and / or receive RF signals for purposes other than communication, for example in automotive radar systems, or in medical applications such as MRI.

[0093] In various embodiments, RF device 2200 may be included in an FDD or Time-Domain Duplex (TDD) variant of frequency allocation that can be used in a cellular network. In an FDD system, uplink (i.e., RF signals transmitted from the UE device to the BS) and downlink (i.e., RF signals transmitted from the BS to the US device) can use different frequency bands simultaneously. In a TDD system, uplink and downlink can use the same frequency but at different times.

[0094] exist Figure 7Several components included in RF device 2200 are shown, but any one or more of these components may be omitted or copied to suit the application. For example, in some embodiments, RF device 2200 may be an RF device that supports both wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include components referred to herein as the transmit (TX) path and components referred herein as the receive (RX) path. However, in other embodiments, RF device 2200 may be an RF device that only supports wireless reception (e.g., an RF receiver), in which case it may include components of the RX path but not components of the TX path; or RF device 2200 may be an RF device that only supports wireless transmission (e.g., an RF transmitter), in which case it may include components of the TX path but not components of the RX path.

[0095] In some implementations, some or all of the components included in the RF device 2200 may be attached to one or more motherboards. In some implementations, some or all of these components are manufactured on a single chip, for example, on a single system-on-a-chip (SoC).

[0096] Furthermore, in various embodiments, the RF device 2200 may not include... Figure 7 The RF device 2200 may include one or more components as shown, but may include interface circuitry for coupling to one or more components. For example, the RF device 2200 may not include antenna 2202, but may include antenna interface circuitry (e.g., matching circuitry, connectors, and driver circuitry) to which antenna 2202 may be coupled. In another set of examples, the RF device 2200 may not include digital processing unit 2208 or LO 2206, but may include device interface circuitry (e.g., connectors and support circuitry) to which digital processing unit 2208 or LO 2206 may be coupled.

[0097] like Figure 7 As shown, RF device 2200 may include antenna 2202, duplexer 2204 (e.g., if RF device 2200 is an FDDRF device; otherwise, duplexer 2204 may be omitted), LO 2206, and digital processing unit 2208. Also as... Figure 7 As shown, the RF device 2200 may include an RX path, which may include an RX path amplifier 2212, an RX path premix filter 2214, an RX path mixer 2216, an RX path postmix filter 2218, and an analog-to-digital converter (ADC) 2220. Figure 7Further, the RF device 2200 may include a TX path, which may include a TX path amplifier 2222, a TX path post-mixer filter 2224, a TX path mixer 2226, a TX path pre-mixer filter 2228, and a digital-to-analog converter (DAC) 2230. Furthermore, the RF device 2200 may also include an impedance tuner 2232, an RF switch 2234, and control logic 2236. In various embodiments, the RF device 2200 may include... Figure 7 Multiple instances of any of the components shown. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form or be part of the RF front end (FE) of RF device 2200. In some embodiments, RX path amplifier 2212, TX path amplifier 2222, duplexer 2204, and RF switch 2234 may be considered to form or be part of the RF FE of RF device 2200. In some embodiments, RX path mixer 2216 and TX path mixer 2226 (possibly with Figure 7 The associated premixing and postmixing filters shown can be considered as forming the RF transceiver of RF device 2200 or as part of the RF transceiver of RF device 2200 (or RF receiver or RF transmitter, if only RX path or TX path components are included in RF device 2200, respectively). In some embodiments, RF device 2200 may also include one or more control logic elements / circuits, such as Figure 7 The diagram illustrates control logic 2236, such as an RFFE control interface. In some embodiments, control logic 2236 may be configured to control the operation of at least a portion of one or more VGAs having a cross-coupled switch arrangement. For example, control logic 2236 may be configured to provide control signals to the cross-coupled switch arrangement described herein to indicate which gain step circuits should be on and which gate step circuits should be off at a given time. In another example, control logic 2236 may be configured to directly control the switches of the cross-coupled switch arrangement as described herein to place individual gain step circuits in an ON or OFF state. In some embodiments, control logic 2236 may be used to perform other functions within RF device 2200, such as enhancing control over complex RF system environments, supporting the implementation of envelope tracking techniques, reducing power dissipation, etc.

[0098] Antenna 2202 can be configured to receive and transmit communication signals according to any wireless standard or protocol, such as Wi-Fi, LTE, or GSM, and any other wireless protocol specified as 3G, 4G, 5G, and higher. If RF device 2200 is an FDD transceiver, antenna 2202 can be configured to simultaneously receive and transmit communication signals in separate, i.e., non-overlapping and discontinuous frequency bands, for example, in frequency bands spaced apart by, for example, 20 MHz. If RF device 2200 is a TDD transceiver, antenna 2202 can be configured to sequentially receive and transmit communication signals in frequency bands where the TX and RX paths may be the same or overlapping. In some embodiments, RF device 2200 can be a multi-band RF device, in which case antenna 2202 can be configured to simultaneously receive signals having multiple RF components in a single frequency band and / or be configured to simultaneously transmit signals having multiple RF components in a single frequency band. In such embodiments, antenna 2202 can be a single broadband antenna or multiple band-specific antennas (i.e., multiple antennas each configured to receive and / or transmit signals in a specific frequency band). In various embodiments, antenna 2202 may include multiple antenna elements, such as multiple antenna elements forming a phased antenna array (i.e., a communication system or antenna array that can use multiple antenna elements and phase shifts to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array can provide advantages such as increased gain, directional control capability, and simultaneous communication. In some embodiments, RF device 2200 may include more than one antenna 2202 to achieve antenna diversity. In some such embodiments, an RF switch 2234 may be deployed to switch between different antennas.

[0099] The output of antenna 2202 can be coupled to the input of duplexer 2204. Duplexer 2204 can be any suitable component configured to filter multiple signals to allow bidirectional communication via a single path between duplexer 2204 and antenna 2202. Duplexer 2204 can be configured to provide an RX signal to the RX path of RF device 2200 and to receive a TX signal from the TX path of RF device 2200.

[0100] RF device 2200 may include one or more LOs 2206 configured to provide an LO signal that can be used for down-conversion of RF signals received by antenna 2202 and / or up-conversion of signals to be transmitted by antenna 2202.

[0101] RF device 2200 may include a digital processing unit 2208, which may include one or more processing devices. The digital processing unit 2208 may be configured to perform various functions related to the digital processing of RX and / or TX signals. Examples of such functions include, but are not limited to, decimation / downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although Figure 7 Not shown, but in some embodiments, the radio frequency device 2200 may also include a storage device configured to cooperate with the digital processing unit 2208.

[0102] The steering may include details of the RX path in RF device 2200, and in some embodiments, RX path amplifier 2212 may include an LNA. In some embodiments, RX path amplifier 2212 may include a VGA with a cross-coupled switch arrangement according to any embodiment of this disclosure. The input of RX path amplifier 2212 may be coupled to an antenna port (not shown) of antenna 2202, for example, via duplexer 2204. RX path amplifier 2212 may amplify the RF signal received by antenna 2202.

[0103] The output of the RX path amplifier 2212 can be coupled to the input of the RX path premix filter 2214, which can be a harmonic or bandpass (e.g., low-pass) filter, configured to filter the received RF signal that has been amplified by the RX path amplifier 2212.

[0104] The output of the RX path premixer 2214 can be coupled to the input of the RX path mixer 2216, also referred to as a downconverter. The RX path mixer 2216 can include two inputs and one output. A first input can be configured to receive an RX signal, which can be a current signal indicating the signal received by the antenna 2202 (e.g., the first input can receive the output of the RX path premixer 2214). A second input can be configured to receive an LO signal from one of the local oscillators 2206. The RX path mixer 2216 can then mix the signals received at its two inputs to generate a downconverted RX signal, provided at the output of the RX path mixer 2216. As used herein, downconversion refers to the process of mixing a received RF signal with an LO signal to generate a lower frequency signal. Specifically, the TX path mixer (e.g., the downconverter) 2216 can be configured to generate a sum and / or difference frequency at the output port when two input frequencies are provided at the two input ports. In some implementations, RF device 2200 can implement a direct conversion receiver (DCR), also known as a zero-difference, synchronous, or zero-IF receiver. In this case, RX path mixer 2216 can be configured to demodulate the incoming radio signal using an LO signal that is the same as or very close to the carrier frequency of the radio signal. In other embodiments, RF device 2200 can utilize down-conversion to intermediate frequency (IF). IF can be used in superheterodyne radio receivers, where the received RF signal is converted to IF before the final detection of information in the received signal is completed. Conversion to IF can be useful for a variety of reasons. For example, when using multi-stage filters, they can all be set to fixed frequencies, making them easier to build and tune. In some implementations, RX path mixer 2216 may include several such IF conversion stages.

[0105] Despite Figure 7 The RX path diagram shows a single RX path mixer 2216, but in some embodiments, the RX path mixer 2216 can be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer can be configured to perform downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by antenna 2202 and the in-phase component of the LO signal provided by LO 2206. The second RX path mixer can be configured to perform downconversion to generate a quadrature (Q) downconverted RX signal by mixing the RX signal received by antenna 2202 and the quadrature component of the LO signal provided by LO 2206 (the quadrature component is a component that is 90 degrees out of phase with the in-phase component of the LO signal). The output of the first RX path mixer can be provided to the I signal path, and the output of the second RX path mixer can be provided to the Q signal path, which can be 90 degrees out of phase with the I signal path.

[0106] The output of RX path mixer 2216 may optionally be coupled to RX path post-mixer filter 2218, which may be a low-pass filter. If RX path mixer 2216 is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers, respectively, may be coupled to the respective individual first and second RX path post-mixer filters included in filter 2218.

[0107] ADC 2220 can be configured to convert the mixed RX signal from RX path mixer 2216 from the analog domain to the digital domain. ADC 2220 can be a quadrature ADC, similar to RX path quadrature mixer 2216, and can include two ADCs configured to digitize the down-converted RX path signal separated into in-phase and quadrature components. The output of ADC 2220 can be provided to digital processing unit 2208, which is configured to perform various functions related to the digital processing of the RX signal, thereby extracting the information encoded in the RX signal.

[0108] Moving on to the details of the TX path that may be included in RF device 2200, the digital signal (TX signal) to be transmitted later by antenna 2202 can be provided from digital processing unit 2208 to DAC 2230. For ADC 2220, DAC 2230 may include two DACs configured to convert the digital I- and Q-path TX signal components into analog form, respectively.

[0109] Optionally, the output of DAC 2230 can be coupled to TX path premix filter 2228, which can be a bandpass (e.g., low-pass) filter (or a pair of bandpass filters, such as low-pass filters, in the case of quadrature processing), configured to filter out signal components outside the desired frequency band from the analog TX signal output by DAC 2230. The digital TX signal can then be provided to TX path mixer 2226, which may also be referred to as an upconverter. Similar to RX path mixer 2216, TX path mixer 2226 may include a pair of TX path mixers for mixing in-phase and quadrature components. Similar to the first and second RX path mixers that can be included in the RX path, each TX path mixer of TX path mixer 2226 may include two inputs and one output. The first input can receive TX signal components converted to analog form by the corresponding DAC 2230, which will be upconverted to generate the RF signal to be transmitted. The first TX path mixer generates an in-phase (I) up-converted signal by mixing the TX signal component converted to analog form by DAC 2230 with the in-phase component of the TX path LO signal provided from LO 2206. (In various embodiments, LO 2206 may include multiple different local oscillators or be configured to provide different local oscillator frequencies for mixer 2216 in the RX path and mixer 2226 in the TX path.) The second TX path mixer generates a quadrature-phase (Q) up-converted signal by mixing the TX signal component converted to analog form by DAC 2230 with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer can be added to the output of the first TX path mixer to create a real RF signal. A second input of each TX path mixer can be coupled to local oscillator 2206.

[0110] Optionally, the RF device 2200 may include a TX path post-mixer filter 2224 configured to filter the output of the TX path mixer 2226.

[0111] In some embodiments, the TX path amplifier 2222 may include an array 330 of one or more PAs, such as PA 332. In some embodiments, according to any embodiment of this disclosure, the TX path amplifier 2222 may include a VGA with a cross-coupled switch arrangement.

[0112] In various embodiments, any one of the RX path premix filter 2214, RX path postmix filter 2218, TX postmix filter 2224, and TX premix filter 2228 may be implemented as an RF filter. In some embodiments, the RF filter may be implemented as a plurality of RF filters or a filter bank. The filter bank may include a plurality of RF filters that can be coupled to a switch (e.g., RF switch 2234) and configured to selectively switch any one of the plurality of RF filters on and off (e.g., activate any one of the plurality of RF filters) to achieve the desired filtering characteristics of the filter bank (i.e., to program the filter bank). For example, when the RF device 2200 is or is included in a BS or UE device, such a filter bank may be used to switch between different RF frequency ranges. In another example, such a filter bank may be programmable to suppress TX leakage at different duplex distances.

[0113] Impedance tuner 2232 may include any suitable circuitry configured to match the input and output impedances of different RF circuits to minimize signal loss in RF device 2200. For example, impedance tuner 2232 may include an antenna impedance tuner. The ability to tune the impedance of antenna 2202 may be particularly advantageous because the antenna impedance is a function of the RF device 2200, for example, the impedance variation of the antenna depends on, for example, whether the antenna is held in one's hand, placed on a car roof, etc.

[0114] As described above, the RF switch 2234 can be a device configured to route high-frequency signals through a transmission path, for example, in order to Figure 7 The components shown are selectively switched among multiple instances, for example, to achieve desired behavior and characteristics of the RF device 2200. For example, in some embodiments, the RF switch may be used to switch between different antennas 2202. In other embodiments, the RF switch may be used to switch between multiple RF filters of the RF device 2200 (e.g., by selectively turning RF filters on and off). Typically, an RF system will include multiple such RF switches.

[0115] RF device 2200 is provided in a simplified version, and in further embodiments, may include devices not in... Figure 7Other components are specifically illustrated below. For example, the RX path of RF device 2200 may include a current-to-voltage amplifier between the RX path mixer 2216 and the ADC 2220, which may be configured to amplify the down-converted signal and convert it into a voltage signal. In another example, the RX path of RF device 2200 may include a balun for generating a balanced signal. In yet another example, RF device 2200 may also include a clock generator, which may include, for example, a suitable phase-locked loop (PLL) configured to receive a reference clock signal and use it to time the operation of the ADC 2220, DAC 2230, and / or may also be used by local oscillator 2206 to time the operation of a local oscillator signal to be used in the RX or TX path.

[0116] Example Data Processing System

[0117] Figure 8 A block diagram illustrating an example data processing system 2300 according to some embodiments of the present disclosure is provided. This example data processing system 2300 can be configured to control the operation of one or more VGAs using the cross-coupled switch arrangement described herein. For example, the data processing system 2300 can be configured to use a reference... Figure 1-7 The described cross-coupled switch arrangement implements or controls the operation of one or more VGA components. In some embodiments, the data processing system 2300 can be configured to implement... Figure 7 At least a portion of the control logic 2236 shown.

[0118] like Figure 8 As shown, the data processing system 2300 may include at least one processor 2302, such as a hardware processor 2302, coupled to a memory element 2304 via a system bus 2306. Therefore, the data processing system can store program code within the memory element 2304. Furthermore, the processor 2302 can execute program code accessed from the memory element 2304 via the system bus 2306. On one hand, the data processing system can be implemented as a computer suitable for storing and / or executing program code. However, it should be understood that the data processing system 2300 can be implemented in the form of any system including a processor and memory capable of performing the functions described in this disclosure.

[0119] In some embodiments, processor 2302 may execute software or algorithms to perform the activities discussed in this disclosure, particularly activities relating to operating one or more VGAs having a cross-coupled switch arrangement as described herein. Processor 2302 may include any combination of hardware, software, or firmware providing programmable logic, including, as non-limiting examples, a microprocessor, digital signal processor (DSP), field-programmable gate array (FPGA), programmable logic array (PLA), application-specific integrated circuit (IC) (ASIC), or virtual machine processor. Processor 2302 may be communicatively coupled to memory element 2304, for example in a direct memory access (DMA) configuration, such that processor 2302 can read from or write to memory element 2304.

[0120] Generally, memory element 2304 may include any suitable volatile or non-volatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash memory, read-only memory (ROM), optical media, virtual memory regions, magnetic or magnetic tape memory, or any other suitable technology. Unless otherwise stated, any memory element discussed herein should be construed as being included within the broad term "memory". Information being measured, processed, tracked, or sent to or from any component of data processing system 2300 may be provided in any database, register, control list, cache, or storage structure, all of which may be referenced within any suitable time frame. Any such storage option may be included within the broad term "memory" as used herein. Similarly, any potential processing elements, modules, and machines described herein should be construed as being included within the broad term "processor". Each element shown in this figure illustrates having, as Figure 1-7 Any elements of the VGA with the cross-coupled switch arrangement shown may also include suitable interfaces for receiving, transmitting and / or otherwise conveying data or information in a network environment so that they can communicate with, for example, the data processing system 2300.

[0121] In some example implementations, a mechanism for a VGA with the cross-coupled switch arrangement outlined herein can be implemented by logic encoded in one or more tangible media, which may include non-transitory media, such as embedded logic provided in ASIC, DSP instructions, software (potentially including object code and source code) executed by a processor or other similar machine. In some of these cases, storage elements, such as Figure 8The memory element 2304 shown can store data or information for the operations described herein. This includes memory elements capable of storing software, logic, code, or processor instructions that are executed to perform the activities described herein. A processor can execute any type of instructions associated with data or information to implement the operations detailed herein. In one example, such as Figure 8 A processor, such as processor 2302 shown, can transform an element or item (data) from one state or thing to another. In another example, the activities outlined herein can be implemented using fixed logic or programmable logic (e.g., software / computer instructions executed by a processor), and the elements identified herein can be some type of programmable processor, programmable digital logic (e.g., FPGA, DSP, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), or an ASIC that includes digital logic, software, code, electronic instructions, or any suitable combination thereof.

[0122] Memory element 2304 may include one or more physical memory devices, such as local memory 2308 and one or more mass storage devices 2310. Local memory may refer to RAM or other non-persistent memory devices that are typically used during the actual execution of the program code. Mass storage devices may be implemented as hard disk drives or other persistent data storage devices. Processing system 2300 may also include one or more cache memories (not shown) that provide temporary storage for at least some program code to reduce the number of times program code must be retrieved from mass storage device 2310 during execution.

[0123] like Figure 8 As shown, memory element 2304 can store application program 2318. In various embodiments, application program 2318 can be stored in local memory 2308, one or more mass storage devices 2310, or separately from local memory and mass storage devices. It should be understood that data processing system 2300 can also execute an operating system that facilitates the execution of application program 2318. Figure 8 (Not shown in the image). The application 2318, implemented as executable program code, can be executed by the data processing system 2300, for example, by the processor 2302. In response to the execution of the application, the data processing system 2300 can be configured to perform one or more of the operational or method steps described herein.

[0124] The input / output (I / O) devices, described as input device 2312 and output device 2314, may optionally be coupled to a data processing system. Examples of input devices may include, but are not limited to, a keyboard, a pointing device such as a mouse, etc. Examples of output devices may include, but are not limited to, a monitor or display, a speaker, etc. In some embodiments, output device 2314 may be any type of screen display, such as a plasma display, a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an electroluminescent (EL) display, or any other indicator, such as a dial, a barometer, or an LED. In some embodiments, the system may include a driver (not shown) for output device 2314. Input and / or output devices 2312, 2314 may be coupled to the data processing system directly or through an intervening I / O controller.

[0125] In one embodiment, the input and output devices can be implemented as a combined input / output device (in... Figure 8 (Seen in the diagram with dashed lines surrounding input device 2312 and output device 2314). An example of such a combined device is a touch-sensitive display, sometimes also called a "touchscreen display" or simply a "touchscreen". In such an embodiment, input to the device can be provided by movement of a physical object on or near the touchscreen display, such as a user's stylus or finger.

[0126] Network adapter 2316 may also optionally be coupled to the data processing system, enabling it to couple to other systems, computer systems, remote network devices, and / or remote storage devices by intervening in private or public networks. The network adapter may include a data receiver for receiving data transmitted to the data processing system 2300 by said systems, devices, and / or networks, and a data transmitter for transmitting data from the data processing system 2300 to said systems, devices, and / or networks. Modems, cable modems, and Ethernet cards are examples of different types of network adapters that can be used with the data processing system 2300.

[0127] Select an example

[0128] The following paragraphs provide various examples of the embodiments disclosed herein.

[0129] Example 1 provides a VGA configured to receive differential input signals and generate an output signal based on the differential input signals and a desired gain. The VGA includes: a transistor arrangement comprising a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal; and a switch arrangement wherein the transistor arrangement includes a first portion and a second portion (e.g., positive (P) and negative (N) sides of a differential circuit), each portion being coupled to receive a corresponding differential input signal (e.g., the first portion is coupled to a differential input terminal INP as described herein and is configured to receive a first differential input signal (e.g., a bias voltage VB and an input voltage signal V based on the transistor arrangement). IN The sum of voltage signals V INP For example, V INP =VB+V IN Meanwhile, the second part is coupled to the differential input terminal INN described herein and is configured to receive a second differential input signal (e.g., a bias voltage VB based on a transistor arrangement and an input voltage signal V). IN The sum of voltage signals V INN For example, V INN =VB-V IN The corresponding (i.e., different) differential input terminals of the transistors are associated (e.g., coupled to or have) each other. Furthermore, the plurality of transistors in the transistor arrangement include a first transistor (e.g., transistor N described herein) in each section. 11 ) and the second transistor (e.g., transistor N described herein) 12 Furthermore, the switch arrangement is configured to operate the first and second transistors of each portion in either a first mode or a second mode, wherein in the first mode, a second terminal of the second transistor of the first portion is coupled to a differential input associated with the first portion, and a second terminal of the second transistor of the second portion is coupled to a differential input associated with the second portion; and in the second mode, a second terminal of the second transistor of the first portion is coupled to a differential input associated with the second portion, and a second terminal of the second transistor of the second portion is coupled to a differential input associated with the first portion.

[0130] Example 2 provides a VGA according to Example 1, wherein each section is associated with a corresponding differential output for providing a corresponding differential output signal (e.g., a first section is coupled to a differential output OUTP, and a second section is coupled to a differential output OUTN, as described herein), and for each section, a first terminal of each of the first and second transistors of that section is coupled to the differential output associated with that section, and a second terminal of the first transistor of that section is coupled to the differential input associated with that section.

[0131] Example 3 provides a VGA according to Example 1 or 2, wherein the plurality of transistors arranged in the transistor arrangement include an input transistor (e.g., transistor M1 as described herein) in each section, and for each section, a second terminal of a first transistor of that section is coupled to a differential input associated with that section via the input transistor of that section. In a first mode, a second terminal of a second transistor of the first section is coupled to a differential input associated with the first section via the input transistor of the first section, and a second terminal of a second transistor of the second section is coupled to a differential input associated with the second section via the input transistor of the second section. In a second mode, a second terminal of a second transistor of the first section is coupled to a differential input associated with the second section via the input transistor of the second section, and a second terminal of a second transistor of the second section is coupled to a differential input associated with the first section via the input transistor of the first section.

[0132] Example 4 provides a VGA according to any of the foregoing examples, wherein the plurality of transistors arranged in the transistor configuration include an input transistor (e.g., transistor M1 as described herein) in each section, and for each section, a second terminal of a first transistor of that section is coupled to a first terminal of an input transistor of that section, and a third terminal of an input transistor of that section is coupled to a differential input associated with that section. In a first mode, the second terminal of a second transistor of a first section is coupled to a differential input associated with the first section in such a way that the second terminal of the second transistor of the first section is coupled to the first terminal of the input transistor of the first section, while the third terminal of the input transistor of the first section is coupled to a differential input associated with the first section; and the second terminal of a second transistor of a second section is coupled to a differential input associated with the second section in such a way that the second terminal of the second transistor of the second section is coupled to the first terminal of the input transistor of the second section, while the third terminal of the input transistor of the second section is coupled to a differential input associated with the second section. In the second mode, the second terminal of the second transistor of the first part is coupled to the differential input associated with the second part in the following manner: the second terminal of the second transistor of the first part is coupled to the first terminal of the input transistor of the second part, while the third terminal of the input transistor of the second part is coupled to the differential input associated with the second part; and the second terminal of the second transistor of the second part is coupled to the differential input associated with the first part in the following manner: the second terminal of the second transistor of the second part is coupled to the first terminal of the input transistor of the first part, while the third terminal of the input transistor of the first part is coupled to the differential input associated with the first part.

[0133] Example 5 provides a VGA according to any of the foregoing examples, wherein each portion is associated with a corresponding differential output for providing a corresponding differential output signal (e.g., a first portion is coupled to a differential output terminal OUTP, and a second portion is coupled to a differential output terminal OUTN, as described herein), the transistor arrangement of a plurality of transistors includes a shared transistor (e.g., transistor N0 as described herein), and for each portion, a first end of the shared transistor of that portion is coupled to the differential output associated with that portion, and a second end of the shared transistor of that portion is coupled to the differential input associated with that portion.

[0134] Example 6 provides a VGA according to Example 5, in which, for each section, the third terminal of each of the first transistor, the second transistor, and the shared transistor is coupled to one or more bias voltages.

[0135] Example 7 provides a VGA according to any of the preceding examples, wherein the first and second transistors of the first portion and the first and second transistors of the second portion form a first gain step circuit, the transistor arrangement including a plurality of gain step circuits, each gain step circuit being implemented as a first gain step circuit, and the switching arrangement being configured to selectively operate the first and second transistors of each portion of each of the plurality of gain step circuits in either the first mode or the second mode.

[0136] Example 8 provides a VGA according to Example 7, wherein the switching arrangement is configured to selectively operate the first and second transistors of each portion of each of the plurality of gain step circuits in either the first or the second mode based on a control signal of each of the plurality of gain step circuits.

[0137] Example 9 provides a VGA according to any of the foregoing examples, wherein the first and second transistors of the first portion and the first and second transistors of the second portion form a first gain step circuit, the first mode and the second mode of any of the foregoing examples being the first mode and the second mode of the first gain step circuit, respectively, and the plurality of transistors arranged in each portion further include a third transistor (e.g., transistor N, as described herein but belonging to the second gain step circuit). 11 ,) and the fourth transistor (e.g., transistor N, as described herein but belonging to the second gain step circuit). 12The first portion of the second portion and the third and fourth transistors of the second portion form a second gain step circuit. Furthermore, the switching arrangement is configured to operate the third and fourth transistors of each portion in either a first mode or a second mode of the second gain step circuit. In the first mode of the second gain step circuit, the second terminal of the fourth transistor of the first portion is coupled to a differential input associated with the first portion, and the second terminal of the fourth transistor of the second portion is coupled to a differential input associated with the second portion; and in the second mode of the second gain step circuit, the second terminal of the fourth transistor of the first portion is coupled to a differential input associated with the second portion, and the second terminal of the fourth transistor of the second portion is coupled to a differential input associated with the first portion.

[0138] Example 10 provides a VGA configured to receive a differential input signal and generate an output signal based on the differential input signal and a desired gain. The VGA includes: a transistor arrangement comprising a plurality of transistors, each transistor having a first terminal, a second terminal, and a third terminal; and a switch arrangement wherein the transistor arrangement includes a first portion and a second portion (e.g., positive (P) and negative (N) sides of a differential circuit), each portion being associated (e.g., coupled to or having) a corresponding (i.e., different) differential output terminal for providing a respective differential output signal (e.g., the first portion is coupled to a differential output terminal OUTP, while the second portion is coupled to a differential output terminal OUTN, as described herein), and the plurality of transistors in each portion of the transistor arrangement includes a first transistor (e.g., transistor N as described herein). 11 ) and the second transistor (e.g., transistor N described herein) 12 Furthermore, the switching arrangement is configured to operate the first and second transistors of each portion in a first mode or a second mode, wherein in the first mode, a first terminal of the second transistor of the first portion is coupled to a differential output terminal associated with the first portion, and a first terminal of the second transistor of the second portion is coupled to a differential output terminal associated with the second portion; and in the second mode, a first terminal of the second transistor of the first portion is coupled to a differential output terminal associated with the second portion, and a first terminal of the second transistor of the second portion is coupled to a differential output terminal associated with the first portion.

[0139] Example 11 provides a VGA according to Example 10, wherein each section is associated with a corresponding (i.e. different) differential input for receiving a corresponding differential input signal, and for each section, a second terminal of each of the first and second transistors of that section is coupled to the differential input associated with that section, and a first terminal of the first transistor of that section is coupled to the differential output associated with that section.

[0140] Example 12 provides a VGA according to Example 10 or 11, wherein the plurality of transistors arranged therein include an input transistor (e.g., transistor M1 as described herein) in each section, and for each section, the second end of each of the first and second transistors of that section is coupled to the input transistor of that section.

[0141] Example 13 provides a VGA according to Example 12, wherein each portion is coupled to a differential input terminal INP as described herein for receiving a corresponding differential input signal (e.g., the first portion is coupled to the differential input terminal INP described herein and is configured to receive a first differential input signal (e.g., a bias voltage VB based on a transistor arrangement and an input voltage signal V). IN The sum of voltage signals V INP For example, V INP =VB+V IN Meanwhile, the second part is coupled to the differential input terminal INN described herein and is configured to receive a second differential input signal (e.g., a bias voltage VB based on a transistor arrangement and an input voltage signal V). IN The sum of voltage signals V INN For example, V INN =VB-V IN The corresponding (i.e. different) differential input terminals of the portion are associated (e.g., coupled to or have), and for each portion, the second terminal of each of the first and second transistors of that portion is coupled to the first terminal of the input transistor of that portion, and the third terminal of the input transistor of that portion is coupled to the differential input terminal associated with that portion.

[0142] Example 14 provides a VGA according to any one of Examples 10-13, wherein each portion is associated with a corresponding (i.e., different) differential input for receiving a corresponding differential input signal, and for each portion, a second terminal of each of the first and second transistors of that portion is coupled to the differential input associated with that portion, and a first terminal of the first transistor of that portion is coupled to a differential output associated with that portion, wherein each portion is associated with a corresponding (i.e., different) differential input for receiving a corresponding differential input signal, the plurality of transistors arranged in each portion include a shared transistor (e.g., transistor N0 as described herein), and for each portion, a first terminal of the shared transistor of that portion is coupled to the differential output associated with that portion, and a second terminal of the shared transistor of that portion is coupled to the differential input associated with that portion.

[0143] Example 15 provides a VGA according to Example 14, wherein for each section, the third terminal of each of the first transistor, the second transistor, and the shared transistor is coupled to one or more bias voltages.

[0144] Example 16 provides a VGA according to any one of Examples 10-15, wherein the first and second transistors of the first portion form a first gain step circuit with the first and second transistors of the second portion, the transistor arrangement including a plurality of gain step circuits, each gain step circuit being implemented as a first gain step circuit, and the switch arrangement being configured to selectively operate the first and second transistors of each portion of each of the plurality of gain step circuits in either the first mode or the second mode.

[0145] Example 17 provides a VGA according to Example 16, wherein the switching arrangement is configured to selectively operate the first and second transistors of each portion of each of the plurality of gain step circuits in either the first or the second mode based on a control signal of each of the plurality of gain step circuits.

[0146] Example 18 provides a VGA according to any of the preceding examples, wherein during operation, each of the first and second transistors of each portion is configured to conduct current, regardless of whether the first and second transistors of each portion are operating in the first mode or the second mode.

[0147] Example 19 provides a VGA according to any of the foregoing examples, wherein during operation, in a first mode, the current through the second transistor of the first portion and the current through the second transistor of the second portion increase the total current at the load, and in a second mode, the current through the second transistor of the first portion and the current through the second transistor of the second portion decrease the total current at the load. In this document, the terms "increase" and "decrease" are used to refer to the current due to the shared transistor N0 and the first transistor N in the first and second portions. 11 AC current in the load, the change of the total current (e.g., AC current) at the load relative to the current at the load.

[0148] Example 20 provides a VGA according to any one of Examples 1-19, wherein each of the plurality of transistors is an N-type transistor (e.g., an NMOS or NPN transistor).

[0149] Example 21 provides a VGA according to any of Examples 1-19, wherein each of the plurality of transistors is a P-type transistor (e.g., a PMOS or PNP transistor).

[0150] Example 22 provides a VGA according to any one of Examples 1-21, wherein each of the plurality of transistors is a FET (e.g., an NMOS or PMOS transistor), and for each FET, a first terminal is the drain terminal of the FET, a second terminal is the source terminal of the field-effect transistor, and a third terminal is the gate terminal of the field-effect transistor.

[0151] Example 23 provides a VGA according to any one of Examples 1-21, wherein each of the plurality of transistors is a BJT (e.g., an NPN or PNP transistor), and for each BJT, a first terminal is the collector terminal of the BJT, a second terminal is the emitter terminal of the BJT, and a third terminal is the base terminal of the BJT.

[0152] Example 24 provides a VGA configured to receive differential input signals and generate an output signal based on the differential input signals and a desired gain. The VGA includes: a transistor arrangement comprising a plurality of transistors; and a switch arrangement wherein the transistor arrangement includes a first portion and a second portion (e.g., positive (P) and negative (N) sides of a differential circuit), each portion being associated with a corresponding differential input for receiving a corresponding differential input signal and a corresponding differential output for providing a corresponding differential output signal, the plurality of transistors in each portion including a first transistor (e.g., transistor N described herein). 11 ) and the second transistor (e.g., transistor N described herein) 12 The switching arrangement is configured to operate the first and second transistors of each part in either a first mode or a second mode. Furthermore, for each part, in the first mode, the current through the second transistor of that part is added to the current through the first transistor of that part, and in the second mode, the current through the second transistor of that part is subtracted from the current through the first transistor of that part.

[0153] Example 25 provides a VGA according to Example 24, wherein during operation, each of the first and second transistors of each section is configured to conduct current, regardless of whether the first and second transistors of each section are operating in the first mode or the second mode.

[0154] Example 26 provides a VGA according to Example 24 or 25, wherein during operation, in a first mode, the current through the second transistor of the first part and the current through the second transistor of the second part increase the total current at the load, and in a second mode, the current through the second transistor of the first part and the current through the second transistor of the second part decrease the total current at the load.

[0155] Example 27 provides a VGA according to any one of Examples 24-26, wherein a plurality of transistors arranged in a transistor configuration include an input transistor (e.g., transistor M1 as described herein) in each section, and for each section, each of the first and second transistors of that section is coupled to the input transistor of that section.

[0156] Example 28 provides a VGA according to Example 27, wherein each of the plurality of transistors includes a first end, a second end, and a third end, and wherein for each portion, the first end of the input transistor of that portion is coupled to the second end of the first transistor of that portion.

[0157] Example 29 provides a VGA according to Example 28, wherein for each portion, the third terminal of each of the first transistor and the second transistor is coupled with one or more bias signals.

[0158] Example 30 provides a VGA according to any one of Examples 24-29, wherein each of the plurality of transistors includes a first terminal, a second terminal, and a third terminal. In this VGA, in a first mode, the first terminal of the second transistor of one portion is coupled to the first terminal of the first transistor of the other portion, and the second terminal of the second transistor of the other portion is coupled to the second terminal of the first transistor of the other portion; and in a second mode, either the first terminal of the second transistor of one portion is coupled to the first terminal of the first transistor of another portion, or the second terminal of the second transistor of one portion is coupled to the second terminal of the first transistor of another portion.

[0159] Example 31 provides an electronic device that includes a VGA according to any of the foregoing examples.

[0160] Example 32 provides an electronic device according to Example 31, wherein the electronic device is a beamformer of an RF transceiver.

[0161] Example 33 provides an electronic device according to Example 31, wherein the electronic device is an RF transceiver.

[0162] Example 34 provides an electronic device according to any one of Examples 31-33, wherein the electronic device is a base station of a wireless cellular network.

[0163] Example 35 provides an electronic device according to any one of Examples 31-33, wherein the electronic device is a transceiver of a wired communication network.

[0164] Change and Implementation

[0165] Although the above references Figure 1-8 The exemplary embodiments illustrated herein describe embodiments of this disclosure, but those skilled in the art will recognize that the various teachings described above are applicable to a wide range of other embodiments. In some cases, the features discussed herein may be applicable to automotive systems, medical systems, scientific instruments, wireless and wired communications, radio, radar, and remote sensing systems.

[0166] In the discussion of the above embodiments, system components, such as phase shifters, mixers, transistors, resistors, capacitors, amplifiers, and / or other components, can be readily replaced, substituted, or otherwise modified to suit specific circuit requirements. Furthermore, it should be noted that the use of complementary electronics, hardware, software, etc., provides equally feasible options for implementing the teachings of this disclosure in relation to the VGA with cross-coupled switch arrangement described herein.

[0167] Various parts of a system that can be implemented with one or more VGAs having the cross-coupled switch arrangement as presented herein may include electronic circuitry to perform the functions described herein. In some cases, one or more parts of the system may be provided by a processor specifically configured to perform the functions described herein. For example, the processor may include one or more dedicated components, or may include programmable logic gates configured to perform the functions described herein. The circuitry may operate in the analog domain, digital domain, or mixed-signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer-readable storage medium.

[0168] In one example embodiment, any number of circuits of this figure can be implemented on a board of an associated electronic device. This board can be a general-purpose circuit board that can house various components of the electronic device's internal electronic system and further provide connectors for other peripheral devices. More specifically, the board can provide electrical connections through which other components of the system can communicate electrically. Any suitable processor (including DSPs, microprocessors, supporting chipsets, etc.), computer-readable non-transitory storage elements, etc., can be appropriately coupled to the board according to specific configuration requirements, processing requirements, computer design, etc. Other components, such as external memory, additional sensors, controllers for audio / video displays, and peripheral devices, can be connected to the board via cables as plug-in cards or integrated into the board itself. In various embodiments, the functions described herein can be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) elements arranged in a structural configuration to support these functions. The emulated software or firmware can be provided on a non-transitory computer-readable storage medium comprising instructions that allow the processor to perform those functions.

[0169] In another example embodiment, the circuitry of this figure may be implemented as a standalone module (e.g., a device with associated components and circuitry configured to perform a specific application or function) or as a module plugged into dedicated hardware of an electronic device. Note that specific embodiments of this disclosure can be readily included, in part or in whole, in a SOC package. SOC stands for IC, which integrates components of a computer or other electronic system into a single chip. It may include digital, analog, mixed-signal, and typical RF functions: all of these functions can be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM), in which multiple individual ICs reside within a single electronic package and are configured to interact closely with each other via the electronic package.

[0170] It is also important to note that all specifications, dimensions, and relationships outlined here (e.g., Figure 1-8 The number of components shown in the system is for illustrative and teaching purposes only. Such information can vary considerably without departing from the spirit of this disclosure or the scope of the appended claims. It should be understood that the system can be combined in any suitable manner. Along similar design alternatives, any of the circuits, components, modules, and elements shown in this figure can be combined in a variety of possible configurations, all of which are clearly within the broad scope of this specification. In the foregoing description, exemplary embodiments have been described with reference to specific processor and / or component arrangements. Various modifications and changes can be made to these embodiments without departing from the scope of the appended claims. Therefore, the description and drawings are to be considered illustrative rather than restrictive.

[0171] It is equally important to note that the functions associated with the VGA with cross-coupled switch arrangement presented herein are only some of the possible functions that can be performed by or within the RF system. Some of these operations may be appropriately removed or eliminated, or these operations may be significantly modified or altered, without departing from the scope of this disclosure. The embodiments described herein offer substantial flexibility without departing from the teachings of this disclosure, as any suitable arrangement, timing sequence, configuration, and timing mechanism can be provided.

Claims

1. A variable gain amplifier VGA (200), comprising: A transistor arrangement comprising multiple transistors, each transistor having a first terminal, a second terminal, and a control terminal; and Switch layout, in: The transistor arrangement includes a first portion (210-1) and a second portion (210-2), wherein the first portion (210-1) includes a first input terminal (INP) configured to receive a first signal of a differential input signal and a first output terminal (OUTP) configured to provide a first signal of a differential output signal, wherein the second portion (210-2) includes a second input terminal (INN) configured to receive a second signal of the differential input signal and a second output terminal (OUTN) configured to provide a second signal of the differential output signal. The transistor arrangement comprises a first transistor (N) in each of the first portion (210-1) and the second portion (210-2). 11 ), second transistor (N 12 ) and shared transistor (N0), wherein the first transistor (N) in each of the first portion (210-1) and the second portion (210-2) 11 ), the second transistor (N) 12 The shared transistor (N0) and the cascaded transistor are cascaded transistors. Among them, the first transistor (N) of the first part (210-1) 11 ), the second transistor (N) 12 The first terminal of each of the shared transistors (N0) is coupled to the first output terminal (OUTP), and the first transistor (N) of the first portion (210-1) is coupled to the first output terminal (OUTP). 11 The second terminal of each of the shared transistors (N0) is coupled to the first input terminal (INP). Among them, the first transistor (N) in the second part (210-2) 11 ), the second transistor (N) 12 The first terminal of each of the shared transistors (N0) is coupled to the second output terminal (OUTN), and the first transistor (N) of the second portion (210-2) is coupled to the second output terminal (OUTN). 11 The second terminal of each of the shared transistors (N0) is coupled to the second input terminal (INN), and The switching arrangement is configured to operate the first transistor (N) of each part of the first portion (210-1) and the second portion (210-2) in a first mode or a second mode. 11 ) and the second transistor (N) 12 ),in: In the first mode, the second transistor (N) of the first part (210-1) 12 The second terminal of the second part (210-2) is coupled to the first input terminal (INP), and the second transistor (N) of the second part (210-2) 12 The second terminal of ) is coupled to the second input terminal (INN), and In the second mode, the second transistor (N) of the first part (210-1) 12 The second terminal of the second part (210-1) is coupled to the second input terminal (INN), and the second transistor (N) of the second part (210-1) 12 The second terminal of the input terminal is coupled to the first input terminal (INP).

2. The variable gain amplifier VGA (200) according to claim 1, wherein: The transistor arrangement includes an input transistor (M1) in each of the first portion (210-1) and the second portion (210-2). For the first part (210-1), the first transistor (N) of the first part (210-1) 11 The second terminal of the first part (210-1) is coupled to the first input terminal (INP) via the input transistor (M1) of the first part (210-1). For the second part (210-2), the first transistor (N) of the second part (210-2) 11 The second terminal of the second part (210-2) is coupled to the second input terminal (INN) via the input transistor (M1) of the second part (210-2). In the first mode, the second transistor (N) of the first part (210-1) 12 The second terminal of the first part (210-1) is coupled to the first input terminal (INP) via the input transistor (M1) of the first part (210-1), and the second transistor (N) of the second part (210-2) 12 The second terminal of the second part (210-2) is coupled to the second input terminal (INN) via the input transistor (M1) of the second part (210-2). In the second mode, the second transistor (N) of the first part (210-1) 12 The second terminal of the second part (210-2) is coupled to the second input terminal (INN) via the input transistor (M1) of the second part (210-2), and the second transistor (N) of the second part (210-2) 12 The second terminal of the first part (210-1) is coupled to the first input terminal (INP) via the input transistor (M1) of the first part (210-1).

3. The variable gain amplifier VGA (200) according to claim 1, wherein: The first transistor (N) of the first part (210-1) 11 ) and second transistor (N 12 ) and the first transistor (N) of the second part (210-2) 11 ) and second transistor (N 12 This forms the first gain step circuit. The transistor arrangement includes multiple gain step circuits, each of which is implemented as the first gain step circuit, and The switching arrangement is configured to selectively operate the first transistor (N) of each portion of the first part (210-1) and the second part (210-2) of each of the plurality of gain step circuits in either the first mode or the second mode. 11 ) and second transistor (N 12 ).

4. The variable gain amplifier VGA (200) according to claim 1, wherein: The first transistor (N) of the first part (210-1) 11 ) and second transistor (N 12 ) and the first transistor (N) of the second part (210-2) 11 ) and second transistor (N 12 This forms the first gain step circuit. The first mode and the second mode are respectively the first mode and the second mode of the first gain step circuit. The transistor arrangement further includes a third transistor and a fourth transistor in each of the first portion (210-1) and the second portion (210-2). The third and fourth transistors of the first part (210-1) and the third and fourth transistors of the second part (210-2) form a second gain step circuit, and The switching arrangement is configured to operate the third and fourth transistors of each part of the first portion (210-1) and the second portion (210-2) in either a first or second mode of the second gain step circuit, wherein: In the first mode of the second gain step circuit, the second terminal of the fourth transistor in the first portion (210-1) is coupled to the first input terminal (INP), and the second terminal of the fourth transistor in the second portion (210-2) is coupled to the second input terminal (INN). In the second mode of the second gain step circuit, the second terminal of the fourth transistor of the first part (210-1) is coupled to the second input terminal (INN), and the second terminal of the fourth transistor of the second part (210-2) is coupled to the first input terminal (INP).

5. A variable gain amplifier VGA (200), comprising: A transistor arrangement comprising multiple transistors, each transistor having a first terminal, a second terminal, and a control terminal; and Switch layout, in: The transistor arrangement includes a first portion (210-1) and a second portion (210-2), wherein the first portion (210-1) includes a first input terminal (INP) configured to receive a first signal of a differential input signal and a first output terminal (OUTP) configured to provide a first signal of a differential output signal, wherein the second portion (210-2) includes a second input terminal (INN) configured to receive a second signal of the differential input signal and a second output terminal (OUTN) configured to provide a second signal of the differential output signal. The transistor arrangement comprises a first transistor (N) in each of the first portion (210-1) and the second portion (210-2). 11 ), second transistor (N 12 ) and shared transistor (N0), Wherein, the first transistor (N) in each of the first part (210-1) and the second part (210-2) 11 ), the second transistor (N) 12 The shared transistor (N0) and the cascaded transistor are cascaded transistors. Wherein, the first terminal of the shared transistor (N0) of the first part (210-1) is coupled to the first output terminal (OUTP) and the second terminal of the shared transistor (N0) of the first part (210-1) is coupled to the first input terminal (INP), and wherein the first transistor (N0) of the first part (210-1) 11 ) and second transistor (N 12 The second terminal of each of the first portions (210-1) is coupled to the first input terminal (INP), and the first transistor (N) of the first portion (210-1) 11 The first terminal of the device is coupled to the first output terminal (OUTP). In this configuration, the first terminal of the shared transistor (N0) of the second part (210-2) is coupled to the second output terminal (OUTN), and the second terminal of the shared transistor (N0) of the second part (210-2) is coupled to the second input terminal (INN). Furthermore, for the second part (210-2), the first transistor (N0) of the second part (210-2)... 11 ) and second transistor (N 12 The second terminal of each of the two portions (210-2) is coupled to the second input terminal (INN), and the first transistor (N) of the second portion (210-2) 11 The first terminal of the output is coupled to the second output terminal (OUTN), and The switching arrangement is configured to operate the first transistor (N) of each of the first portion (210-1) and the second portion (210-2) in either a first mode or a second mode. 11 ) and second transistor (N 12 ),in: In the first mode, the second transistor (N) of the first part (210-1) 12 The first terminal of the second part (210-2) is coupled to the first output terminal (OUTP), and the second transistor (N) of the second part (210-2) 12 The first terminal of the output is coupled to the second output terminal (OUTN), and In the second mode, the second transistor (N) of the first part (210-1) 12 The first terminal of the second part (210-2) is coupled to the second output terminal (OUTN), and the second transistor (N) of the second part (210-2) 12 The first terminal of the device is coupled to the first output terminal (OUTP).

6. The variable gain amplifier VGA (200) according to claim 5, wherein: The transistor arrangement includes multiple transistors, each comprising an input transistor (M1) in each of the first portion (210-1) and the second portion (210-2), and For the first part (210-1), the first transistor (N) of the first part (210-1) 11 ) and second transistor (N 12 The second terminal of each of the components is coupled to the input transistor (M1) of the first part (210-1); and For the second part (210-2), the first transistor (N) of the second part (210-2) 11 ) and second transistor (N 12 The second terminal of each of the two portions (210-2) is coupled to the input transistor (M1) of the second portion (210-2).

7. The variable gain amplifier VGA (200) according to claim 6, wherein: For the first part (210-1), the first transistor (N) of the first part (210-1) 11 ) and second transistor (N 12 The second terminal of each of the components is coupled to the first terminal of the input transistor (M1) of the first part (210-1), and the control terminal of the input transistor (M1) of the first part (210-1) is coupled to the first input terminal (INP); and For the second part (210-2), the first transistor (N) of the second part (210-2) 11 ) and second transistor (N 12 The second terminal of each of the two portions (210-2) is coupled to the first terminal of the input transistor (M1) of the second portion (210-2), and the control terminal of the input transistor (M1) of the second portion (210-2) is coupled to the second input terminal (INN).

8. The variable gain amplifier VGA (200) according to claim 5, wherein: The first transistor (N) of the first part (210-1) 11 ) and second transistor (N 12 ) and the first transistor (N) of the second part (210-2) 11 ) and second transistor (N 12 This forms the first gain step circuit. The transistor arrangement includes multiple gain step circuits, each of which is implemented as the first gain step circuit, and The switching arrangement is configured to selectively operate the first transistor (N) of each portion of the first part (210-1) and the second part (210-2) of each of the plurality of gain step circuits in either the first mode or the second mode. 11 ) and second transistor (N 12 ).

9. The variable gain amplifier VGA (200) according to claim 5, wherein, During operation, the first transistor (N) of each of the first portion (210-1) and the second portion (210-2) 11 ) and second transistor (N 12 Each of the first transistors (N) in the first part (210-1) and the second part (210-2) is configured to conduct current, regardless of the first transistor (N) in each part of the first part (210-1) and the second part (210-2). 11 ) and second transistor (N 12 Whether to operate in the first mode or the second mode.

10. The variable gain amplifier VGA (200) according to claim 5, wherein, During operation: In the first mode, the second transistor (N) of the first part (210-1) 12 The current and the second transistor (N) through the second part (210-2) 12 The current increases the total current at the load, and In the second mode, the second transistor (N) of the first part (210-1) 12 The current and the second transistor (N) through the second part (210-2) 12 The current at the load is reduced by the current of the load.

11. A variable gain amplifier VGA (200), comprising: A transistor arrangement comprising multiple transistors, each transistor having a first terminal, a second terminal, and a control terminal; and Switch layout, in: The transistor arrangement includes a first portion (210-1) and a second portion (210-2), wherein the first portion (210-1) includes a first input terminal (INP) configured to receive a first signal of a differential input signal and a first differential output current (I0) configured to provide a first differential output current (I0). OUTP The first output terminal (OUTP) of the differential input signal, wherein the second part (210-2) includes a second input terminal (INN) configured to receive a second signal of the differential input signal and a second differential output current (I) configured to provide a second differential output current. OUTN The second output terminal (OUTN); The transistor arrangement comprises a first transistor (N) in each of the first portion (210-1) and the second portion (210-2). 11 ), second transistor (N 12 ) and shared transistor (N0), wherein the first transistor (N) in each of the first portion (210-1) and the second portion (210-2) 11 ), the second transistor (N) 12 The shared transistor (N0) and the cascaded transistor are cascaded transistors. Among them, the first transistor (N) of the first part (210-1) 11 ), the second transistor (N) 12 The first terminal of each of the shared transistors (N0) is coupled to the first output terminal (OUTP), and the first transistor (N) of the first portion (210-1) 11 The second terminal of each of the transistors (N0) and the shared transistor (N0) is coupled to the first input terminal (INP). Among them, the first transistor (N) in the second part (210-2) 11 ), the second transistor (N) 12 The first terminal of each of the shared transistors (N0) is coupled to the second output terminal (OUTN), and the first transistor (N) of the second part (210-2) is coupled to the second output terminal (OUTN). 11 The second terminal of each of the shared transistors (N0) is coupled to the second input terminal (INN), and The switching arrangement is configured to operate the first transistor (N) of each of the first portion (210-1) and the second portion (210-2) in either a first mode or a second mode. 11 ) and second transistor (N 12 ),in: In the first mode, the second transistor (N) of the first part (210-1) 12 The current is added to the first transistor (N) passing through the first part (210-1). 11 The current flows through the second transistor (N) of the second part (210-2). 12 The current is added to the first transistor (N) through the second part (210-2). 11 The current of ) and In the second mode, from the first transistor (N) through the first part (210-1) 11 The current of the second transistor (N) passing through the first part (210-1) is subtracted from the current of the first part (210-1). 12 The current flows from the first transistor (N) through the second part (210-2). 11 The current of the second transistor (N) passing through the second part (210-2) is subtracted from the current of the second transistor (N). 12 The current.

12. The variable gain amplifier VGA (200) according to claim 11, wherein, During operation, the first transistor (N) of each of the first portion (210-1) and the second portion (210-2) 11 ) and second transistor (N 12 Each of the first transistors (N) in the first part (210-1) and the second part (210-2) is configured to conduct current, regardless of the first transistor (N) in each part of the first part (210-1) and the second part (210-2). 11 ) and second transistor (N 12 Whether to operate in the first mode or the second mode.

13. The variable gain amplifier VGA (200) according to claim 11, wherein, During operation: In the first mode, the second transistor (N) of the first part (210-1) 12 The current and the second transistor (N) through the second part (210-2) 12 The current increases the total current at the load, and In the second mode, the second transistor (N) of the first part (210-1) 12 The current and the second transistor (N) through the second part (210-2) 12 The current at the load is reduced by the current of the load.

14. The variable gain amplifier VGA (200) according to claim 11, wherein: The transistor arrangement includes multiple transistors, each comprising an input transistor (M1) in each of the first portion (210-1) and the second portion (210-2), and For the first part (210-1), the first transistor (N) of the first part (210-1) 11 The second terminal of the first part (210-1) is coupled to the first input terminal (INP) via the input transistor (M1) of the first part (210-1). For the second part (210-2), the first transistor (N) of the second part (210-2) 11 The second terminal of the second part (210-2) is coupled to the second input terminal (INN) via the input transistor (M1) of the second part (210-2).

15. The variable gain amplifier VGA (200) according to claim 14, wherein: For the first part (210-1), the first terminal of the input transistor (M1) of the first part (210-1) is coupled to the first transistor (N) of the first part (210-1). 11 The second terminal of ) For the second part (210-2), the first terminal of the input transistor (M1) of the second part (210-2) is coupled to the first transistor (N) of the second part (210-2). 11 The second terminal of ) For the first part (210-1), the first transistor (N) of the first part (210-1) 11 ) and the second transistor (N) 12 Each of the control terminals in the array is coupled to one or more bias signals, and For the second part (210-2), the first transistor (N) of the second part (210-2) 11 ) and the second transistor (N) 12 Each of the control terminals in the array is coupled to one or more bias signals.

16. The variable gain amplifier VGA (200) according to claim 11, wherein: In the first mode, the second transistor (N) of the first part (210-1) 12 The first terminal of the first part (210-1) is coupled to the first transistor (N). 11 The first terminal of the first portion (210-1) and the second transistor (N) 12 The second terminal of ) is coupled to the first transistor (N) of the first part (210-1). 11 The second terminal of the second part (210-2), the second transistor (N) 12 The first terminal of ) is coupled to the first transistor (N) of the second part (210-2). 11 The first terminal of the second part (210-2) and the second transistor (N) 12 The second terminal of ) is coupled to the first transistor (N) of the second part (210-2). 11 The second terminal of ) and In the second mode, or the second transistor (N) of the first part (210-1) 12 The first terminal of ) is coupled to the first transistor (N) of the second part (210-2). 11 The first terminal of the second part (210-2) and the second transistor (N) 12 The first terminal of the first part (210-1) is coupled to the first transistor (N). 11 The first terminal of ), or the second transistor (N) of the first part (210-1) 12 The second terminal of ) is coupled to the first transistor (N) of the second part (210-2). 11 The second terminal of the second part (210-2) and the second transistor (N) 12 The second terminal of ) is coupled to the first transistor (N) of the first part (210-1). 11 The second terminal of ).

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