A common mode transient disturbance suppression circuit, isolator

Abstract

The application discloses a common-mode transient interference suppression circuit and an isolator, and belongs to the technical field of signal transmission. The common-mode transient interference suppression circuit comprises a first-stage high-pass filter, a second-stage high-pass filter, a signal demodulation circuit and a common-mode detection circuit arranged between the first-stage high-pass filter and the second-stage high-pass filter in series connection. The first-stage high-pass filter and the second-stage high-pass filter are used for filtering input signals of a signal receiving end in sequence, outputting differential signals and providing a current discharge channel when common-mode transient interference occurs. The common-mode detection circuit is used for detecting the differential signals, generating a common-mode transient detection result signal and outputting the common-mode transient detection result signal to the signal demodulation circuit. The signal demodulation circuit is used for demodulating the differential signals according to the common-mode transient detection result signal, and obtaining original signals. The application can effectively suppress signal decoding abnormity caused by common-mode transient interference, and improve the anti-common-mode transient interference capability of the isolator.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a common-mode transient interference suppression circuit, and also relates to an isolator. BACKGROUND

[0002] The isolator is an intermediate circuit between the signal output end and the signal receiving end, commonly used to deal with the problem that the two sides of the isolator do not share the ground, so that the circuits in different voltage domains can keep communication, while preventing mutual interference between the circuits in different voltage domains. When the reference ground on one side of the isolator is dithered, common-mode transient interference will be generated, which may affect the accuracy of the signal transmission of the isolation channel.

[0003] The traditional scheme for dealing with common-mode transient interference in the isolator is to use a differential structure and an ON-OFF Keying (OOK) encoding mode, and a structural diagram thereof is shown in Figure 1 The isolator mainly includes a sending circuit 1 and a receiving circuit 2. The differential outputs of a signal modulation circuit 101 of the sending circuit 1 are connected with isolation capacitors Ciso1 and Ciso3 respectively. Isolation capacitors Ciso2 and Ciso4 are connected with a node Vin1 and a node Vin2 of the receiving circuit 2. The node Vin1 is connected with a capacitor C1 and a resistor R1 respectively. The node Vin2 is connected with a capacitor C2 and a resistor R2 respectively. The differential signals transmitted by the capacitors C1 and C2 are connected with input ends VINN and VINP of a differential amplifier 102 respectively, and are also connected with resistors R3 and R4 respectively. When common-mode interference occurs between a signal sending end ground TGND and a signal receiving end ground RGND, the capacitors C1 and C2 and the resistors R1, R2, R3 and R4 play a role in reducing the common-mode interference. However, due to the limited common-mode input range of the differential structure, when the common-mode interference is very large, the common-mode voltage at the input end of the differential amplifier 102 will exceed the input common-mode voltage range, resulting in errors in the transmission signal. SUMMARY

[0004] The common-mode transient interference suppression circuit and the isolator provided by the embodiments of the present application can effectively suppress the signal decoding abnormality caused by common-mode transient interference, and improve the anti-common-mode transient interference capability of the isolator.

[0005] The common-mode transient interference suppression circuit provided by the embodiments of the present application comprises a first-stage high-pass filter, a second-stage high-pass filter and a signal demodulation circuit connected in series, and a common-mode detection circuit arranged between the first-stage high-pass filter and the second-stage high-pass filter.

[0006] The first-stage high-pass filter and the second-stage high-pass filter are used to filter the input signal of the signal receiving end in sequence, output a differential signal, and provide a current discharge channel when common-mode transient interference occurs.

[0007] The common mode detection circuit is configured to detect the differential signal, generate a common mode transient detection result signal, and output the common mode transient detection result signal to the signal demodulation circuit.

[0008] The signal demodulation circuit is configured to demodulate the differential signal according to the common mode transient detection result signal to obtain an original signal.

[0009] Optionally, the common mode detection circuit comprises a sink current detection unit, a flood current detection unit, and a logic processing unit.

[0010] The flood current detection unit is configured to detect whether current is flooded from the signal transmitting end to the signal receiving end, and output a flood current detection result to the logic processing unit.

[0011] The sink current detection unit is configured to detect whether current is flowed from the signal receiving end to the signal transmitting end, and output a sink current detection result to the logic processing unit.

[0012] The logic processing unit is configured to process the flood current detection result and the sink current detection result, and output the common mode transient detection result signal.

[0013] Optionally, the signal demodulation circuit comprises a threshold adjustment unit, a signal demodulation unit, and a buffer BUF1 connected in sequence.

[0014] The threshold adjustment unit is configured to adjust a demodulation threshold according to the common mode transient detection result signal.

[0015] The signal demodulation unit is configured to demodulate the differential signal according to the adjusted demodulation threshold to obtain an original signal.

[0016] The buffer BUF1 is configured to convert an analog signal output by the signal demodulation unit into a digital signal and increase driving capability.

[0017] Optionally, the first-stage high-pass filter comprises a second isolation capacitor Ciso2 and a fourth isolation capacitor Ciso4, a first resistor R1 and a second resistor R2 connected in series; upper plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 are connected to the signal transmitting end respectively, a lower plate of the second isolation capacitor Ciso2 is connected to one end of the first resistor R1 and a first input end of the common mode detection circuit simultaneously, a lower plate of the fourth isolation capacitor Ciso4 is connected to one end of the second resistor R2 and a second input end of the common mode detection circuit simultaneously; and a common end of the first resistor R1 and the second resistor R2 is connected to a reference ground RGND of the signal receiving end.

[0018] The second-stage high-pass filter comprises a first capacitor C1 and a second capacitor C2, a third resistor R3 and a fourth resistor R4 connected in series, the upper plates of the first capacitor C1 and the second capacitor C2 are connected to the lower plates of a second isolation capacitor Ciso2 and a fourth isolation capacitor Ciso4 respectively, the lower plate of the first capacitor C1 is connected to one end of the third resistor R3, the lower plate of the second capacitor C2 is connected to one end of the fourth resistor R4, and the common end of the third resistor R3 and the fourth resistor R4 is connected to a common mode level Vcm.

[0019] Optionally, the sink current detection unit comprises a pull-down current source I1, a first PMOS tube P1 and a second PMOS tube P2, the sources of the first PMOS tube P1 and the second PMOS tube P2 are connected to a power supply VDD of a receiving circuit respectively, the gate of the first PMOS tube P1 is connected to a first input end of the common mode detection circuit through a third capacitor C3 and connected to the power supply VDD through a fifth resistor R5, the gate of the second PMOS tube P2 is connected to a second input end of the common mode detection circuit through a fifth capacitor C5 and connected to the power supply VDD through a seventh resistor R7, the drains of the first PMOS tube P1 and the second PMOS tube P2 are connected to the pull-down current source I1 respectively, and the sink current detection result is output.

[0020] The sink current detection unit comprises a pull-down current source I1, a first PMOS tube P1 and a second PMOS tube P2, the sources of the first PMOS tube P1 and the second PMOS tube P2 are connected to a power supply VDD of a receiving circuit respectively, the gate of the first PMOS tube P1 is connected to a first input end of the common mode detection circuit through a third capacitor C3 and connected to the power supply VDD through a fifth resistor R5, the gate of the second PMOS tube P2 is connected to a second input end of the common mode detection circuit through a fifth capacitor C5 and connected to the power supply VDD through a seventh resistor R7, the drains of the first PMOS tube P1 and the second PMOS tube P2 are connected to the pull-down current source I1 respectively, and the sink current detection result is output.

[0021] Optionally, the logic processing unit comprises a first inverter INV1 and an or gate OR1.

[0022] The output of the pull-down current source I1 is connected to one input end of the or gate OR1, the output of the pull-up current source I2 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the other input end of the or gate OR1, and the or gate OR1 outputs the common mode transient detection result signal.

[0023] Optionally, the threshold adjusting unit comprises a second inverter INV2, a NOR gate NOR1, an AND gate AND1, a fifth NMOS transistor N703 and a sixth NMOS transistor N702.

[0024] One input terminal of the AND gate AND1 is connected to an output terminal VOUT of the buffer BUF1, and another input terminal of the AND gate AND1 is connected to an output terminal of the common mode detection circuit.

[0025] An input terminal of the second inverter INV2 is connected to the output terminal of the common mode detection circuit.

[0026] One input terminal of the NOR gate NOR1 is connected to the output terminal of the buffer BUF1, and another input terminal of the NOR gate NOR1 is connected to an output terminal of the second inverter INV2.

[0027] A source of the fifth NMOS transistor N703 is connected to a first current source I701, a gate of the fifth NMOS transistor N703 is connected to an output terminal of the AND gate AND1, and a drain of the fifth NMOS transistor N703 is an output terminal VON of the threshold adjusting unit.

[0028] A source of the sixth NMOS transistor N702 is connected to a second current source I702, a gate of the sixth NMOS transistor N702 is connected to an output terminal of the NOR gate NOR1, and a drain of the sixth NMOS transistor N702 is another output terminal VO of the threshold adjusting unit.

[0029] Optionally, the signal demodulating unit comprises a third PMOS transistor P700, a fourth PMOS transistor P701, a third NMOS transistor N700, a fourth NMOS transistor N701 and a tail current source I703.

[0030] The source of the third PMOS transistor P700 and the source of the fourth PMOS transistor P701 are both connected to the power supply VDD, the drain and the gate of the third PMOS transistor P700 are shorted to an output terminal VON of the threshold adjusting unit, the gate of the fourth PMOS transistor P701 is connected to the output terminal VON of the threshold adjusting unit, and the drain of the fourth PMOS transistor P701 is connected to another output terminal VO of the threshold adjusting unit.

[0031] The source of the third NMOS tube N700 and the source of the fourth NMOS tube N701 are connected to a tail current source I703, one end of the tail current source I703 is grounded; the gate of the third NMOS tube N700 is used for inputting the differential signal, and the drain of the third NMOS tube N700 is connected to one output end VON of the threshold adjustment unit; the gate of the fourth NMOS tube N701 is used for inputting a demodulation threshold voltage Vref, and the drain of the fourth NMOS tube N701 is connected to another output end VO of the threshold adjustment unit.

[0032] The input end of the buffer BUF1 is connected to the other output end VO of the threshold adjustment unit.

[0033] Optionally, the third NMOS tube N700 is composed of two NMOS structure units, and the gates of the two NMOS structure units are different, and the source and the drain of the two NMOS structure units are short-circuited.

[0034] The embodiment of the present application further provides an isolator, which comprises: a sending circuit 1 and a receiving circuit 2; the sending circuit 1 comprises a signal modulation circuit, a first isolation capacitor Ciso1 and a third isolation capacitor Ciso3, and the output of the signal modulation circuit is connected to the lower plate of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 respectively; the receiving circuit 2 comprises the common-mode transient interference suppression circuit according to any one of claims 1 to 9.

[0035] Optionally, the receiving circuit 2 further comprises a differential amplifier arranged between the second-order high-pass filter and the signal demodulation circuit.

[0036] The common-mode transient interference suppression circuit and the isolator provided by the embodiment of the present application can distinguish the common-mode transient event from the normal signal transmission by detecting the current generated by the positive and negative common-mode transient interference respectively through the common-mode transient interference detection circuit, accurately detect the common-mode transient interference, and meanwhile, do not affect the signal transmission when there is no common-mode transient interference. When the common-mode transient interference is detected, the equivalent threshold voltage can follow the change trend of the signal by compensating the threshold voltage of the demodulation circuit, so that the signal decoding abnormality caused by the common-mode transient interference can be suppressed, and the anti-common-mode transient interference capability of the isolator is improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 is a structure schematic diagram of an isolator adopting a differential structure in the prior art;

[0038] Figure 2 is a common-mode transient interference and common-mode current waveform schematic diagram generated in the isolator adopting a differential structure in the prior art;

[0039] Figure 3 is a principle block diagram of the common-mode transient interference suppression circuit of the embodiment of the present application;

[0040] Figure 4 is a specific structure diagram of the common-mode transient interference suppression circuit of the embodiment of the present application;

[0041] Figure 5 is a principle block diagram of the common-mode detection circuit of the embodiment of the present application;

[0042] Figure 6 is a specific structure diagram of the common-mode detection circuit of the embodiment of the present application;

[0043] Figure 7 is a principle block diagram of the signal demodulation circuit of the embodiment of the present application;

[0044] Figure 8 is a specific structure diagram of the signal demodulation circuit of the embodiment of the present application;

[0045] Figure 9 is a working flow chart of the signal demodulation circuit of the embodiment of the present application;

[0046] Figure 10 is a structure diagram of the isolator of the embodiment of the present application;

[0047] Figure 11 is a detection waveform diagram of the common-mode detection circuit of the embodiment of the present application;

[0048] Figure 12 is a waveform diagram of the traditional isolator when affected by common-mode transient interference;

[0049] Figure 13 is a waveform diagram of the isolator of the embodiment of the present application when affected by common-mode transient interference. DETAILED DESCRIPTION

[0050] In order to make the above objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a thorough understanding of several embodiments of the present application. However, it will be apparent to one skilled in the art that at least some embodiments of the present application can be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram format in order to avoid unnecessarily obscuring the present application. Thus, the specific details set forth are merely exemplary. Particular implementations can vary from these exemplary details and still be contemplated to be within the scope of the present application.

[0052] For the capacitor isolation type isolator, when the transient occurs on the ground potential on both sides of the isolator, the voltage domain of the transmitting circuit or the receiving circuit will change, resulting in voltage mutation on both sides of the isolation capacitor, and common-mode current I CMT As shown in Figure 2 , the common-mode current I CMT is calculated as follows:

[0053]

[0054] During the rise of the signal transmitting end ground TGND, the generated current will flow from the transmitting circuit 1 to the receiving circuit 2 through the isolation capacitor, and during the fall of the signal transmitting end ground TGND, the generated current will flow from the receiving circuit 2 to the transmitting circuit 1, as shown in Figure 2 .

[0055] For the traditional isolator using differential structure, when the common-mode interference is large, it will cause the transmission signal to appear error, therefore, the embodiment of the present application provides a common-mode transient interference suppression circuit and an isolator, a common-mode detection circuit is added, the currents generated by the positive and negative common-mode transient interference are detected respectively, when the common-mode transient interference is detected, the threshold voltage of the demodulation circuit is compensated, so that the equivalent threshold voltage follows the change trend of the signal, thereby suppressing the signal decoding abnormality caused by the common-mode transient interference, and improving the anti-common-mode transient interference ability of the isolator.

[0056] As shown in Figure 3 , it is a structure schematic diagram of the common-mode transient interference suppression circuit of the embodiment of the present application.

[0057] The common-mode transient interference suppression circuit comprises a first-stage high-pass filter 205, a second-stage high-pass filter 206, a signal demodulation circuit 203, and a common-mode detection circuit 204 arranged between the first-stage high-pass filter 205 and the second-stage high-pass filter 206. For the convenience of description, one connection point of the common-mode detection circuit 204 is marked as Vin1, which will be referred to as the first input end Vin1 of the common-mode detection circuit 204 in the subsequent description, and the other connection point is marked as Vin2, which will be referred to as the second input end Vin2 of the common-mode detection circuit 204 in the subsequent description. Wherein:

[0058] The first-stage high-pass filter 205 and the second-stage high-pass filter 206 are used for filtering the input signal of the signal receiving end in sequence, outputting a differential signal, and providing a current discharge channel when common-mode transient interference occurs;

[0059] The common-mode detection circuit 204 is used for detecting the differential signal, generating a common-mode transient detection result signal CMT_DETECT and outputting to the signal demodulation circuit 203;

[0060] The signal demodulation circuit 203 is configured to demodulate the differential signal according to the common-mode transient detection result signal to obtain an original signal.

[0061] Figure 4 A specific structure diagram of the common-mode transient interference suppression circuit according to an embodiment of the application is shown.

[0062] In this embodiment, the signal transmitting end transmits the differential output signal to the signal receiving end through the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3, and the ground of the signal transmitting end is denoted as TGND, and the ground of the signal receiving end is denoted as RGND.

[0063] Referring to Figure 3 and Figure 4 , the first-stage high-pass filter 205 includes the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4, and the first resistor R1 and the second resistor R2 connected in series; the upper plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 are connected to the upper plates of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 of the signal transmitting end respectively, the lower plate of the second isolation capacitor Ciso2 is connected to one end of the first resistor R1 and the first input end Vin1 of the common-mode detection circuit 204 simultaneously, and the lower plate of the fourth isolation capacitor Ciso4 is connected to one end of the second resistor R2 and the second input end Vin2 of the common-mode detection circuit 204 simultaneously; the common end of the first resistor R1 and the second resistor R2 is connected to the reference ground RGND of the signal receiving end. The second-stage high-pass filter 206 includes the first capacitor C1 and the second capacitor C2, and the third resistor R3 and the fourth resistor R4 connected in series; the upper plates of the first capacitor C1 and the second capacitor C2 are connected to the lower plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 respectively, the lower plate of the first capacitor C1 is connected to one end of the third resistor R3, the lower plate of the second capacitor C2 is connected to one end of the fourth resistor R4, and the common end of the third resistor R3 and the fourth resistor R4 is connected to the common-mode level Vcm.

[0064] As shown in Figure 5 , it is a principle block diagram of the common-mode detection circuit according to an embodiment of the application. In this example, the common-mode detection circuit 204 includes the fill-in current detection unit 401, the draw-in current detection unit 402, and the logic processing unit 403. Wherein:

[0065] The fill-in current detection unit 401 is configured to detect whether there is current filled in from the signal transmitting end to the signal receiving end, and output the fill-in current detection result to the logic processing unit 403;

[0066] The draw-in current detection unit 402 is configured to detect whether there is current drawn from the signal receiving end to the signal transmitting end, and output the draw-in current detection result to the logic processing unit 403;

[0067] The logic processing unit 403 is configured to process the filling current detection result and the drawing current detection result, and output the common mode transient detection result signal CMT_DETECT.

[0068] Figure 6 A specific structure diagram of the common mode detection circuit in the embodiment of the application is shown.

[0069] Referring to Figure 5 and Figure 6 simultaneously, the drawing current detection unit 402 comprises a pull-down current source I1, a first PMOS tube P1 and a second PMOS tube P2. The source of the first PMOS tube P1 and the source of the second PMOS tube P2 are respectively connected to the power supply VDD of the receiving circuit, the gate of the first PMOS tube P1 is connected to the first input end Vin1 of the common mode detection circuit through the third capacitor C3 and connected to the power supply VDD through the fifth resistor R5, the gate of the second PMOS tube P2 is connected to the second input end Vin2 of the common mode detection circuit through the fifth capacitor C5 and connected to the power supply VDD through the seventh resistor R7, the drain of the first PMOS tube P1 and the drain of the second PMOS tube P2 are respectively connected to the pull-down current source I1, and the drawing current detection result is outputted.

[0070] Continuing to refer to Figure 5 and Figure 6 , the filling current detection unit 401 comprises a pull-up current source I2, a first NMOS tube N1 and a second NMOS tube N2. The source of the first NMOS tube N1 and the source of the second NMOS tube N2 are respectively connected to the reference ground RGND of the receiving circuit, the gate of the first NMOS tube N1 is connected to the first input end Vin1 of the common mode detection circuit through the fourth capacitor C4 and connected to the reference ground RGND of the receiving circuit through the sixth resistor R6, the gate of the second NMOS tube N2 is connected to the second input end Vin2 of the common mode detection circuit through the sixth capacitor C6 and connected to the reference ground RGND of the receiving circuit through the eighth resistor R8, the drain of the first NMOS tube N1 and the drain of the second NMOS tube N2 are respectively connected to the pull-up current source I2, and the filling current detection result is outputted.

[0071] As shown in Figure 6 , the other end of the pull-down current source I1 is connected to the reference ground RGND, and the other end of the pull-up current source I2 is connected to the power supply VDD.

[0072] Figure 6In the formula, I4 and I3 respectively represent currents generated by the first PMOS tube P1, the second PMOS tube P2 and the first NMOS tube N1, the second NMOS tube N2, I4 and I3 are both 0 when there is no common-mode transient interference, and I4 and I3 are not 0 when there is common-mode transient interference.

[0073] The pull-down current source I1 and the pull-up current source I2 correspond to two threshold values, and the potentials of the nodes A and B depend on the size relationship between I4 and I1 and I2 and I3.

[0074] Continuing to refer to Figure 5 and Figure 6 , the logic processing unit 403 comprises a first inverter INV1 and an OR gate OR1. In which, the output of the pull-down current source I1 is connected to one input end of the OR gate OR1; the output of the pull-up current source I2 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the other input end of the OR gate OR1; the OR gate OR1 outputs the common-mode transient detection result signal CMT_DETECT.

[0075] As shown in Figure 7 , it is a principle block diagram of the signal demodulation circuit in the embodiment of the present application;

[0076] The signal demodulation circuit 203 comprises a threshold adjusting unit, a signal demodulation unit and a buffer BUF1 connected in sequence. In which:

[0077] The threshold adjusting unit 231 is configured to adjust the demodulation threshold according to the common-mode transient detection result signal;

[0078] The signal demodulation unit 232 is configured to demodulate the differential signal according to the adjusted demodulation threshold to obtain an original signal;

[0079] The buffer BUF1 is configured to convert the analog signal output by the signal demodulation unit 232 into a digital signal and increase the driving capability.

[0080] Figure 8 A specific structural schematic diagram of the signal demodulation circuit is given.

[0081] Meanwhile refer to Figure 7 and Figure 8The threshold adjusting unit 231 comprises a second inverter INV2, a NOR gate NOR1, an AND gate AND1, a fifth NMOS transistor N703 and a sixth NMOS transistor N702. One input terminal of the AND gate AND1 is connected to the output terminal of the buffer BUF1, and the output signal of the buffer BUF1 is denoted as VOUT. The other input terminal of the AND gate AND1 is connected to the output terminal of the common mode detection circuit, i.e. inputs the common mode transient detection result signal CMT_DETECT. The input terminal of the second inverter INV2 is connected to the output terminal of the common mode detection circuit, i.e. inputs the common mode transient detection result signal CMT_DETECT. One input terminal of the NOR gate NOR1 is connected to the output terminal of the buffer BUF1, and the other input terminal of the NOR gate NOR1 is connected to the output terminal of the second inverter INV2. The source of the fifth NMOS transistor N703 is connected to the first current source I701, the gate of the fifth NMOS transistor N703 is connected to the output terminal of the AND gate AND1, and the drain of the fifth NMOS transistor N703 serves as one output terminal VON of the threshold adjusting unit 231. The source of the sixth NMOS transistor N702 is connected to the second current source I702, the gate of the sixth NMOS transistor N702 is connected to the output terminal of the NOR gate NOR1, and the drain of the sixth NMOS transistor N702 serves as the other output terminal VO of the threshold adjusting unit 231.

[0082] With reference to Figure 7 and Figure 8 continuously, the signal demodulation unit 232 comprises a third PMOS transistor P700, a fourth PMOS transistor P701, a third NMOS transistor N700, a fourth NMOS transistor N701 and a tail current source I703. The source of the third PMOS transistor P700 and the source of the fourth PMOS transistor P701 are both connected to the power supply VDD. The drain and the gate of the third PMOS transistor P700 are shorted to one output terminal VON of the threshold adjusting unit 231. The gate of the fourth PMOS transistor P701 is connected to one output terminal VON of the threshold adjusting unit 231. The drain of the fourth PMOS transistor P701 is connected to the other output terminal VO of the threshold adjusting unit 231. The source of the third NMOS transistor N700 and the source of the fourth NMOS transistor N701 are connected to the tail current source I703, and one end of the tail current source I703 is grounded. The gate of the third NMOS transistor N700 is used for inputting a differential signal Vsignal. The drain of the third NMOS transistor N700 is connected to one output terminal VON of the threshold adjusting unit 231. The gate of the fourth NMOS transistor N701 is used for inputting a demodulation threshold voltage Vref. The drain of the fourth NMOS transistor N701 is connected to the other output terminal VO of the threshold adjusting unit 231.

[0083] The input end of the buffer BUF1 is connected to another output end VO of the threshold adjusting unit 231.

[0084] It should be noted that in actual application, the third NMOS transistor N700 can be composed of two NMOS structure units, and the gates of the two NMOS structure units are different, and the source and the drain are shorted to each other. Correspondingly, the differential signal Vsignal can also be composed of a group of differential signals, which are respectively connected to the gate ends of the two NMOS structure units constituting the third NMOS transistor N700.

[0085] The working process of the signal demodulation circuit will be described in detail below. Figure 8 The working process of the signal demodulation circuit will be described in detail below.

[0086] When the common mode detection signal CMT_DETECT output by the common mode detection circuit 204 is at low level, the high level common mode detection signal CTRL_H output by the AND gate AND1 and the low level common mode detection signal CTRL_L output by the second inverter NV2 and the NOR gate NOR1 are both at low level, so that the fifth NMOS transistor N703 and the sixth NMOS transistor N702 are both in the off state. At this time, the core decoding comparator composed of the third NMOS transistor N700, the fourth NMOS transistor N701, the third PMOS transistor P700, the fourth PMOS transistor P701 and the tail current source I703 is not disturbed. In this case, when the differential signal Vsignal is greater than the demodulation threshold voltage Vref, the node VO is at high level; when the differential signal Vsignal is less than the demodulation threshold voltage Vref, the node VO is at low level.

[0087] When the common mode detection signal CMT_DETECT output by the common mode detection circuit 204 is at high level, if the output signal VOUT of the buffer BUF1 is at high level at this time, the high level common mode detection signal CTRL_H is at high level, and the low level common mode detection signal CTRL_L is at low level, at this time the fifth NMOS transistor N703 is turned on, and the first current source I701 provides an additional pull-down current source for the node VON. From the output node, the first current source I701 creates a negative offset voltage superimposed on the demodulation threshold voltage Vref, so that Vref+Vos is reduced, wherein Vos represents the offset voltage, so that the output node VO of the core decoding comparator is more difficult to turn to low level. If the transmitted signal is flipped from high level to low level at this time, the differential signal Vsignal is less than Vref+Vos, the comparator can still be normally flipped. Thus, the ability of the signal demodulation circuit 203 to resist common mode transient interference when transmitting high level is improved, while the output signal flipping to low level due to the change of the input signal is not affected.

[0088] When the common mode detection signal CMT_DETECT outputted by the common mode detection circuit 204 is high, if the output signal VOUT of the buffer BUF1 is low at this time, the common mode detection signal CTRL_H is low, and the low common mode detection signal CTRL_L is high. At this time, the sixth NMOS transistor N702 is turned on, and the second current source I702 provides an additional pull-down current for the output node VO of the comparator, so that a larger pull-up current is needed to pull up the node VO, and the second current source I702 creates a positive offset voltage superimposed on the demodulation threshold voltage Vref, so that Vref+Vos is increased, thereby making it more difficult for the output node VO of the comparator to flip to high. If the transmitted signal flips from low to high at this time, the comparator can still normally flip when the differential signal Vsignal is greater than Vref+Vos. Thus, the ability of the signal demodulation circuit 203 to resist common mode transient interference when transmitting low is improved, and the output signal flipping to high due to changes in the input signal is not affected.

[0089] The change amplitude of the offset voltage is set by the first current source I701 and the second current source I702, and needs to be designed according to the matching degree and gain of the differential amplifier in front of the signal demodulation circuit, and does not make a fixed requirement.

[0090] Figure 9 A working flowchart of the signal demodulation circuit in the embodiment of the application is shown, including the following steps:

[0091] In step 901, it is judged whether common mode transient interference is detected, i.e., whether the common mode detection signal CMT_DETECT is high. If yes, step 902 is executed; otherwise, step 903 is executed.

[0092] In step 902, the decoding threshold is not compensated, i.e., the differential signal Vsignal is demodulated according to the demodulation threshold voltage Vref.

[0093] In step 903, it is judged whether the output signal VOUT of the buffer BUF1 is low. If yes, step 904 is executed; otherwise, step 905 is executed.

[0094] In step 904, the low common mode detection signal CTRL_L is effective, i.e., high, the sixth NMOS transistor N702 is turned on, the output node VO is pulled down for compensation, the VOUT is maintained in a low level state, and the equivalent threshold voltage is increased, i.e., the differential signal Vsignal is demodulated according to the increased demodulation threshold voltage.

[0095] In step 905, the high-level common-mode detection signal CTRL_H is effective, that is, high, the fifth NMOS tube N703 is opened, the output node VOUT is pulled down for compensation, the output node VO and the VOUT are maintained in a high-level state, and the equivalent threshold voltage is lowered, that is, the differential signal Vsignal is demodulated according to the demodulated threshold voltage after the lowering.

[0096] Correspondingly, the embodiment of the present application also provides an isolator, as shown in the accompanying drawings. Figure 10 As shown in the accompanying drawings, it is a structural schematic diagram of the isolator.

[0097] The isolator comprises a sending circuit 1 and a receiving circuit 2. The sending circuit 1 comprises a signal modulation circuit 201, a first isolation capacitor Ciso1 and a third isolation capacitor Ciso3, and the output of the signal modulation circuit 201 is connected to the lower plate of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 respectively. The receiving circuit 2 comprises the common-mode transient interference suppression circuit as described above, and the upper plates of the second isolation capacitor Ciso2 and the fourth isolation capacitor Ciso4 in the receiving circuit 2 are connected to the upper plates of the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 in the sending circuit 1 respectively.

[0098] Further, the receiving circuit 2 can further comprise a differential amplifier (AMP) 202 arranged between the second-order high-pass filter and the signal demodulation circuit 203.

[0099] The working principle of the isolator provided by the embodiment will be described below. Figure 10 The working principle of the isolator provided by the embodiment will be described below.

[0100] Referring to Figure 10 , the signal modulation circuit 201 performs OOK encoding on the input signal IN, that is, outputs an OSC (Oscillator, oscillator) signal during the period when the input signal IN is high, outputs a group of differential signals with a phase difference of 180° to the first isolation capacitor Ciso1 and the third isolation capacitor Ciso3 in a differential structure, and outputs a low-level signal during the period when the input signal IN is low. The differential signal is input to the input end VINN and VINP of the differential amplifier 202 after passing through the first capacitor C1 and the second capacitor C2, and the input common-mode voltage required by the differential amplifier 202 is provided by the common-mode voltage Vcm connected by the third resistor R3 and the fourth resistor R4. The differential signal is input to the signal demodulation circuit 203 after being amplified by the differential amplifier 202, the original signal is restored by the signal demodulation circuit 203, and the output signal VOUT is output.

[0101] The common mode detection circuit 204 judges whether common mode transient interference occurs by detecting whether the potential of the node Vin1 and the node Vin2 has a large mutation, and outputs a common mode detection signal CMT_DETECT to the signal demodulation circuit 203 when detecting that common mode transient interference occurs, so as to compensate the threshold voltage of the signal demodulation circuit 203, make the equivalent threshold voltage follow the change trend of the signal, and improve the ability of the signal demodulation circuit 203 to resist common mode transient interference, thereby suppressing the signal decoding abnormality caused by common mode transient interference and improving the ability of the isolator to resist common mode transient interference.

[0102] Referring to Figure 5 , when common mode transient interference occurs, there are two states that the sending circuit 1 pours current into the receiving circuit 2 and the sending circuit 1 extracts current from the receiving circuit 2, which correspond to the rising and falling stages of TGND respectively. The pouring current detection unit 401 and the extracting current detection unit 402 in the common mode detection circuit 204 are respectively used for detecting the two states that the receiving circuit 2 is poured into current and extracted current through the isolation capacitor, so as to realize the detection of the rising edge and the falling edge of the signal sending end ground TGND, thereby realizing the detection of the positive common mode transient interference and the negative common mode transient interference. The logic processing unit 403 is used for integrating the output signals of the pouring current detection unit 401 and the extracting current detection unit 402, and outputting the final common mode detection signal CMT_DETECT.

[0103] Figure 11 The detection waveform diagram of the common mode detection circuit is shown, and the working process of the common mode detection circuit will be described in detail below with reference to Figure 5 , Figure 6 , Figure 10 and Figure 11 .

[0104] Referring to the common mode detection circuit detection waveform diagram shown in Figure 11 :

[0105] When the positive common mode transient interference occurs at T1, the common mode current generated by the common mode transient interference flows from the sending circuit 1 to the receiving circuit 2, the current poured into the receiving circuit 2 is discharged through the first resistor R1 and the second resistor R2, and the voltage of the node Vin1 and the node Vin2 is raised, and the highest voltage of the node Vin1 and the node Vin2 is I CMT *R1, when the current flowing through the first capacitor C1 and the second capacitor C2 flows to the signal receiving end ground RGND through the third resistor R3 and the fourth resistor R4, the voltage of the two input ends of the differential amplifier, i.e. the node VINN and the node VINP, is raised, so that the current flowing through the first capacitor C1 and the second capacitor C2 is reduced, and the current flowing through the first resistor R1 and the second resistor R2 is gradually increased, and finally the voltage of the node Vin1 and the node Vin2 gradually approaches the maximum value ICMT R1, after which the majority of the current generated by the common-mode transient disturbance will flow through the first resistor R1 and the second resistor R2 to the signal receiving end ground RGND.

[0106] When the common-mode transient disturbance ends at T3, the current flowing into the receiving circuit 2 gradually decreases, and the voltages of the node Vin1 and the node Vin2 gradually decrease to 0V.

[0107] When a negative common-mode transient disturbance occurs at T5, the common-mode current generated by the common-mode transient disturbance will flow from the receiving circuit 2 to the sending circuit 1, and the minimum value of the voltages of the node Vin1 and the node Vin2 is -I CMT R1.

[0108] When the common-mode transient disturbance ends at T7, the common-mode current flowing from the receiving circuit 2 to the sending circuit 1 gradually decreases, and the voltages of the node Vin1 and the node Vin2 gradually increase to 0V, as shown in Figure 10 .

[0109] From the above analysis and Figure 10 it can be seen that: when the common-mode transient disturbance occurs, the signals of the node Vin1 and the node Vin2 are approximately square waves and the pulse width is approximately the duration of the common-mode transient disturbance, the time when the subsequent differential amplification circuit 202 and the signal demodulation circuit 203 are most affected is the time when a larger current flows through the first capacitor C1 and the second capacitor C2, that is, the time when the common-mode transient disturbance starts and ends, and during the period of the common-mode transient disturbance, since the signals of the node Vin1 and the node Vin2 are close to the maximum value, the current flowing through the first capacitor C1 and the second capacitor C2 decreases, and the influence on the subsequent differential amplification circuit 202 and the signal demodulation circuit 203 is smaller.

[0110] When a positive common-mode transient disturbance occurs, at T1 when the common-mode transient disturbance starts, the node Vin1 and the node Vin2 are in the rising edge, and the current is discharged to the signal receiving end ground RGND through the fourth capacitor C4 and the sixth resistor R6, and the sixth capacitor C6 and the eighth resistor R8, respectively, when the current flowing through the sixth resistor R6 and the eighth resistor R8 causes a voltage drop greater than V thN , a pull-down current I3 is generated, and when I3 is greater than the reference current I2, the output node B will be flipped from high to low, generating a high-level pulse on the output signal CMT_DETECT from T1 to T2. At T3 when the common-mode transient disturbance ends, Vin1 and Vin2 are in the falling edge, and the current is extracted through the capacitor C3 and the resistor R5, and the capacitor C5 and the resistor R7, respectively, when the current coupled through C3 and C5 generates a voltage greater than V thPWhen the positive common-mode transient interference occurs, at the T2 moment when the common-mode transient interference starts, the nodes Vin1 and Vin2 are at the falling edge, and the current is drawn through the third capacitor C3 and the fifth resistor R5, and the fifth capacitor C5 and the seventh resistor R7, respectively, when the current flowing through the fifth resistor R5 and the seventh resistor R7 makes the voltage drop greater than VthP, the pull-up current I4 is generated, when the pull-up current I4 is greater than the reference current I1, the output node A will be flipped from the low level to the high level, and a high level pulse from the T2 moment to the T3 moment is generated on the output common-mode detection signal CMT_DETECT.

[0111] When the negative common-mode transient interference occurs, at the T5 moment when the common-mode transient interference starts, the nodes Vin1 and Vin2 are at the falling edge, and the current is drawn through the third capacitor C3 and the fifth resistor R5, and the fifth capacitor C5 and the seventh resistor R7, respectively, when the current flowing through the fifth resistor R5 and the seventh resistor R7 makes the voltage drop greater than VthP, the pull-up current I4 is generated, when the pull-up current I4 is greater than the reference current I1, the output node A will be flipped from the low level to the high level, and a high level pulse from the T5 moment to the T6 moment is generated on the output common-mode detection signal CMT_DETECT. At the T7 moment when the common-mode transient interference ends, the nodes Vin1 and Vin2 are at the rising edge, and the current is discharged to the signal receiving end ground RGND through the fourth capacitor C4 and the sixth resistor R6, and the sixth capacitor C6 and the eighth resistor R8, respectively, when the current coupled through the fourth capacitor C4 and the sixth capacitor C6 makes the voltage on the sixth resistor R6 and the eighth resistor R8 greater than VthN, the pull-down current I3 is generated, when the pull-down current I3 is greater than the reference current I2, the output node B will be flipped from the high level to the low level, and a high level pulse from the T7 moment to the T8 moment is generated on the output common-mode detection signal CMT_DETECT.

[0112] When there is no common-mode transient interference, no current flows through the coupling capacitor, the first PMOS tube P1 and the second PMOS tube P2, and the first NMOS tube N1 and the second NMOS tube N2 are all in the off state, the pull-up current I4 and the pull-down current I3 will not be generated, the reference current I1 will pull down the output node A to the low level, the reference current I2 will pull up the output node B to the high level, and the common-mode detection signal CMT_DETECT output by the common-mode detection circuit 204 is at the low level.

[0113] Figure 12 is the waveform diagram of the conventional isolator when the common-mode transient interference occurs, Figure 13 is the waveform diagram of the isolator provided by the embodiment of the present application when the common-mode transient interference occurs. The following compares the waveforms of the conventional isolator and the isolator provided by the embodiment of the present application to further illustrate the ability of the isolator provided by the embodiment of the present application to resist the common-mode transient interference.

[0114] Referring to Figure 1 and Figure 12At T1 to T4, the transmission signal is low, and at T1 to T3, a positive common-mode transient interference occurs, the sending circuit pours current into the receiving circuit, and the voltages of the node Vin1 and the node Vin2 rise at T1 to T3 when the common-mode transient interference lasts, and at the rising edge T1 and the falling edge T3, the current is poured into or extracted from the common-mode voltage Vcm through the capacitor C1 and the capacitor C2 respectively, so that the common-mode voltage of the input ends VINN and VINP of the differential amplification circuit rises at T1 and falls at T3, which exceeds the input common-mode voltage range of the differential amplification circuit 202, causes the error of the signal after amplification processing, and the differential signal Vsignal is jittered, which exceeds the demodulation threshold voltage Vref of the signal demodulation circuit at T1 to T2 and T3 to T4, so that the decoding output VOUT is wrong and jumps from low to high.

[0115] At T4 to T5, although there is a difference between the ground potentials on both sides of the isolator, no common-mode current flows between the sending circuit and the receiving circuit, and the differential amplification circuit AMP202 of the receiving circuit works normally.

[0116] At T5 to T8, the transmission signal is low, and at T5 to T7, a negative common-mode transient interference occurs, the sending circuit extracts current from the receiving circuit, and the voltages of the node Vin1 and the node Vin2 fall at T5 to T7 when the common-mode transient interference lasts, and at the falling edge T5 and the rising edge T7, the current is extracted and poured into the common-mode voltage Vcm through the capacitor C1 and the capacitor C2 respectively, so that the common-mode voltage of the input ends VINN and VINP of the differential amplification circuit falls at T5 and rises at T7, which exceeds the input common-mode voltage range of the differential amplification circuit, causes the error of the signal after amplification processing, and the differential signal Vsignal is jittered, which exceeds the demodulation threshold voltage Vref of the signal demodulation circuit at T5 to T6 and T7 to T8, so that the output VOUT of the signal demodulation circuit is wrong and flips from low to high.

[0117] At the time of T9 to T12, the transmission signal is high, and the positive common-mode transient interference occurs at the time of T9 to T11, the sending circuit pours the current into the receiving circuit, the voltages of the node Vin1 and the node Vin2 rise at the time of T9 to T11 when the common-mode transient interference lasts, and the rising edge T9 and the falling edge T11 respectively pour and extract the current to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2, so that the common-mode voltage of the input ends VINN and VINP of the differential amplification circuit rises at the time of T9 and lowers at the time of T11, which exceeds the input common-mode voltage range of the differential amplification circuit, causes the error of the signal after the amplification processing, the amplitude of the differential signal Vsignal of the input signal demodulation circuit is small, which is lower than the demodulation threshold voltage Vref of the signal demodulation circuit at the time of T9 to T10 and the time of T11 to T12, and causes the error of the output VOUT of the signal demodulation circuit, which is flipped from high to low.

[0118] At the time of T12 to T13, although there is a difference between the ground potentials on both sides of the isolator, no common-mode current flows between the sending circuit and the receiving circuit, and the differential amplification circuit of the receiving circuit works normally.

[0119] At the time of T13 to T16, the transmission signal is high, and the negative common-mode transient interference occurs at the time of T13 to T15, the sending circuit extracts the current from the receiving circuit, the voltages of the node Vin1 and the node Vin2 lower at the time of T13 to T15 when the common-mode transient interference lasts, and the falling edge T13 and the rising edge T15 respectively extract and pour the current to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2, so that the common-mode voltage of the input ends VINN and VINP of the differential amplification circuit lowers at the time of T13 and rises at the time of T15, which exceeds the input common-mode voltage range of the differential amplification circuit, causes the error of the signal after the amplification processing, the differential signal Vsignal is dithered, which is lower than the demodulation threshold voltage Vref of the signal demodulation circuit at the time of T13 to T14 and the time of T15 to T16, and causes the error of the output VOUT of the signal demodulation circuit, which is flipped from high to low.

[0120] Referring to Figure 10 and Figure 13At T1 to T4, the transmission signal is low, and the positive common-mode transient interference occurs at T1 to T3, the sending circuit 1 pours current into the receiving circuit 2, and the voltages of the node Vin1 and the node Vin2 rise at T1 to T3 when the common-mode transient interference lasts, and the rising edge T1 and the falling edge T3 respectively pour or extract current to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2, so that the common-mode voltage of the input ends VINN and VINP of the differential amplification circuit 202 rises at T1 and falls at T3, which exceeds the input common-mode voltage range of the differential amplification circuit 202, resulting in an error of the signal after amplification processing, and the differential signal Vsignal is jittered, which may exceed the demodulation threshold voltage Vref of the signal demodulation circuit 203 at T1 to T2 and T3 to T4. The common-mode detection circuit 204 detects the common-mode transient interference at T1 to T4, outputs the high-level pulse lasting from T1 to T2 at T1, and outputs the high-level pulse lasting from T3 to T4 at T3. Since the output VOUT of the signal demodulation circuit at the previous time is low, the high-level common-mode detection signal CTRL_H outputs low, and the low-level common-mode detection signal CTRL_L is effective at T1 to T2 and T3 to T4, outputs high, and generates a positive offset voltage superimposed on the demodulation threshold voltage Vref, so that the differential signal Vsignal is increased, but still satisfies Vsignal < Vref + Vos, and the node VO maintains low, so that the output VOUT of the signal demodulation circuit maintains low.

[0121] At T4 to T5, although there is a difference in the ground potential on both sides of the isolator, no common-mode current flows between the sending circuit and the receiving circuit, and the differential amplification circuit 202 of the receiving circuit 2 works normally.

[0122] At the time of T5 to T8, the transmission signal is low, at the time of T5 to T7, the negative common-mode transient interference occurs, the sending circuit 1 extracts current from the receiving circuit 2, the voltage of the node Vin1 and the node Vin2 decreases at the time of T5 to T7 when the common-mode transient interference lasts, and extracts or fills the current to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2 at the falling edge T5 and the rising edge T7 respectively, so that the common-mode voltage of the input end VINN and VINP of the differential amplification circuit 202 decreases at the time of T5 and increases at the time of T7, which exceeds the input common-mode voltage range of the differential amplification circuit 202, causes the error of the signal after the amplification processing, the differential signal Vsignal shakes, and can exceed the demodulation threshold voltage Vref of the signal demodulation circuit 203 at the time of T5 to T6 and T7 to T8. The common-mode detection circuit 204 detects the common-mode transient interference at the time of T5 to T8, outputs the high-level pulse lasting from the time of T5 to T6 at the time of T5, and outputs the high-level pulse lasting from the time of T7 to T8 at the time of T7. Since the output VOUT of the signal demodulation circuit at the previous time is low, the high-level common-mode detection signal CTRL_H outputs low, CTRL_L is valid at the time of T5 to T6 and T7 to T8, outputs high, and generates the positive offset voltage superimposed on the demodulation threshold voltage Vref, so that the differential signal Vsignal increases, but still satisfies Vsignal

[0123] At T9 to T12, the transmission signal is high, and the positive common-mode transient interference occurs at T9 to T11, the sending circuit 1 pours current into the receiving circuit 2, and the voltages of the node Vin1 and the node Vin2 rise at T9 to T11 when the common-mode transient interference lasts, and the rising edge T9 and the falling edge T11 respectively pour or extract current to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2, so that the common-mode voltages of the input ends VINN and VINP of the differential amplification circuit 202 rise at T9 and decrease at T11, which exceeds the input common-mode voltage range of the differential amplification circuit 202, causes the error of the signal after the amplification processing, and the differential signal Vsignal is dithered, which may be lower than the demodulation threshold voltage Vref of the signal demodulation circuit 203 at T9 to T10 and T11 to T12. The common-mode detection circuit 204 detects the common-mode transient interference at T9 to T12, outputs the high-level pulse lasting from T9 to T10 at T9, and outputs the high-level pulse lasting from T11 to T12 at T11. Since the output VOUT of the signal demodulation circuit at the previous time is high, the low-level common-mode detection signal CTRL_L outputs low, and the high-level common-mode detection signal CTRL_H is effective at T9 to T10 and T11 to T12, outputs high, and generates the negative offset voltage superimposed on the demodulation threshold voltage Vref, so that the differential signal Vsignal is reduced, but still satisfies Vsignal>Vref+Vos, the node VO maintains high, and thus the output VOUT of the signal demodulation circuit maintains high.

[0124] At T12 to T13, although there is a difference in the ground potential on both sides of the isolator, no mutation occurs, and no common-mode current flows between the sending circuit and the receiving circuit, so the differential amplification circuit 202 of the receiving circuit works normally.

[0125] At the time of T13 to T16, the transmission signal is high, the negative common-mode transient interference occurs at the time of T13 to T15, the sending circuit 1 extracts the current from the receiving circuit 2, the voltage of the node Vin1 and the node Vin2 is reduced at the time of T13 to T15 when the common-mode transient interference lasts, and the current is extracted or filled to the common-mode voltage Vcm through the capacitor C1 and the capacitor C2 at the falling edge T13 and the rising edge T15 respectively, so that the common-mode voltage of the input end VINN and VINP of the differential amplification circuit 202 is reduced at the time of T13 and is increased at the time of T15, which exceeds the input common-mode voltage range of the differential amplification circuit 202, resulting in that the error occurs to the signal after the amplification processing, the differential signal Vsignal is jittered, and the differential signal Vsignal can be lower than the demodulation threshold voltage Vref of the signal demodulation circuit 203 at the time of T13 to T14 and the time of T15 to T16. The common-mode detection circuit 204 detects the common-mode transient interference at the time of T13 to T15, outputs the high-level pulse lasting from the time of T13 to the time of T14 at the time of T13, and outputs the high-level pulse lasting from the time of T15 to the time of T16 at the time of T15. Since the output VOUT of the signal demodulation circuit at the previous time is high, the low-level common-mode detection signal CTRL_L outputs low, the high-level common-mode detection signal CTRL_H is valid at the time of T13 to T14 and the time of T15 to T16, and outputs high, so that the negative offset voltage is superimposed on the demodulation threshold voltage Vref, the differential signal Vsignal is reduced, but still satisfies Vsignal>Vref+Vos, the node VO maintains high, and thus the output VOUT of the signal demodulation circuit maintains high.

[0126] It can be seen from the waveform diagrams of the two that, in the isolator of the embodiment of the application, the common-mode transient interference detection circuit is arranged, the current generated by the positive and negative common-mode transient interference is detected by the common-mode transient interference detection circuit respectively, the common-mode transient event can be distinguished from the normal signal transmission, the common-mode transient interference is accurately detected, and the signal transmission without the common-mode transient interference is not affected. When the common-mode transient interference is detected, the threshold voltage of the demodulation circuit is compensated, the equivalent threshold voltage follows the change trend of the signal, the signal decoding abnormality caused by the common-mode transient interference is inhibited, and the anti-common-mode transient interference capability of the isolator is improved.

[0127] It should be understood that the term “and / or” herein only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character “ / ” herein represents that the front and rear associated objects are in an “or” relationship.

[0128] “Multiple” appearing in the embodiment of the application means two or more.

[0129] The first, second, and the like appearing in the embodiments of the present application are only for illustration and distinguishing the described objects, and do not have sequence and do not represent special limitation of the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0130] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be defined by the scope defined by the claims.

Claims

1. A common-mode transient interference suppression circuit, characterized in that, include: The series-connected first-stage high-pass filter, second-stage high-pass filter, and signal demodulation circuit also include a common-mode detection circuit. The first-stage high-pass filter and the second-stage high-pass filter are used to filter the input signal at the signal receiving end in sequence, output the filtered differential signal, and provide a current discharge path when common-mode transient interference occurs. The common-mode detection circuit is used to detect the differential signal output by the first-stage high-pass filter, generate a common-mode transient detection result signal, and output it to the signal demodulation circuit. The signal demodulation circuit is used to demodulate the differential signal output by the second-stage high-pass filter based on the common-mode transient detection result signal to obtain the original signal; The signal demodulation circuit includes: a threshold adjustment unit, a signal demodulation unit, and a buffer (BUF1) connected in sequence. The threshold adjustment unit is used to adjust the demodulation threshold according to the common-mode transient detection result signal; The signal demodulation unit is used to demodulate the differential signal according to the adjusted demodulation threshold to obtain the original signal; The buffer (BUF1) is used to convert the analog signal output by the signal demodulation unit into a digital signal and increase the driving capability.

2. The common-mode transient interference suppression circuit according to claim 1, characterized in that, The common-mode detection circuit includes: a sink current detection unit, a pump current detection unit, and a logic processing unit; The sinking current detection unit is used to detect whether there is current being injected from the signal transmitting end into the signal receiving end, and output the sinking current detection result to the logic processing unit. The current extraction detection unit is used to detect whether there is current flowing from the signal receiving end to the signal transmitting end, and outputs the current extraction detection result to the logic processing unit. The logic processing unit is used to process the sink current detection result and the pump current detection result, and output the common-mode transient detection result signal.

3. The common-mode transient interference suppression circuit according to claim 1, characterized in that, The first-stage high-pass filter includes: a second isolation capacitor (Ciso2) and a fourth isolation capacitor (Ciso4), and a first resistor (R1) and a second resistor (R2) connected in series; the upper plates of the second isolation capacitor (Ciso2) and the fourth isolation capacitor (Ciso4) are respectively connected to the signal transmitting end; the lower plate of the second isolation capacitor (Ciso2) is connected to one end of the first resistor (R1) and the first input terminal of the common-mode detection circuit; the lower plate of the fourth isolation capacitor (Ciso4) is connected to one end of the second resistor (R2) and the second input terminal of the common-mode detection circuit; the common terminal of the first resistor (R1) and the second resistor (R2) is connected to the reference ground (RGND) of the signal receiving end. The second-stage high-pass filter includes: a first capacitor (C1) and a second capacitor (C2), and a third resistor (R3) and a fourth resistor (R4) connected in series; the upper plates of the first capacitor (C1) and the second capacitor (C2) are respectively connected to the lower plates of the second isolation capacitor (Ciso2) and the fourth isolation capacitor (Ciso4); the upper plates of the first capacitor (C1) and the second capacitor (C2) are also respectively connected to the common-mode detection circuit; the lower plate of the first capacitor (C1) is connected to one end of the third resistor (R3); the lower plate of the second capacitor (C2) is connected to one end of the fourth resistor (R4); and the common terminal of the third resistor (R3) and the fourth resistor (R4) is connected to the common-mode level (Vcm).

4. The common-mode transient interference suppression circuit according to claim 2, characterized in that, The current extraction detection unit includes: a pull-down current source (I1), a first PMOS transistor (P1), and a second PMOS transistor (P2); the source of the first PMOS transistor (P1) and the source of the second PMOS transistor (P2) are respectively connected to the power supply (VDD) of the receiving circuit; the gate of the first PMOS transistor (P1) is connected to the first input terminal of the common-mode detection circuit through a third capacitor (C3) and then connected to the power supply (VDD) through a fifth resistor (R5); the gate of the second PMOS transistor (P2) is connected to the second input terminal of the common-mode detection circuit through a fifth capacitor (C5) and then connected to the power supply (VDD) through a seventh resistor (R7); the drain of the first PMOS transistor (P1) and the drain of the second PMOS transistor (P2) are respectively connected to the pull-down current source (I1), and the current extraction detection result is output; The sink current detection unit includes: a pull-up current source (I2), a first NMOS transistor (N1), and a second NMOS transistor (N2); the source of the first NMOS transistor (N1) and the source of the second NMOS transistor (N2) are respectively connected to the reference ground (RGND) of the receiving circuit; the gate of the first NMOS transistor (N1) is connected to the first input terminal of the common-mode detection circuit through a fourth capacitor (C4) and to the reference ground (RGND) of the receiving circuit through a sixth resistor (R6); the gate of the second NMOS transistor (N2) is connected to the second input terminal of the common-mode detection circuit through a sixth capacitor (C6) and to the reference ground (RGND) of the receiving circuit through an eighth resistor (R8); the drain of the first NMOS transistor (N1) and the drain of the second NMOS transistor (N2) are respectively connected to the pull-up current source (I2), and the sink current detection result is output.

5. The common-mode transient interference suppression circuit according to claim 4, characterized in that, The logic processing unit includes: a first inverter (INV1) and an OR gate (OR1). The output of the pull-down current source (I1) is connected to one input of the OR gate (OR1); the output of the pull-up current source (I2) is connected to the input of the first inverter (INV1), and the output of the first inverter (INV1) is connected to the other input of the OR gate (OR1); the OR gate (OR1) outputs the common-mode transient detection result signal.

6. The common-mode transient interference suppression circuit according to claim 5, characterized in that, The threshold adjustment unit includes: a second inverter (INV2), a NOR gate (NOR1), an AND gate (AND1), a fifth NMOS transistor (N703), and a sixth NMOS transistor (N702). One input of the AND gate (AND1) is connected to the output (VOUT) of the buffer (BUF1), and the other input of the AND gate (AND1) is connected to the output of the common-mode detection circuit; The input terminal of the second inverter (INV2) is connected to the output terminal of the common-mode detection circuit; One input of the NOR gate (NOR1) is connected to the output of the buffer (BUF1), and the other input of the NOR gate (NOR1) is connected to the output of the second inverter (INV2). The source of the fifth NMOS transistor (N703) is connected to the first current source (I701), the gate of the fifth NMOS transistor (N703) is connected to the output of the AND gate (AND1), and the drain of the fifth NMOS transistor (N703) serves as an output (VON) of the threshold adjustment unit. The source of the sixth NMOS transistor (N702) is connected to the second current source (I702), the gate of the sixth NMOS transistor (N702) is connected to the output of the NOR gate (NOR1), and the drain of the sixth NMOS transistor (N702) serves as another output (VO) of the threshold adjustment unit.

7. The common-mode transient interference suppression circuit according to claim 5, characterized in that, The signal demodulation unit includes: a third PMOS transistor (P700), a fourth PMOS transistor (P701), a third NMOS transistor (N700), a fourth NMOS transistor (N701), and a tail current source (I703); The source of the third PMOS transistor (P700) and the source of the fourth PMOS transistor (P701) are both connected to the power supply (VDD). The drain and gate of the third PMOS transistor (P700) are shorted to one output terminal (VON) of the threshold adjustment unit. The gate of the fourth PMOS transistor (P701) is connected to one output terminal (VON) of the threshold adjustment unit, and the drain of the fourth PMOS transistor (P701) is connected to the other output terminal (VO) of the threshold adjustment unit. The source of the third NMOS transistor (N700) and the source of the fourth NMOS transistor (N701) are connected to the tail current source (I703), one end of which is grounded. The gate of the third NMOS transistor (N700) is used to input the differential signal, and the drain of the third NMOS transistor (N700) is connected to one output terminal (VON) of the threshold adjustment unit. The gate of the fourth NMOS transistor (N701) is used to input the demodulation threshold voltage (Vref), and the drain of the fourth NMOS transistor (N701) is connected to the other output terminal (VO) of the threshold adjustment unit. The input of the buffer (BUF1) is connected to the other output (VO) of the threshold adjustment unit.

8. The common-mode transient interference suppression circuit according to claim 7, characterized in that, The third NMOS transistor (N700) consists of two NMOS structural units, and the gates of the two NMOS structural units are different, while the source and drain are shorted to each other.

9. An isolator, characterized in that, The isolator includes a transmitting circuit (1) and a receiving circuit (2); the transmitting circuit (1) includes a signal modulation circuit, a first isolation capacitor (Ciso1) and a third isolation capacitor (Ciso3), the output of the signal modulation circuit being connected to the lower plates of the first isolation capacitor (Ciso1) and the third isolation capacitor (Ciso3) respectively; the receiving circuit (2) includes a common-mode transient interference suppression circuit as described in any one of claims 1 to 8.

10. The isolator according to claim 9, characterized in that, The receiving circuit (2) further includes a differential amplifier disposed between the second-stage high-pass filter and the signal demodulation circuit.

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