A test method for detecting CAF failure of circuit board vias

Abstract

The present invention discloses a test method for detecting the CAF failure of circuit board vias, including: providing a test board, the via size, via spacing, and trace width of the test board are the same as the via size, via spacing, and trace width of the circuit board to be tested; measuring the via resistance value of the test board, which is the initial resistance value; placing the test board into a hot and cold shock experimental device, and adopting a first temperature and a second temperature cycle experiment; taking out the test board, placing it at room temperature and letting it stand; using a resistance tester to measure the via resistance value of the test board, which is the experimental resistance value; until the experimental resistance value tested and the rate of change of the initial resistance value are not less than a set threshold, the failure time is calculated. The present invention uses the test board to simulate the circuit state of the circuit board to be tested, and performs a hot and cold shock experiment on the test board, obtains test data of degradation failure, calculates the failure and degradation time of the circuit board to be tested, facilitates the design of the optimized circuit board, and improves the reliability of the product.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic product testing, and in particular to a testing method for detecting CAF failure of via holes in a circuit board. Background Art

[0002] In recent years, as electronic products have developed towards being lighter, thinner, shorter, smaller and more multifunctional, the circuit design on circuit boards has become more dense and refined, the circuit integration density has become increasingly higher, and the hole spacing has become increasingly smaller. This has led to a corresponding increase in the reliability requirements for vias in printed circuit boards, especially in the field of automotive electronics, where the requirements for resistance to high temperature and high humidity environments are relatively high. Often, unreasonable via design on circuit boards will easily lead to defects such as copper faults or breakage in the holes. If CAF (Conductive Anodic Filament) occurs in the vias of a circuit board, it will affect the performance of the entire product and seriously affect the safety functions of the vehicle. Therefore, a CAF failure test method is needed to obtain test data for degradation failures, so as to calculate the failure and degradation time to improve the reliability of the product. Summary of the Invention

[0003] The present invention discloses a test method for detecting CAF failure of circuit board vias, which is used to solve the problem in the prior art that the adverse phenomenon of circuit board vias affects product reliability.

[0004] In order to solve the above problems, the present invention adopts the following technical solutions:

[0005] A circuit board via CAF failure testing method, comprising:

[0006] A test board is provided, wherein one end of the test board is provided with at least two pads for connecting to a resistance tester, and the other end is provided with a plurality of vias, wherein the vias are connected by traces; the via size, the via spacing, and the trace width of the test board are the same as the via size, via spacing, and trace width of the circuit board to be tested;

[0007] Measuring the via resistance value of the test board as the initial resistance value;

[0008] The test plate is placed in a thermal shock test device and subjected to a first temperature and a second temperature cycle test;

[0009] Take out the test plate and let it stand at room temperature;

[0010] Use a resistance tester to measure the resistance value of the via hole of the test board, which is the experimental resistance value;

[0011] Calculating the rate of change of the experimental resistance value and the initial resistance value;

[0012] If the rate of change between the experimental resistance value and the initial resistance value is not lower than a set threshold, the test is terminated and the failure time is estimated;

[0013] If the rate of change between the experimental resistance value and the initial resistance value is less than the set threshold, the test board is placed in the hot and cold shock test equipment again, and the first temperature and second temperature cycle is adopted. The test board is taken out and placed at room temperature for stagnant time, and the experimental resistance value is tested again until the rate of change between the experimental resistance value and the initial resistance value is not less than the set threshold. The test is terminated and the failure time is estimated.

[0014] In the above solution, the first temperature is 100 to 150°C, and the second temperature is -50 to -30°C.

[0015] In the above solution, each time the test board is placed in the thermal shock test equipment, the first temperature and the second temperature cycle 70 to 120 times.

[0016] In the above solution, in one cycle, the impact time of the first temperature is 10 to 20 minutes, the impact time of the second temperature is 10 to 20 minutes, and the conversion time between the first temperature and the second temperature does not exceed 5 minutes.

[0017] In the above solution, after the test board is taken out of the thermal shock test equipment, it is left to stand at room temperature for 1 to 3 hours.

[0018] In the above solution, the temperature of the test plate after standing is not lower than 20°C.

[0019] In the above solution, there are four solder pads.

[0020] In the above solution, the resistance tester includes a 4-wire terminal resistance tester.

[0021] In the above solution, the set threshold value of the change rate between the experimental resistance value and the initial resistance value is ±10%.

[0022] In the above solution, the calculation of the failure time includes:

[0023] When the rate of change between the experimental resistance value and the initial resistance value is not less than a set threshold, determining the number of cycles between the first temperature and the second temperature;

[0024] Calculate the failure time using the following formula:

[0025] T = N / C;

[0026] Where T is the estimated failure time in years, N is the number of experimental cycles, and C is the conversion fixed constant 30.

[0027] The technical solution adopted by the present invention can achieve the following beneficial effects:

[0028] Use a test board to simulate the circuit status of the circuit board to be tested, and perform hot and cold shock experiments on the test board to obtain degradation failure test data. This can help calculate the failure and degradation time of the circuit board to be tested, facilitate optimization of the circuit board design, and improve product reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments, which constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are provided to explain the present invention and do not constitute an undue limitation of the present invention. In the drawings:

[0030] Figure 1 This is a flow chart of the circuit board via CAF failure testing method disclosed in Example 1 of the present invention;

[0031] Figure 2 Schematic diagram of the overall structure of a test board for detecting CAF failure of circuit board vias disclosed in Example 1 of the present invention;

[0032] Figure 3 This is a line graph of the experimental results of the circuit board via CAF failure testing method disclosed in Example 2 of the present invention.

[0033] Specifically include the following reference numerals:

[0034] Test board-10; pad-11; via-12; trace-13. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with specific embodiments of the present invention and corresponding drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0036] Example 1

[0037] The present invention also provides a circuit board via CAF failure test method, combined with Figure 1 and Figure 2 Shown, including:

[0038] A test board 10 is provided. One end of the test board 10 is provided with at least two pads 11 for connecting to a resistance tester. The other end of the test board 10 is provided with multiple vias 12. The vias 12 are connected by traces 13. Preferably, the multiple traces 13 are arranged on different layers and connected by the vias 12. The size of the vias 12, the spacing between the vias 12, and the width of the traces 13 are the same as the via size, via spacing, and trace width of the circuit board to be tested.

[0039] Measure the resistance value of the via 12 of the test board 10, which is the initial resistance value;

[0040] The test board 10 is placed in a thermal shock test apparatus and subjected to a first temperature and a second temperature cycle test;

[0041] Take out the test plate 10 and place it at room temperature;

[0042] Use a resistance tester to measure the resistance value of the via hole of the test board 10, which is the experimental resistance value;

[0043] Calculate the rate of change of the experimental resistance value and the initial resistance value;

[0044] If the rate of change between the experimental resistance value and the initial resistance value is not lower than the set threshold, the test is terminated and the failure time is estimated;

[0045] If the rate of change between the experimental resistance value and the initial resistance value is less than the set threshold, the test board 10 is placed in the hot and cold shock test equipment again, and the first temperature and second temperature cycle are adopted. The test board 10 is taken out and placed at room temperature for stagnant time, and the experimental resistance value is tested again until the rate of change between the experimental resistance value and the initial resistance value is not less than the set threshold. The test is terminated and the failure time is estimated.

[0046] The present invention uses a test board 10 to simulate a circuit board to be tested for experiments, obtains degradation failure test data, and can infer the failure and degradation time of the circuit board to be tested, thereby facilitating optimization of the circuit board design and improving product reliability. The test board 10 is manufactured according to the structure of the circuit board to be tested, ensuring the reliability of the experimental data.

[0047] The first temperature is 100-150° C., and the second temperature is -50--30° C. Preferably, in this embodiment, the first temperature is 125° C., and the second temperature is -40° C.

[0048] After the test board 10 is placed in the thermal shock test equipment, the first temperature and the second temperature are cycled 70 to 120 times. In this embodiment, the number of cycles is preferably 100 times.

[0049] In one cycle, the impact time of the first temperature is 10 to 20 minutes, the impact time of the second temperature is 10 to 20 minutes, and the transition time between the first temperature and the second temperature does not exceed 5 minutes. In this embodiment, preferably, the impact time of the first temperature is 15 minutes, and the impact time of the second temperature is 15 minutes.

[0050] After the test board 10 is taken out of the thermal shock test equipment, it is left at room temperature for 1 to 3 hours. Preferably, the resting time is 2 hours, so that the temperature of the test board 10 can be roughly restored to room temperature.

[0051] After standing, the temperature of the test board 10 is not lower than 20° C. Preferably, the test board 10 is allowed to stand until the temperature reaches 25° C., which is the same as room temperature.

[0052] In this embodiment, four pads 11 are preferably provided, and the device is used in conjunction with a 4-wire terminal resistance tester.

[0053] In this embodiment, the threshold value of the change rate between the experimental resistance value and the initial resistance value is preferably set to ±10%.

[0054] The calculation of failure time includes:

[0055] When the rate of change between the experimental resistance value and the initial resistance value is not less than a set threshold, determining the number of cycles between the first temperature and the second temperature;

[0056] Calculate the failure time using the following formula:

[0057] T = N / C;

[0058] Where T is the estimated failure time in years, N is the number of experimental cycles, and C is the conversion fixed constant 30.

[0059] Example 2

[0060] This embodiment provides a test board 10 in Example 1. Specifically, the via 12 of the test board 10 provided in this embodiment has a diameter of 0.2 mm. The test board 10 is made of epoxy glass fiber board and has four layers. The test method in Example 1 was used for testing. The specific test results are shown in the following table:

[0061] Table 1

[0062] Number of cycles Resistance change rate 0 0 100 2％ 200 3％ 300 5％ 400 7％ 500 10％

[0063] The resistance value change rate curve is as follows: Figure 3 As shown in Table 1, when the number of cycles is 500, the change rate of the resistance value reaches 10%. Therefore, applying the formula in Example 1, in this embodiment, the failure time of the via 12 is: T=500 / 30=17 years.

[0064] The present invention uses a test board to simulate the circuit state of the circuit board to be tested, and performs a cold and hot shock experiment on the test board to obtain degradation failure test data. The failure and degradation time of the circuit board to be tested can be calculated, which facilitates the optimization of the circuit board design and improves the reliability of the product.

[0065] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A circuit board via CAF failure test method, characterized in that: include: A test board is provided, wherein one end of the test board is provided with at least two pads for connecting to a resistance tester, and the other end is provided with a plurality of vias, wherein the vias are connected by traces; the via size, the via spacing, and the trace width of the test board are the same as the via size, via spacing, and trace width of the circuit board to be tested; Measuring the via resistance value of the test board as the initial resistance value; The test board is placed in a thermal shock test apparatus and subjected to a first temperature and a second temperature cycle test; the first temperature is 100 to 150° C., and the second temperature is -50 to -30° C.; each time the test board is placed in the thermal shock test apparatus, the first temperature and the second temperature cycle 70 to 120 times; in one cycle, the shock time at the first temperature is 10 to 20 minutes, the shock time at the second temperature is 10 to 20 minutes, and the switching time between the first temperature and the second temperature does not exceed 5 minutes; Take out the test plate and place it at room temperature for 1 to 3 hours; after the test plate is left at room temperature, the temperature is not less than 20°C; Use a resistance tester to measure the resistance value of the via hole of the test board, which is the experimental resistance value; Calculating the rate of change of the experimental resistance value and the initial resistance value; If the rate of change between the experimental resistance value and the initial resistance value is not lower than a set threshold, the test is terminated and the failure time is estimated; If the rate of change between the experimental resistance value and the initial resistance value is less than a set threshold, the test board is placed in the thermal shock test equipment again and cycled through the first and second temperatures. The test board is removed and allowed to stand at room temperature, and the experimental resistance value is tested again until the rate of change between the experimental resistance value and the initial resistance value is no less than a set threshold. The test is terminated and the failure time is estimated. The calculation of the failure time includes: When the rate of change between the experimental resistance value and the initial resistance value is not less than a set threshold, determining the number of times the first temperature and the second temperature cycle is performed; Calculate the failure time using the following formula: T = N / C; Where T is the estimated failure time in years, N is the number of experimental cycles, and C is the conversion fixed constant 30.

2. The circuit board via CAF failure testing method according to claim 1, characterized in that: There are four solder pads.

3. The circuit board via CAF failure testing method according to claim 2, characterized in that: The resistance tester includes a 4-wire terminal resistance tester.

4. The circuit board via CAF failure testing method according to claim 1, characterized in that: The set threshold value of the rate of change between the experimental resistance value and the initial resistance value is ±10%.

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