Layout planning method, device, electronic device, and storage medium for digital circuits

Abstract

A layout planning method, device, electronic device, and storage medium for a digital circuit. The layout planning method for the digital circuit includes: obtaining attribute information corresponding to a plurality of first units and a plurality of second units respectively; calculating weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively; and performing layout planning on the digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively to obtain a layout planning result corresponding to the digital circuit. The layout planning method calculates the weight centers of the first units and the second units through the attribute information, and provides the positional relationship and logical relationship between the units for the synthesis and placement and routing of the digital circuit through the attribute information and the weight centers, effectively reducing the randomness in the existing placement methods and obtaining a circuit with better performance, lower power consumption, and smaller area overhead.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a layout planning method for a digital circuit, a layout planning device for a digital circuit, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Driven by Moore's Law, the integrated circuit process has achieved rapid development, and the number of transistors per unit area has been increasing continuously. The System-on-Chip (SoC) has the advantages of high integration, low power consumption, and low cost, and has become the mainstream direction of large-scale integrated circuit system design, solving many challenging problems in the fields of communication, image, computing, consumer electronics, etc. With the increasingly rich application requirements of the SoC, the SoC needs to integrate more and more IP (Intellectual Property) for different applications. With the high integration of the SoC, higher requirements are put forward for on-chip communication. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a layout planning method for a digital circuit. The digital circuit includes a plurality of first units and a plurality of second units, and the plurality of first units and the plurality of second units are coupled by on-chip interconnection. The layout planning method includes: obtaining attribute information corresponding to the plurality of first units and the plurality of second units respectively; calculating weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively; and performing layout planning on the digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively to obtain a layout planning result corresponding to the digital circuit.

[0004] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, calculating weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively includes: calculating a plurality of first weight centers corresponding one by one to the plurality of first units according to the attribute information corresponding to the plurality of first units respectively; calculating a plurality of second weight centers corresponding one by one to the plurality of second units according to the attribute information corresponding to the plurality of second units respectively; and determining a global weight center according to the plurality of first weight centers and the plurality of second weight centers. Wherein, the weight centers corresponding to the plurality of first units and the plurality of second units respectively include the plurality of first weight centers and the plurality of second weight centers.

[0005] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the attribute information corresponding to each first unit at least includes layout information, logical relationship, and unit type. According to the attribute information respectively corresponding to the multiple first units, calculating multiple first weight centers corresponding to the multiple first units one by one includes: for each first unit among the multiple first units: in response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a computing unit, determining the input register and output register corresponding to the first unit according to the logical relationship in the attribute information corresponding to the first unit; determining all combinational logic devices between the input register and the output register; determining the position coordinates of all the combinational logic devices according to the layout information in the attribute information corresponding to the first unit; and calculating the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices.

[0006] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, calculating the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices includes: calculating the average value or weighted average value of the position coordinates of all the combinational logic devices, and using the average value or the weighted average value as the first weight center corresponding to the first unit.

[0007] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the attribute information corresponding to each first unit at least includes layout information and unit type. According to the attribute information respectively corresponding to the multiple first units, calculating multiple first weight centers corresponding to the multiple first units respectively includes: for each first unit among the multiple first units: in response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a storage unit or a communication bus, determining the position coordinates of multiple devices included in the first unit according to the layout information in the attribute information corresponding to the first unit; calculating the average value or weighted average value of the position coordinates of the multiple devices, and using the average value or the weighted average value as the first weight center corresponding to the first unit.

[0008] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, determining the global weight center according to the multiple first weight centers and the multiple second weight centers includes: calculating the average value or weighted average value of the multiple first weight centers and the multiple second weight centers, and using the average value or the weighted average value as the global weight center.

[0009] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the on-chip interconnection includes a crossbar switch circuit, and the crossbar switch circuit is configured to perform sharing and exchange of resources of the plurality of first units and resources of the plurality of second units. According to the weight centers respectively corresponding to the plurality of first units and the plurality of second units, layout planning is performed on the digital circuit to obtain a layout planning result corresponding to the digital circuit, including: using the plurality of first weight centers as the initial positions of the plurality of first units respectively, using the plurality of second weight centers as the initial positions of the plurality of second units respectively, using the global weight center as the initial position of the crossbar switch circuit, and performing the layout planning on the digital circuit to obtain the layout planning result.

[0010] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, using the plurality of first weight centers as the initial positions of the plurality of first units respectively, using the plurality of second weight centers as the initial positions of the plurality of second units respectively, using the global weight center as the initial position of the crossbar switch circuit, and performing the layout planning on the digital circuit to obtain the layout planning result, including: using the plurality of first weight centers as the initial positions of the plurality of first units respectively, using the plurality of second weight centers as the initial positions of the plurality of second units respectively, using the global weight center as the initial position of the crossbar switch circuit, performing placement and routing on the digital circuit to obtain an initial layout result; performing optimization iteration processing based on the initial layout result to obtain the layout optimization result; wherein, the optimization iteration processing includes: calculating the transmission power consumption of multiple groups of interconnection lines between the plurality of first units and the plurality of second units according to the source layout result, where the source layout result includes the initial layout result, and each group of interconnection lines is used to connect a first unit and a second unit; performing placement and routing optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnection lines to obtain the layout optimization result; in response to the layout optimization result meeting a predetermined condition, stopping the execution of the optimization iteration processing, using the layout optimization result as the layout planning result, and in response to the layout optimization result not meeting the predetermined condition, using the layout optimization result as the source layout result and continuing to execute the optimization iteration processing.

[0011] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the multiple first weight centers are respectively used as the initial positions of the multiple first units, the multiple second weight centers are respectively used as the initial positions of the multiple second units, and the global weight center is used as the initial position of the crossbar circuit. Layout and routing are performed on the digital circuit to obtain an initial layout result, including: for a target first unit and a target second unit connected by a group of interconnecting lines: calculating the Manhattan distance between the target first unit and the target second unit according to the first weight center corresponding to the target first unit and the second weight center corresponding to the target second unit; determining the metal layer where the group of interconnecting lines is located according to the Manhattan distance.

[0012] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the digital circuit includes multiple metal layers, and the multiple metal layers include a first group of metal layers and a second group of metal layers. Determining the metal layer where the group of interconnecting lines is located according to the Manhattan distance includes: in response to the Manhattan distance being greater than a preset threshold, determining that the group of interconnecting lines is located in one of the metal layers in the first group of metal layers; in response to the Manhattan distance being less than or equal to the preset threshold, determining that the group of interconnecting lines is located in one of the metal layers in the second group of metal layers; wherein, the resistance of at least one metal layer included in the first group of metal layers is less than the resistance of at least one metal layer included in the second group of metal layers.

[0013] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, calculating the transmission power consumption of multiple groups of interconnecting lines between the multiple first units and the multiple second units according to a source layout result includes: determining the multiple groups of interconnecting lines according to the source layout result; determining the metal layer and length of each group of interconnecting lines according to the source layout result; calculating the coupling capacitance of each group of interconnecting lines according to the metal layer and length of each group of interconnecting lines; calculating the transmission power consumption of each group of interconnecting lines according to the coupling capacitance of each group of interconnecting lines.

[0014] For example, in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure, the optimization iteration process further includes: calculating the delay of the multiple groups of interconnecting lines according to the source layout result; performing layout and routing optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnecting lines to obtain the layout optimization result, including: performing the layout and routing optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnecting lines and the delay of the multiple groups of interconnecting lines to obtain the layout optimization result.

[0015] For example, in a layout planning method of a digital circuit provided by at least one embodiment of the present disclosure, the crossbar switch circuit is configured such that there is a connection relationship between each pair of the plurality of first units and the plurality of second units, and the conduction state between the plurality of first units and the plurality of second units is switched in real time.

[0016] For example, in a layout planning method of a digital circuit provided by at least one embodiment of the present disclosure, the crossbar switch circuit includes a plurality of controllers, and the plurality of controllers are used to switch the conduction state between the plurality of first units and the plurality of second units according to corresponding control signals. In the layout optimization result, the crossbar switch circuit is a distributed circuit, and the plurality of controllers are distributed to the plurality of first units or the plurality of second units.

[0017] For example, a layout planning method of a digital circuit provided by at least one embodiment of the present disclosure further includes: determining the positions of at least one device included in the crossbar switch circuit according to the layout planning result; and performing resource optimization processing on the digital circuit according to the positions of the at least one device, where the resource optimization processing includes common path optimization processing.

[0018] At least one embodiment of the present disclosure provides a layout planning device for a digital circuit. The digital circuit includes a plurality of first units and a plurality of second units, and the plurality of first units and the plurality of second units are coupled by on-chip interconnection. The layout planning device includes: an acquisition unit configured to acquire attribute information corresponding to the plurality of first units and the plurality of second units respectively; a calculation unit configured to calculate weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively; and a planning unit configured to perform layout planning on the digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively to obtain a layout planning result corresponding to the digital circuit.

[0019] At least one embodiment of the present disclosure further provides an electronic device, including: a memory that stores computer-executable instructions non-transiently; and a processor configured to run the computer-executable instructions, where the computer-executable instructions, when run by the processor, implement the layout planning method of the digital circuit according to any one of the embodiments of the present disclosure.

[0020] At least one embodiment of the present disclosure further provides a non-transient computer-readable storage medium. The non-transient computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions, when executed by a processor, implement the layout planning method of the digital circuit according to any one of the embodiments of the present disclosure. Description of the Drawings

[0021] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0022] Figure 1A Shows a schematic diagram of the routing logic of GPU computing resources;

[0023] Figure 1B Shows a layout view of GPU computing resources;

[0024] Figure 1C Shows a layout view of GPU computing resources;

[0025] Figure 2 Is a schematic flowchart of a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure;

[0026] Figure 3 Is a schematic flowchart of step S20 in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure;

[0027] Figure 4 Is a schematic diagram of the weight center of a digital circuit provided by an embodiment of the present disclosure;

[0028] Figure 5 Is a schematic diagram of the layout planning result provided by an embodiment of the present disclosure;

[0029] Figure 6A Is a schematic block diagram of a layout planning device for a digital circuit provided by at least one embodiment of the present disclosure;

[0030] Figure 6B Is a schematic block diagram of a computing unit provided by at least one embodiment of the present disclosure;

[0031] Figure 7 Is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure;

[0032] Figure 8 Is a schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of some known functions and known components are omitted in the present disclosure.

[0036] On-chip interconnection includes a communication bus, a crossbar switch matrix (CrossBar), etc. For example, in a communication bus structure, all processors and IP modules share one or more communication buses, and the communication bus can implement broadcast communication. When multiple processors access a communication bus simultaneously, an arbitration mechanism is required to determine the ownership of the communication bus. For example, in a crossbar switch matrix structure, each input link and output link has a cross point (CrossPoint). For example, at the cross point, a semiconductor switch connects the input line and the output line. When the input data from the source port needs to be switched to the destination port and output, the switch at the cross point is switched under the control of the processor or the switch matrix, so that the cross point between the source port and the destination port is in a conducting state, and thus the data is sent to the destination port and output. The Crossbar ensures the real-time performance of multiple communications occurring simultaneously.

[0037] In practical applications, on-chip interconnection may also adopt a combination of Crossbar and a communication bus, and use a bridge to connect the Crossbar network and the communication bus network.

[0038] A graphics processing unit (GPU) may include multiple storage units and multiple computing units. Each unit may be divided into one or more functional modules according to its function. Each functional module may be composed of some circuit logics that perform specific functions. The graphics processor may combine these functional modules to implement functions such as calculation and storage. For example, a storage unit may include a memory bank, a RAM (random access memory) or an ECC (Error Checking and Correcting) memory, etc.; for example, a computing unit may include an object for performing a specific computing task, such as a multiplication operation, a multiplication-accumulation operation, etc.

[0039] Due to the computing characteristics of graphics processors, resources need to be shared and switched between various units in real time.

[0040] Figure 1A A routing diagram of GPU computing resources is shown.

[0041] For example, a GPU includes P storage units, such as Figure 1A As shown, N first storage units (such as Figure 1A The first storage unit 1, the first storage unit 2, ... the first storage unit N) in the above-mentioned number represent some or all of the storage units in the P storage units. Similarly, the M second storage units (such as Figure 1A The second storage unit 1, the second storage unit 2, ... the second storage unit M) in the figure represent part or all of the P storage units. The N first storage units and the M second storage units may partially overlap or may be different storage units.

[0042] In addition, the GPU also includes Q computing units (such as Figure 1A Here, P, N, M and Q are all positive integers, P is greater than or equal to N and P is greater than or equal to M.

[0043] For example, data resources are stored in N first storage units, and these data resources need to be sent to Q computing units to perform corresponding operations. For example, the data resources in the N first storage units can be sent to the Q computing units through a cross switch matrix, for example, the GPU controls the corresponding cross points to be turned on, so that the data resources in the first storage units are sent to the corresponding computing units through the turned-on lines.

[0044] For example, after the computing unit finishes the corresponding operations, it is necessary to send the calculation results to the second storage unit for storage. For example, the calculation results in Q computing units can be sent to M second storage units through a crossbar switch matrix. For example, the GPU controls the corresponding crosspoints to conduct, so that the data resources in the computing unit are sent to the corresponding second storage unit through the conducting lines.

[0045] During the operation of the GPU, this sharing and switching of data resources will occur in real time. At different times, different storage units may need to send data to one or more computing units for calculation, and at different times, different computing units may need to send calculation results to one or more storage units for storage.

[0046] It should be noted that Figure 1A is only a schematic routing diagram. At different times, M, N, and Q can have different values.

[0047] When Figure 1A this kind of digital circuit with resource sharing and switching as shown is physically implemented, the typical layout view obtained is usually as Figure 1B shown.

[0048] As Figure 1B shown, P storage units are usually located in the edge area of the circuit, computing units are usually located in the middle area of the circuit, and storage units and computing units are usually arranged in an array.

[0049] When considering layout and wiring, the shortest line is usually required. The central position of the layout view will be the most essential intersection of all resources. Therefore, as Figure 1C shown, after layout and wiring, the crossbar switch circuit used to implement resource sharing and switching may be placed in the central area. At this time, the data sharing between storage unit 1 and computing unit 1 needs to be completed through the crossbar switch matrix located in the central area, so that the utilization rate of the wiring resources in the central area is very high, resulting in congestion, and even the situation of insufficient resources may occur. In addition, this layout and wiring method results in a longer interconnection line length between storage unit 1 and computing unit 1, and a larger transmission power consumption.

[0050] In addition, during synthesis, layout, and wiring, due to not understanding the logical relationship between devices, the real data source and data receiver cannot be determined. Therefore, multiple devices included in the crossbar switch matrix are usually regarded as loose logics and randomly arranged and wired, resulting in a chaotic wiring result. And to solve the congestion phenomenon in the central area, the circuit area may be selected to be enlarged during layout and wiring, and the arrangement density of devices is reduced, which further increases the area overhead and transmission power consumption.

[0051] For example, in a specific example, such as in the design of high-performance GPUs, the power consumption of a GPU includes computational power and transport power. Computational power is the dynamic power consumption generated by the computing units during the computing process, and transport power is the dynamic power consumption generated during the process of moving data from different storage units to the computing units (and vice versa). On the surface, they both belong to computational power. However, computational power is only a part of the power consumption generated by the GPU due to operations, and transport power actually accounts for a large part of the power consumption. For example, as Figure 1C shown, the data sharing between storage unit 1 and computing unit 1 needs to pass through the crossbar switch matrix located in the central area. Therefore, the length of the interconnecting line connecting storage unit 1 and computing unit 1 is relatively long, resulting in a large transport power consumption.

[0052] Currently, dynamic power optimization usually back annotates the SAIF (Switching Activity Interface Format) file to the digital circuit for dynamic power optimization. However, since the SAIF file only captures the time spent on signal transitions and logic levels, and records the toggle counts and static probabilities in the network, the dynamic optimization performed in this way only considers computational power and does not consider transport power. Therefore, the power optimization is only limited to the switching of the circuit and does not perform targeted optimization for transport power.

[0053] At least one embodiment of the present disclosure provides a layout planning method for a digital circuit, including: obtaining the attribute information corresponding to a plurality of first units and a plurality of second units respectively; calculating the weighted centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively; and performing layout planning on the digital circuit according to the weighted centers corresponding to the plurality of first units and the plurality of second units respectively to obtain the layout planning result corresponding to the digital circuit.

[0054] The layout planning method provided by at least one embodiment of the present disclosure calculates the weighted centers of the first units and the second units through the attribute information, and provides the positional relationship and logical relationship between the units for the synthesis and layout and routing of the digital circuit through the attribute information and the weighted centers, so as to determine the true data source end and data destination end, analyze and route from the unit level, effectively reduce the randomness in the existing layout method, and overall improve the PPA (Power, Performance and Area) of the circuit, that is, obtain a circuit with better performance, lower power consumption and smaller area overhead.

[0055] It should be noted that in the embodiments of the present disclosure, the device includes logic devices, and the logic devices include combinational logic devices and sequential logic devices. Here, the sequential logic device refers to devices such as flip-flops, registers, and latches in digital circuit design. The sequential logic device has the function of storing and memorizing input signals. When receiving the valid edge or valid level of the clock signal, it can trigger the sequential logic device to store the input signal and change the state of the output signal. The combinational logic device refers to devices that implement logical operations such as AND gates and OR gates in digital circuit design, such as data selectors and magnitude comparators. The combinational logic device does not have the function of storing and memorizing input signals. At any moment, the state of the output signal of the combinational logic device depends on the state of the input signal at the current moment.

[0056] Figure 2 FIG. is a schematic flowchart of a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure. As Figure 2 shown, a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure at least includes steps S10 - S30.

[0057] For example, the digital circuit can be an integrated circuit, such as a large-scale integrated circuit or a very-large-scale integrated circuit, such as the chip circuit of a CPU (Central Processing Unit) or a GPU.

[0058] For example, the digital circuit includes a plurality of first units and a plurality of second units, and the plurality of first units and the plurality of second units are coupled through on-chip interconnection.

[0059] For example, the first unit can include the storage unit, the computing unit, and the communication bus as described above. Similarly, the second unit can also include the storage unit, the computing unit, and the communication bus. For example, the communication bus can be a remote communication bus. The present disclosure does not limit the specific forms of the first unit and the second unit. For example, the first unit can represent the unit that sends data resources at a certain moment, and the second unit represents the unit that receives data resources at a certain moment. Or, for another example, the second unit represents the unit that sends data resources at a certain moment, and the first unit can represent the unit that receives data resources at a certain moment. That is to say, the first unit and the second unit in the present disclosure are only used to represent two different units for resource exchange, and the specific forms and unit types of the first unit and the second unit are not limited.

[0060] For example, in the example as Figure 1A shown, the first unit can be the first storage unit, and the second unit can be the computing unit, or the first unit can be the computing unit, and the second unit can be the second storage unit.

[0061] For example, when broadcast communication is required, the first unit may be a computing unit, and the second unit may be a communication bus. The data resources in the computing unit are broadcast via the communication bus to all storage units or computing units connected to the communication bus.

[0062] For example, in some embodiments, the multiple first units and multiple second units may include computing units and storage units; for example, in other embodiments, when the circuit has communication requirements such as broadcast communication, the multiple first units and multiple second units may further include a communication bus in addition to computing units and storage units. It should be noted that the digital circuit may further include more other types of units, and the first unit and the second unit may also include more types of units, which are not limited in this disclosure.

[0063] For example, on-chip interconnection is used to implement the sharing and switching of data resources between multiple first units and multiple second units. For example, the on-chip interconnection may include a crossbar circuit, and the crossbar circuit is used to implement the functions of the crossbar matrix as described above. Of course, in other embodiments, the on-chip interconnection may also adopt other circuit structures that can implement the functions of the crossbar circuit, which are not limited in this disclosure.

[0064] For example, in step S10, obtain the attribute information corresponding to the multiple first units and multiple second units respectively.

[0065] For example, the attribute information may be defined manually, or the attribute information may also be obtained through EDA (Electronic Design Automation) tools. Generally, each device has its own attribute information. For example, the attribute information may include the name of the device, the logical connection relationship, the device type (such as a register, RAM, etc.). Thus, the EDA tool can determine the attribute information of each unit through circuit analysis or the unit size defined manually. For example, the storage unit usually has a regular naming expression, and the storage unit can be determined according to the naming, and then its attribute information can be extracted.

[0066] For example, the attribute information defines the unit type, function, layout information, logical relationship, etc.

[0067] For example, the unit type may include storage units, computing units, communication buses, etc.

[0068] For example, the function indicates the use of the unit, such as for multiplication calculation, multiply-accumulate calculation, storage, etc. For example, in some embodiments, the unit type can be determined by the function of the unit. For example, if the function of the unit indicates that the unit is used for multiplication calculation, then the unit belongs to the computing unit; for example, if the function of the unit indicates that the unit is used for data storage, then the unit belongs to the storage unit.

[0069] For example, the layout information includes the layout positions of the devices included in the unit. For example, the layout positions can be determined manually based on experience, or the layout positions can also be obtained by extracting the layout placement information from an EDA tool.

[0070] For example, the logical relationship includes the logical connection relationships of the unit. For example, the corresponding input registers, output registers, etc. of the unit. For example, the logical relationship can also include other units that share resources with the unit. For example, such logical relationships can be obtained from the front-end netlist.

[0071] Of course, the attribute information can also include more content. The specific forms of the unit type, function, layout information, and logical relationship can be specifically set according to the actual needs of the circuit, and the present disclosure does not limit this.

[0072] In step S20, according to the attribute information corresponding to the multiple first units and the multiple second units respectively, calculate the weight centers corresponding to the multiple first units and the multiple second units respectively.

[0073] Figure 3 It is a schematic flowchart of step S20 in a layout planning method for a digital circuit provided by at least one embodiment of the present disclosure. As Figure 3 shown, step S20 at least includes steps S201 - S203.

[0074] In step S201, according to the attribute information corresponding to the multiple first units respectively, calculate the multiple first weight centers corresponding one by one to the multiple first units.

[0075] In step S202, according to the attribute information corresponding to the multiple second units respectively, calculate the multiple second weight centers corresponding one by one to the multiple second units.

[0076] In step S203, determine the global weight center according to the multiple first weight centers and the multiple second weight centers.

[0077] For example, the weight centers corresponding to the multiple first units and the multiple second units respectively include the multiple first weight centers and the multiple second weight centers.

[0078] It should be noted that in the present disclosure, the first weight center represents the weight center corresponding to the first unit, and the second weight center represents the weight center corresponding to the second unit.

[0079] For example, taking the first unit as an example, specifically illustrate the specific calculation process of the first weight center.

[0080] For example, the attribute information may at least include layout information, logical relationship, and unit type. For the content of the layout information, logical relationship, and unit type, reference may be made to the relevant descriptions in step S10.

[0081] For example, if the unit type in the attribute information corresponding to the first unit indicates that the first unit is a computing unit, step S201 may include: determining the input register and output register corresponding to the first unit according to the logical relationship in the attribute information corresponding to the first unit; determining all the combinational logic devices between the input register and the output register. For example, the input register and the output register may be used as the starting point and the ending point of a timing path, and this timing path may be extracted to obtain all the combinational logic devices between the input register and the output register; determining the position coordinates of all the combinational logic devices according to the layout information in the attribute information corresponding to the first unit; calculating the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices.

[0082] For example, calculating the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices may include: calculating the average value or weighted average value of the position coordinates of all the combinational logic devices, and using this average value or weighted average value as the first weight center corresponding to the first unit.

[0083] For example, the attribute information may at least include layout information and unit type. In this case, the first weight centers corresponding to the storage unit and the communication bus can be calculated according to the layout information and the unit type.

[0084] If the unit type in the attribute information corresponding to the first unit indicates that the first unit is a storage unit or a communication bus, step S201 may include: determining the position coordinates of multiple devices included in the first unit according to the layout information in the attribute information corresponding to the first unit; calculating the average value or weighted average value of the position coordinates of the multiple devices, and using this average value or weighted average value as the first weight center corresponding to the first unit.

[0085] Perform the above operations for each of the multiple first units, and calculate the first weight center corresponding to each first unit respectively according to the different unit types of the first units, thereby obtaining multiple first weight centers corresponding to the multiple first units respectively.

[0086] It should be noted that in the present disclosure, the first weight center represents the weight center corresponding to the first unit, and the second weight center represents the weight center corresponding to the second unit. For example, the calculation process of the second weight center corresponding to the second unit is exactly the same as that of the first weight center corresponding to the first unit. Therefore, for the specific content of step S202, reference may be made to the relevant descriptions of S201 above, and the repeated parts will not be elaborated.

[0087] For example, step S203 may include: calculating the average value or weighted average value of a plurality of first weight centers and a plurality of second weight centers, and using the average value or the weighted average value as the global weight center.

[0088] Here, the global weight center represents the most essential center of a plurality of first units and a plurality of second units that need to perform resource sharing and switching.

[0089] Figure 4 Schematic diagram of the weight center of the digital circuit provided by an embodiment of the present disclosure.

[0090] As Figure 4 shown, 101 represents a digital circuit (design), the solid rectangular frame 103 represents a storage unit, the dashed rectangular frame 102 represents a calculation unit, and the thick long bar frame 104 in the middle represents a communication bus. As Figure 4 shown, the digital circuit 101 includes 8 storage units 103, 8 calculation units 102 (for example, Figure 4 the calculation units 102_1, 102_2, and 102_3 marked in the figure), and a communication bus 104. It should be noted that Figure 4 the digital circuit shown is only a schematic diagram, and the digital circuit may also include more calculation units, storage units, communication buses, etc., and the arrangement form can also be set according to the circuit requirements, and the present disclosure does not limit this.

[0091] As Figure 4 shown, the "x" in each storage unit, calculation unit, and communication bus represents the weight center corresponding to the unit. For example, for the storage unit 103, 201 represents the weight center corresponding to it; for the calculation unit 102_1, 202 represents the weight center corresponding to it; for the calculation unit 102_2, 204 represents the weight center corresponding to it; for the communication bus, 203 represents the weight center corresponding to it. Regarding the weight center and its specific calculation method, reference can be made to the relevant descriptions in steps S201 and S202, which will not be elaborated here.

[0092] As Figure 4 shown, 205 (GX) represents the global weight center. Regarding the specific calculation method of the global weight center, reference can be made to the relevant description in step S203, and the repeated parts will not be elaborated.

[0093] As Figure 4 shown, 301 indicates that there is a connection relationship between the storage unit 103 and the calculation unit 102_1, and resource sharing and exchange are required. For example, at this time, the storage unit 103 can be the first unit, the calculation unit 102_1 can be the second unit, or the storage unit 103 can be the second unit, and the calculation unit 102_1 can be the first unit.

[0094] 302 indicates that there is a connection relationship between the storage unit 103 and the communication bus 104, and resource sharing and exchange are required. For example, the data resources of the storage unit 103 can be broadcast to 8 computing units 102 through the communication bus 104. For example, at this time, the storage unit 103 can be the first unit, and the communication bus 104 can be the second unit, or the storage unit 103 can be the second unit, and the communication bus 104 can be the first unit.

[0095] 303 indicates that there is a connection relationship between the computing unit 102_1 and the computing unit 102_2, and resource sharing and exchange are required.

[0096] 304 indicates that there is a connection relationship between the computing unit 102_1 and the computing unit 102_3, and resource sharing and exchange are required.

[0097] It should be noted that Figure 4 only the connection relationships existing between some units are shown. In fact, such connection relationships exist between more units in the digital circuit to achieve resource sharing and switching between multiple units.

[0098] After obtaining the weight centers corresponding to each unit and the global weight center, the layout planning of the digital circuit can be carried out based on the first weight center, the second weight center, and the global weight center to obtain the layout planning result.

[0099] For example, in step S30, according to the weight centers corresponding to multiple first units and multiple second units respectively, the layout planning of the digital circuit is carried out to obtain the layout planning result corresponding to the digital circuit.

[0100] For example, the on-chip interconnection includes a crossbar switch circuit, and the crossbar switch circuit is configured to perform resource sharing and switching between multiple first units and multiple second units. For example, the function of the crossbar switch circuit can refer to the related description of CrossBar as described above. For example, the crossbar switch circuit can be composed of devices such as multiplexers, and the present disclosure does not limit the specific implementation manner of the crossbar switch circuit.

[0101] For example, in some embodiments, the crossbar switch circuit is in the "fully cross" mode, and the crossbar switch circuit is configured to enable a connection relationship between multiple first units and multiple second units pairwise, and to switch the conduction states between multiple first units and multiple second units in real time. At this time, the circuit structure of the crossbar switch circuit is the most complex, and there needs to be a logical (physical) connection relationship between any two first units and second units, and the conduction states between multiple first units and multiple second units are switched in real time through a controller to achieve real-time data sharing and exchange between any number of first units and second units.

[0102] Of course, in some other embodiments, the crossbar circuit may not be in the "fully cross-connected" mode. For example, in this case, it is not necessary for there to be a connection relationship between every pair of multiple first units and multiple second units. For example, a certain first unit only has a connection relationship with some of the second units. At this time, the circuit structure of the crossbar circuit is relatively simple compared to the "fully cross-connected" mode, but the layout planning method of the digital circuit provided by at least one embodiment of the present disclosure can still be used.

[0103] For example, step S30 may include: using multiple first weight centers as the initial positions of multiple first units respectively, using multiple second weight centers as the initial positions of multiple second units respectively, using the global weight center as the initial position of the crossbar circuit, and performing layout planning on the digital circuit to obtain a layout planning result.

[0104] For example, layout planning may include physical implementation processes such as backend synthesis, floorplan, and route. The layout planning result may include the circuit after routing, or the layout planning result may also include the circuit after layout and routing optimization. For example, layout and routing optimization may include timing optimization, area optimization, power consumption optimization, etc.

[0105] Since the global weight center is the most essential center for multiple first units and multiple second units that need to share and exchange resources, using the global weight center as the initial position of the crossbar circuit provides a relatively accurate initial position reference close to the actual layout of the circuit for the layout planning process. Moreover, performing layout planning on each circuit device in units of cells provides the logical relationship and position relationship between circuit devices for the layout planning, reduces the randomness of the layout and routing process, makes the obtained layout planning result more logical, the routing pattern more regular, and overall improves the PPA of the circuit.

[0106] For example, taking multiple first weight centers as the initial positions of multiple first units respectively, taking multiple second weight centers as the initial positions of multiple second units respectively, and taking the global weight center as the initial position of the cross-switch circuit, performing layout planning on the digital circuit to obtain a layout planning result may include: taking multiple first weight centers as the initial positions of multiple first units respectively, taking multiple second weight centers as the initial positions of multiple second units respectively, taking the global weight center as the initial position of the cross-switch circuit, performing placement and routing on the digital circuit to obtain an initial layout result; performing an optimization iteration process based on the initial layout result to obtain a layout optimization result; wherein, the optimization iteration process includes: according to the source layout result, calculating the transmission power consumption of multiple groups of interconnection lines between multiple first units and multiple second units, wherein the source layout result includes the initial layout result, and each group of interconnection lines is used to connect a first unit and a second unit; according to the transmission power consumption of multiple groups of interconnection lines, performing placement and routing optimization processing on the source layout result to obtain a layout optimization result; in response to the layout optimization result meeting a predetermined condition, stopping the execution of the optimization iteration process, and taking the layout optimization result as the layout planning result, in response to the layout optimization result not meeting the predetermined condition, taking the layout optimization result as the source layout result, and continuing to execute the optimization iteration process.

[0107] For example, after obtaining the initial layout result, calculating the transmission power consumption of multiple groups of interconnection lines in the initial layout result; then, performing placement and routing optimization processing on the initial layout result according to the transmission power consumption of multiple groups of interconnection lines to obtain a layout optimization result. Here, the specific placement and routing optimization algorithm can adopt any feasible optimization algorithm, and the present disclosure does not limit this; then, if the layout optimization result meets the predetermined condition, at this time, stop executing the optimization iteration process, and take the layout optimization result as the layout planning result. For example, meeting the predetermined condition may include that the critical path delay of the layout optimization result meets minimization, the chip is as dense as possible, the power consumption meets minimization, or the crosstalk meets minimization, etc. The predetermined condition can be set according to actual needs by itself, and the present disclosure does not limit this; if the layout optimization result does not meet the predetermined condition, calculate the transmission power consumption of multiple groups of interconnection lines in the layout optimization result; then, perform placement and routing optimization processing on the layout optimization result according to the transmission power consumption of multiple groups of interconnection lines to obtain an updated layout optimization result, and repeat the above process until a layout optimization result that meets the conditions is obtained, and take it as the layout planning result of the digital circuit.

[0108] For example, during the placement and routing process, according to the multiple first weight centers, multiple second weight centers, and the global weight center calculated in steps S201 - S203, the positional relationship between each first unit and each second unit can be obtained, and accordingly, the corresponding metal layer can be selected distributively.

[0109] For example, when the distance between the target first unit and the target second unit with a connection relationship is relatively far, it can be considered that the target first unit and the target second unit belong to the "far-end" situation. At this time, the interconnection line between the target first unit and the target second unit can use the wiring resources in the upper metal layer with a smaller resistance. For example, when the distance between the target first unit and the target second unit with a connection relationship is relatively close, it can be considered that the target first unit and the target second unit belong to the "near-end" situation. At this time, the interconnection line between the target first unit and the target second unit can use the wiring resources in the lower metal layer with a larger resistance.

[0110] For example, taking multiple first weight centers as the initial positions of multiple first units respectively, taking multiple second weight centers as the initial positions of multiple second units respectively, and taking the global weight center as the initial position of the cross-switch circuit, performing layout and wiring on the digital circuit to obtain the initial layout result, which may include: for the target first unit and the target second unit connected by a group of interconnection lines: calculating the Manhattan distance between the target first unit and the target second unit; determining the metal layer where the group of interconnection lines is located according to the Manhattan distance.

[0111] For example, according to different processes of the integrated circuit, the digital circuit includes multiple metal layers, and the multiple metal layers include a first group of metal layers and a second group of metal layers. For example, the first group of metal layers includes the upper metal layers in the multiple metal layers. For example, the upper metal layers include the top layer or one or more metal layers close to the top layer. The second group of metal layers includes the lower metal layers in the multiple metal layers. For example, the lower metal layers include the bottom layer far from the top layer or one or more metal layers close to the bottom layer.

[0112] For example, determining the metal layer where a group of interconnection lines is located according to the Manhattan distance may include: in response to the Manhattan distance being greater than a preset threshold, determining that the group of interconnection lines is located in a metal layer in the first group of metal layers; in response to the Manhattan distance being less than or equal to the preset threshold, determining that the group of interconnection lines is located in a metal layer in the second group of metal layers; wherein, the resistance of at least one metal layer included in the first group of metal layers is less than the resistance of at least one metal layer included in the second group of metal layers.

[0113] For example, for Figure 4Schematic diagram of the digital circuit shown. When the Manhattan distance between the storage unit 103 and the computing unit 102_1 is less than a preset threshold, it can be determined that the interconnecting line between the storage unit 103 and the computing unit 102_1 selects the routing resources in one metal layer of the second group of metal layers. For example, a metal layer with a larger remaining amount of routing resources can be selected from the second group of metal layers for interconnection; when the Manhattan distance between the computing unit 102_1 and the computing unit 102_2 is less than a preset threshold, it can be determined that the interconnecting line between the computing unit 102_1 and the computing unit 102_2 selects the routing resources in one metal layer of the second group of metal layers; when the Manhattan distance between the computing unit 102_1 and the computing unit 102_3 is greater than a preset threshold, it can be determined that the interconnecting line between the computing unit 102_1 and the computing unit 102_3 selects the routing resources in one metal layer of the first group of metal layers; the communication bus 104 is a remote communication bus, and it can be determined that the communication bus 104 selects the routing resources in one metal layer of the first group of metal layers.

[0114] Generally speaking, the resistance of the upper metal layer is relatively small, and the resistance of the lower metal layer is relatively large. However, the routing resources of the top layer are limited. The layout planning method of the digital circuit provided by at least one embodiment of the present disclosure reasonably selects the corresponding routing resources according to the distance between the units. For example, for two units with a relatively long distance, the upper metal layer with a lower resistance is preferentially selected for interconnection. For example, for two units with a relatively short distance, the lower metal layer with a larger resistance is preferentially selected for interconnection. For example, for the communication bus, the upper metal layer with a smaller resistance is preferentially selected for implementation. This effectively solves the problem of congestion in the central area, greatly reduces the probability of the occurrence of the situation of insufficient resources in the central area, reasonably allocates the top layer routing resources and the bottom layer routing resources, reduces the resistance of the interconnecting line as a whole, and makes the power consumption overhead and performance of the entire circuit optimal.

[0115] Moreover, since the congestion problem in the central area is alleviated, the layout planning method of the digital circuit provided by at least one embodiment of the present disclosure does not need to expand the circuit area to reduce the density between the devices, thereby further reducing the area overhead of the devices and further improving the PPA of the circuit as a whole.

[0116] For example, according to the source layout result, calculating the transmission power consumption of multiple groups of interconnecting lines between multiple first units and multiple second units may include: determining multiple groups of interconnecting lines according to the source layout result; determining the metal layer and length where each group of interconnecting lines is located according to the source layout result; calculating the coupling capacitance of each group of interconnecting lines according to the metal layer and length where each group of interconnecting lines is located; calculating the transmission power consumption of each group of interconnecting lines according to the coupling capacitance of each group of interconnecting lines.

[0117] The layout planning method of the digital circuit provided by at least one embodiment of the present disclosure focuses on the logical interconnection and physical distance between all resources, and establishes a transmission power consumption estimation model based on the positional relationship between units. Thereby, reference information of the transmission power consumption can be provided during the optimization iteration process, so that the routing optimization, such as power consumption optimization, is no longer limited to calculating the power consumption, but can also perform targeted optimization for the transmission power consumption. The PPA of the obtained layout planning result is better, that is, the power consumption is lower, the performance is higher, and the area is smaller.

[0118] In addition, in some other embodiments, in addition to providing the transmission power consumption of multiple groups of interconnecting lines, the delay of multiple groups of interconnecting lines can also be provided for layout and routing optimization.

[0119] For example, the optimization iteration process further includes: calculating the delay of multiple groups of interconnecting lines according to the source layout result; performing layout and routing optimization processing on the source layout result according to the transmission power consumption of multiple groups of interconnecting lines to obtain a layout optimization result, including: performing layout and routing optimization processing on the source layout result according to the transmission power consumption of multiple groups of interconnecting lines and the delay of multiple groups of interconnecting lines to obtain a layout optimization result.

[0120] Thereby, the layout planning method provided by at least one embodiment of the present disclosure can further perform targeted optimization for the transmission power consumption impact and timing impact brought by the interconnecting lines, so as to further improve the PPA of the layout planning result and optimize the timing of the interconnecting lines.

[0121] For example, during the optimization iteration process, when it is found that the cross-switch circuit is located at the global weight center, the routing resources near the global weight center are tense or insufficient, and a layout planning result that meets the predetermined conditions cannot be obtained. At this time, the cross-switch circuit can be implemented in a distributed manner.

[0122] For example, the cross-switch circuit includes multiple controllers, and the multiple controllers are used to switch the conduction state between multiple first units and multiple second units according to corresponding control signals. In the layout optimization result, the cross-switch circuit is a distributed circuit, and the multiple controllers are distributed to multiple first units or multiple second units. For example, the controller can be implemented in the form of a multiplexer. Of course, the controller can also be implemented in the form of a control register. The present disclosure does not limit this.

[0123] Since the attribute information provides the logical relationship between the first unit and the second unit, the corresponding part of the crossbar circuit (such as the corresponding controller) can be distributed inside or near the unit for implementation. For example, the controllers of the first unit and the second unit with a connection relationship can be set at the unit port serving as the data receiving end, etc. Of course, the specific implementation of this distributed method may vary according to different optimization algorithms, different circuit structures, and different circuit performances. However, since the present disclosure can provide the logical relationship between the first unit and the second unit, the implementation of this distributed crossbar circuit can be achieved, and finally a layout planning result with neater wiring and more balanced distribution of routing resources can be obtained.

[0124] Figure 5 It is a schematic diagram of the layout planning result provided by an embodiment of the present disclosure.

[0125] For example, as Figure 5 shown, the digital circuit includes Q computing units, P storage units, and a communication bus. For example, the Q computing units are respectively computing unit 1, computing unit 2,..., computing unit k, computing unit k + 1,..., computing unit Q, and the P storage units are respectively storage unit 1, storage unit 2,..., storage unit i, storage unit i + 1,..., storage unit P, where i, k, P, and Q are all positive integers.

[0126] For example, in the layout planning result obtained based on steps S10 - S30, the crossbar circuit is in a distributed state, rather than being located in the central area of the digital circuit as Figure 1C shown.

[0127] For example, taking the interconnecting line between computing unit 1 and storage unit 1 as an example, during the optimization iteration process, it is found that the routing result obtained by setting the corresponding controllers of computing unit 1 and storage unit 1 at the port of storage unit 1 and / or computing unit 1 is better. Therefore, the corresponding parts of the crossbar circuit related to computing unit 1 and storage unit 1 can be distributed into computing unit 1 and storage unit 1.

[0128] Compared with Figure 1C shown, Figure 5 the data sharing and exchange between storage unit 1 and computing unit 1 do not need to pass through the crossbar circuit located in the central area, which greatly reduces the transmission length of the interconnecting line, reduces the transmission power consumption, optimizes the timing impact brought by the interconnecting line, and alleviates the burden of routing resources in the central area, effectively solving the problems of congestion in the central area, shortage or insufficiency of routing resources, and is a win-win solution for the crossbar circuit with complex connection relationships.

[0129] For example, in some embodiments, there may still be room for optimizing the resources of the layout planning result obtained according to the above process. For example, some devices in the crossbar switch circuit can be cloned to optimize the common path, etc.

[0130] For example, the layout planning method provided by at least one embodiment of the present disclosure may further include: determining the positions of at least one device included in the crossbar switch circuit according to the layout planning result; performing resource optimization processing on the digital circuit according to the positions of the at least one device, where the resource optimization processing includes common path optimization processing.

[0131] For example, the at least one device here may represent the devices used to form multiple controllers. For example, the at least one device may include multiplexers, registers, etc.

[0132] Of course, according to actual needs, other resource optimization processing can also be performed on the digital circuit according to the positions of the devices in the provided crossbar switch circuit to further obtain a layout planning result with better PPA.

[0133] For example, in some other embodiments, step S30 may include: using the multiple first weight centers as the initial positions of the multiple first units respectively, and using the multiple second weight centers as the initial positions of the multiple second units respectively, and performing layout planning on the digital circuit to obtain a layout planning result.

[0134] That is, at this time, the global weight center may not be calculated, and initial position references are provided for the first unit and the second unit. The specific process of layout planning at this time is the same as the above content. For example, the layout planning also includes transmission power consumption optimization, reasonably selecting corresponding routing resources according to the distance between units, etc., which will not be elaborated here. At this time, the logical relationship and position relationship between the units of the digital circuit can also be provided to obtain a layout planning result with better PPA.

[0135] Corresponding to the above layout planning method of the digital circuit, at least one embodiment of the present disclosure further provides a layout planning device for a digital circuit. Figure 6A It is a schematic block diagram of a layout planning device for a digital circuit provided by at least one embodiment of the present disclosure.

[0136] For example, the digital circuit includes multiple first units and multiple second units, and the multiple first units and the multiple second units are coupled through on-chip interconnection. For the specific descriptions of the first unit, the second unit, and the on-chip interconnection, reference can be made to the relevant introductions in the layout planning method of the digital circuit, which will not be elaborated here.

[0137] For example, as Figure 6A shown, the layout planning device 600 of the digital circuit includes: an acquisition unit 601, a calculation unit 602, and a planning unit 603.

[0138] An acquisition unit 601, configured to acquire attribute information corresponding to a plurality of first units and a plurality of second units respectively.

[0139] A calculation unit 602, configured to calculate weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively.

[0140] A layout planning unit 603, configured to perform layout planning on a digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively, so as to obtain a layout planning result corresponding to the digital circuit.

[0141] Figure 6B A schematic block diagram of a calculation unit 602 provided by at least one embodiment of the present disclosure.

[0142] For example, as Figure 6B shown, the calculation unit 602 includes a first calculation unit 6021, a second calculation unit 6022, and a global calculation unit 6023.

[0143] The first calculation unit 6021 is configured to calculate a plurality of first weight centers corresponding to the plurality of first units one by one according to the attribute information corresponding to the plurality of first units respectively.

[0144] The second calculation unit 6022 is configured to calculate a plurality of second weight centers corresponding to the plurality of second units one by one according to the attribute information corresponding to the plurality of second units respectively.

[0145] The global calculation unit 6023 is configured to determine a global weight center according to the plurality of first weight centers and the plurality of second weight centers.

[0146] For example, the attribute information corresponding to each first unit at least includes layout information, logical relationship, and unit type. When the first calculation unit 6021 executes calculating a plurality of first weight centers corresponding to the plurality of first units one by one according to the attribute information corresponding to the plurality of first units respectively, it includes performing the following operations: for each first unit in the plurality of first units: in response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a calculation unit, determining an input register and an output register corresponding to the first unit according to the logical relationship in the attribute information corresponding to the first unit; determining all combinational logic devices between the input register and the output register; determining the position coordinates of all combinational logic devices according to the layout information in the attribute information corresponding to the first unit; calculating the first weight center corresponding to the first unit according to the position coordinates of all combinational logic devices.

[0147] For example, when the first calculation unit 6021 calculates the first weight center corresponding to the first unit according to the position coordinates of all combinational logic devices, the following operations are included: calculating the average value or weighted average value of the position coordinates of all combinational logic devices, and using the average value or weighted average value as the first weight center corresponding to the first unit.

[0148] For example, when the first calculation unit 6021 calculates the multiple first weight centers corresponding to multiple first units respectively according to the attribute information corresponding to the multiple first units, the following operations are included: for each first unit among the multiple first units: in response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a storage unit or a communication bus, determining the position coordinates of the multiple devices included in the first unit according to the layout information in the attribute information corresponding to the first unit; calculating the average value or weighted average value of the position coordinates of the multiple devices, and using the average value or weighted average value as the first weight center corresponding to the first unit.

[0149] For example, when the global calculation unit 6023 determines the global weight center according to the multiple first weight centers and the multiple second weight centers, the following operations are included: calculating the average value or weighted average value of the multiple first weight centers and the multiple second weight centers, and using the average value or weighted average value as the global weight center.

[0150] For example, the on-chip interconnect includes a crossbar switch circuit configured to perform sharing and exchange of resources of multiple first units and resources of multiple second units. When the layout planning unit 603 performs layout planning on the digital circuit according to the weight centers corresponding to the multiple first units and the multiple second units respectively to obtain the layout planning result of the digital circuit, the following operations are included: using the multiple first weight centers as the initial positions of the multiple first units respectively, using the multiple second weight centers as the initial positions of the multiple second units respectively, using the global weight center as the initial position of the crossbar switch circuit, and performing layout planning on the digital circuit to obtain the layout planning result.

[0151] For example, the layout planning unit 603 includes an initial layout planning subunit and an iterative optimization subunit.

[0152] For example, the initial layout planning subunit is configured to use the multiple first weight centers as the initial positions of the multiple first units respectively, use the multiple second weight centers as the initial positions of the multiple second units respectively, use the global weight center as the initial position of the crossbar switch circuit, and perform placement and routing on the digital circuit to obtain the initial layout result.

[0153] For example, the iterative optimization subunit is configured to perform an optimization iteration process based on the initial layout result to obtain a layout optimization result; wherein, the optimization iteration process includes: calculating the transmission power consumption of multiple groups of interconnection lines between multiple first units and multiple second units according to the source layout result, where the source layout result includes the initial layout result, and each group of interconnection lines is used to connect a first unit and a second unit; performing layout and routing optimization processing on the source layout result according to the transmission power consumption of multiple groups of interconnection lines to obtain a layout optimization result; in response to the layout optimization result meeting a predetermined condition, stopping the execution of the optimization iteration process and using the layout optimization result as the layout planning result, and in response to the layout optimization result not meeting the predetermined condition, using the layout optimization result as the source layout result and continuing to execute the optimization iteration process.

[0154] For example, when the initial planning subunit performs layout and routing on the digital circuit to obtain the initial layout result by taking multiple first weight centers as the initial positions of multiple first units respectively, taking multiple second weight centers as the initial positions of multiple second units respectively, and taking the global weight center as the initial position of the cross-switch circuit, the following operations are included: for a target first unit and a target second unit connected by a group of interconnection lines: calculating the Manhattan distance between the target first unit and the target second unit according to the first weight center corresponding to the target first unit and the second weight center corresponding to the target second unit; determining the metal layer where a group of interconnection lines is located according to the Manhattan distance.

[0155] For example, when the initial planning subunit determines the metal layer where a group of interconnection lines is located according to the Manhattan distance, the following operations are included: in response to the Manhattan distance being greater than a preset threshold, determining that a group of interconnection lines is located in a metal layer in the first group of metal layers; in response to the Manhattan distance being less than or equal to the preset threshold, determining that a group of interconnection lines is located in a metal layer in the second group of metal layers; wherein, the resistance of at least one metal layer included in the first group of metal layers is less than the resistance of at least one metal layer included in the second group of metal layers.

[0156] For example, when the iterative optimization subunit calculates the transmission power consumption of multiple groups of interconnection lines between multiple first units and multiple second units according to the source layout result, the following operations are included: determining multiple groups of interconnection lines according to the source layout result; determining the metal layer and length where each group of interconnection lines is located according to the source layout result; calculating the coupling capacitance of each group of interconnection lines according to the metal layer and length where each group of interconnection lines is located; calculating the transmission power consumption of each group of interconnection lines according to the coupling capacitance of each group of interconnection lines.

[0157] For example, when the iterative optimization subunit performs the optimization iteration process, it also includes performing the following operations: calculating the delays of multiple groups of interconnecting lines according to the source layout result; performing placement and routing optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnecting lines to obtain a layout optimization result, including: performing placement and routing optimization processing on the source layout result according to the transmission power consumption and the delays of the multiple groups of interconnecting lines to obtain a layout optimization result.

[0158] For example, the crossbar switch circuit is configured such that there is a connection relationship between each pair of the multiple first units and the multiple second units, and the conduction state between the multiple first units and the multiple second units is switched in real time.

[0159] For example, the crossbar switch circuit includes multiple controllers, and the multiple controllers are used to switch the conduction state between the multiple first units and the multiple second units according to corresponding control signals. In the layout optimization result, the crossbar switch circuit is a distributed circuit, and the multiple controllers are distributed to the multiple first units or the multiple second units.

[0160] For example, in some embodiments, the layout planning device 600 of the digital circuit may further include a resource optimization unit ( Figure 6A not shown).

[0161] For example, the resource optimization unit is configured to determine the positions of at least one device included in the crossbar switch circuit according to the layout planning result; perform resource optimization processing on the digital circuit according to the positions of the at least one device, where the resource optimization processing includes common path optimization processing.

[0162] For example, the acquisition unit 601, the calculation unit 602, and the planning unit 603 include codes and programs stored in the memory; the processor can execute the codes and programs to implement some or all of the functions of the acquisition unit 601, the calculation unit 602, and the planning unit 603 as described above. For example, the acquisition unit 601, the calculation unit 602, and the planning unit 603 can be dedicated hardware devices for implementing some or all of the functions of the acquisition unit 601, the calculation unit 602, and the planning unit 603 as described above. For example, the acquisition unit 601, the calculation unit 602, and the planning unit 603 can be a circuit board or a combination of multiple circuit boards for implementing the functions as described above. In the embodiments of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0163] It should be noted that the acquisition unit 601 is used to implement Figure 2 the step S10 shown, and the calculation unit 602 is used to implement Figure 2Step S20 shown above, the planning unit 603 is used to implement Figure 2 Step S30 shown above. Therefore, the specific description of the acquisition unit 601 can refer to the relevant description of step S10 in the embodiment of the above-mentioned layout planning method for digital circuits Figure 2 shown above. The specific description of the calculation unit 602 can refer to the relevant description of step S20 in the embodiment of the above-mentioned layout planning method for digital circuits Figure 2 shown above. The specific description of the planning unit 603 can refer to the relevant description of step S30 in the embodiment of the above-mentioned layout planning method for digital circuits Figure 2 shown above.

[0164] In addition, the layout planning device for digital circuits can achieve technical effects similar to those of the aforementioned layout planning method for digital circuits, which will not be elaborated here.

[0165] At least one embodiment of the present disclosure further provides an electronic device, Figure 7 which is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.

[0166] For example, as Figure 7 shown above, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004. Components such as the processor 1001, the communication interface 1002, and the memory 1003 can also communicate through a network connection. The type and function of the network are not limited in the present disclosure.

[0167] For example, the memory 1003 is used to non-transiently store computer-executable instructions. When the processor 1001 is used to run the computer-executable instructions, the computer-executable instructions, when run by the processor 1001, implement the layout planning method for digital circuits according to any one of the above embodiments. For the specific implementation and related explanatory content of each step of the layout planning method for digital circuits, reference can be made to the embodiments of the layout planning method for digital circuits above, which will not be elaborated here.

[0168] For example, the implementation manner in which the processor 1001 executes the program stored on the memory 1003 to implement the layout planning method for digital circuits is the same as the implementation manner mentioned in the embodiment part of the aforementioned layout planning method for digital circuits, which will not be elaborated here either.

[0169] For example, the communication bus 1004 can be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. This communication bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity in illustration, only a thick line is used in the figure to represent it, but it does not mean that there is only one bus or one type of bus.

[0170] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0171] For example, the processor 1001 can control other components in the electronic device to perform desired functions. The processor 1001 can be a Central Processing Unit (CPU), a Network Processor (NP), etc., and can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The Central Processing Unit (CPU) can be of the X86 or ARM architecture, etc.

[0172] For example, the memory 1003 can include any combination of one or more computer program products, and the computer program products can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM) and / or cache memory, etc. Non-volatile memory can include, for example, Read Only Memory (ROM), hard disk, Erasable Programmable Read Only Memory (EPROM), Portable Compact Disc Read Only Memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions can be stored on the computer-readable storage media, and the processor 1001 can run the computer-executable instructions to implement various functions of the electronic device. Various application programs and various data can also be stored in the storage media.

[0173] For example, for a detailed description of the process of the electronic device performing the layout planning of digital circuits, reference can be made to the relevant descriptions in the embodiments of the method for layout planning of digital circuits, and repeated parts will not be elaborated here.

[0174] Figure 8 Schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as Figure 8 shown, one or more computer-executable instructions 1101 can be non-temporarily stored on the storage medium 1100. For example, when the computer-executable instructions 1101 are executed by the processor, one or more steps in the method for layout planning of digital circuits described above can be executed.

[0175] For example, the storage medium 1100 can be applied to the above-mentioned electronic device and / or the layout planning device 600 of the digital circuit. For example, the storage medium 1100 can include the memory 1003 in the electronic device.

[0176] For example, the description of the storage medium 1100 can refer to the description of the memory in the embodiments of the electronic device, and the repeated parts will not be described again.

[0177] For the present disclosure, the following points need to be noted:

[0178] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0179] (2) For clarity, in the drawings used to describe the embodiments of the present invention, the thickness and dimensions of layers or structures are enlarged. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or there can be intermediate elements.

[0180] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0181] The above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A layout planning method for a digital circuit, wherein, The digital circuit includes a plurality of first units and a plurality of second units, and the plurality of first units and the plurality of second units are coupled by on-chip interconnection. The layout planning method includes: Obtaining the attribute information corresponding to the plurality of first units and the plurality of second units respectively; Calculating the weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively; Performing layout planning on the digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively to obtain a layout planning result corresponding to the digital circuit; Wherein, the calculating the weight centers corresponding to the plurality of first units and the plurality of second units respectively according to the attribute information corresponding to the plurality of first units and the plurality of second units respectively includes: Calculating a plurality of first weight centers corresponding one by one to the plurality of first units according to the attribute information corresponding to the plurality of first units respectively; Calculating a plurality of second weight centers corresponding one by one to the plurality of second units according to the attribute information corresponding to the plurality of second units respectively; Determining a global weight center according to the plurality of first weight centers and the plurality of second weight centers; Wherein, the weight centers corresponding to the plurality of first units and the plurality of second units respectively include the plurality of first weight centers and the plurality of second weight centers; Wherein, the on-chip interconnection includes a crossbar switch circuit, and the crossbar switch circuit is configured to perform sharing and exchange of resources of the plurality of first units and resources of the plurality of second units. The performing layout planning on the digital circuit according to the weight centers corresponding to the plurality of first units and the plurality of second units respectively to obtain a layout planning result corresponding to the digital circuit includes: Taking the plurality of first weight centers as the initial positions of the plurality of first units respectively, taking the plurality of second weight centers as the initial positions of the plurality of second units respectively, and taking the global weight center as the initial position of the crossbar switch circuit, and performing placement and routing on the digital circuit to obtain an initial layout result; Performing optimization iteration processing based on the initial layout result to obtain a layout optimization result; Wherein, the optimization iteration processing includes: Calculating the transmission power consumption of multiple groups of interconnection lines between the plurality of first units and the plurality of second units according to a source layout result, wherein the source layout result includes the initial layout result, and each group of interconnection lines is used to connect a first unit and a second unit; Performing placement and routing optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnection lines to obtain the layout optimization result; In response to the layout optimization result meeting a predetermined condition, stopping the execution of the optimization iteration processing, and taking the layout optimization result as the layout planning result. In response to the layout optimization result not meeting the predetermined condition, taking the layout optimization result as the source layout result, and continuing to execute the optimization iteration processing.

2. The layout planning method according to claim 1, wherein, The attribute information corresponding to each first unit includes at least layout information, logical relationship, and unit type. Calculating a plurality of first weight centers corresponding one-to-one to the plurality of first units according to the attribute information corresponding to the plurality of first units respectively, includes: For each of the plurality of first units: In response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a calculation unit, Determine the input register and the output register corresponding to the first unit according to the logical relationship in the attribute information corresponding to the first unit; Determine all combinational logic devices between the input register and the output register; Determine the position coordinates of all the combinational logic devices according to the layout information in the attribute information corresponding to the first unit; Calculate the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices.

3. The layout planning method according to claim 2, wherein, Calculating the first weight center corresponding to the first unit according to the position coordinates of all the combinational logic devices, includes: Calculating the average value or weighted average value of the position coordinates of all the combinational logic devices, and taking the average value or the weighted average value as the first weight center corresponding to the first unit.

4. The layout planning method according to claim 1, wherein, The attribute information corresponding to each first unit includes at least layout information and unit type, Calculating a plurality of first weight centers corresponding one-to-one to the plurality of first units according to the attribute information corresponding to the plurality of first units respectively, includes: For each of the plurality of first units: In response to the unit type in the attribute information corresponding to the first unit indicating that the first unit is a storage unit or a communication bus, Determine the position coordinates of a plurality of devices included in the first unit according to the layout information in the attribute information corresponding to the first unit; Calculate the average value or weighted average value of the position coordinates of the plurality of devices, and take the average value or the weighted average value as the first weight center corresponding to the first unit.

5. The layout planning method according to claim 1, wherein, Determining a global weight center according to the plurality of first weight centers and the plurality of second weight centers, includes: Calculating the average value or weighted average value of the plurality of first weight centers and the plurality of second weight centers, and taking the average value or the weighted average value as the global weight center.

6. The layout planning method according to claim 1, wherein, Taking the plurality of first weight centers as the initial positions of the plurality of first units respectively, taking the plurality of second weight centers as the initial positions of the plurality of second units respectively, and taking the global weight center as the initial position of the cross-switch circuit, and performing layout and wiring on the digital circuit to obtain an initial layout result, includes: For a target first unit and a target second unit connected by a group of interconnecting wires: Calculate the Manhattan distance between the target first unit and the target second unit according to the first weight center corresponding to the target first unit and the second weight center corresponding to the target second unit; Determine the metal layer where the group of interconnecting wires is located according to the Manhattan distance.

7. The layout planning method according to claim 6, wherein The digital circuit includes multiple metal layers, and the multiple metal layers include a first group of metal layers and a second group of metal layers, Determining the metal layer where the group of interconnecting wires is located according to the Manhattan distance, includes: In response to the Manhattan distance being greater than a preset threshold, determine that the set of interconnecting lines is located in one of the metal layers in the first set of metal layers; In response to the Manhattan distance being less than or equal to the preset threshold, determine that the set of interconnecting lines is located in one of the metal layers in the second set of metal layers; wherein, the resistance of at least one metal layer included in the first set of metal layers is less than the resistance of at least one metal layer included in the second set of metal layers.

8. The layout planning method according to claim 1, wherein According to the source layout result, calculate the transmission power consumption of multiple sets of interconnecting lines between the multiple first units and the multiple second units, including: According to the source layout result, determine the multiple sets of interconnecting lines; According to the source layout result, determine the metal layer and length where each set of interconnecting lines is located; According to the metal layer and length where each set of interconnecting lines is located, calculate the coupling capacitance of each set of interconnecting lines; According to the coupling capacitance of each set of interconnecting lines, calculate the transmission power consumption of each set of interconnecting lines.

9. The layout planning method according to claim 1, wherein The optimization iteration process further includes: According to the source layout result, calculate the delay of the multiple sets of interconnecting lines; According to the transmission power consumption of the multiple sets of interconnecting lines, perform layout and routing optimization processing on the source layout result to obtain the layout optimization result, including: According to the transmission power consumption of the multiple sets of interconnecting lines and the delay of the multiple sets of interconnecting lines, perform the layout and routing optimization processing on the source layout result to obtain the layout optimization result.

10. The layout planning method according to claim 1, wherein The cross-switch circuit is configured such that there is a connection relationship between the multiple first units and the multiple second units pairwise, and the conduction state between the multiple first units and the multiple second units is switched in real time.

11. The layout planning method according to claim 1, wherein, The cross-switch circuit includes multiple controllers, and the multiple controllers are used to switch the conduction state between the multiple first units and the multiple second units according to corresponding control signals. In the layout optimization result, the cross-switch circuit is a distributed circuit, and the multiple controllers are distributed to the multiple first units or the multiple second units.

12. The layout planning method according to claim 1, further including: According to the layout planning result, determine the position of at least one device included in the cross-switch circuit; According to the position of the at least one device, perform resource optimization processing on the digital circuit, wherein the resource optimization processing includes common path optimization processing.

13. A layout planning device for a digital circuit, wherein, The digital circuit includes multiple first units and multiple second units, and the multiple first units and the multiple second units are coupled through on-chip interconnects. The layout planning device includes: An acquisition unit, configured to acquire the attribute information corresponding to the multiple first units and the multiple second units respectively; A calculation unit, configured to calculate the weight centers corresponding to the multiple first units and the multiple second units respectively according to the attribute information corresponding to the multiple first units and the multiple second units respectively; A planning unit, configured to perform layout planning on the digital circuit according to the weight centers corresponding to the multiple first units and the multiple second units respectively to obtain the layout planning result corresponding to the digital circuit; wherein, the calculation unit includes a first calculation unit, a second calculation unit, and a global calculation unit. The first computing unit is configured to calculate a plurality of first weight centers corresponding to the plurality of first units one by one according to the attribute information corresponding to the plurality of first units respectively; The second computing unit is configured to calculate a plurality of second weight centers corresponding to the plurality of second units one by one according to the attribute information corresponding to the plurality of second units respectively; The global computing unit is configured to determine a global weight center according to the plurality of first weight centers and the plurality of second weight centers; Wherein, the weight centers corresponding to the plurality of first units and the plurality of second units respectively include the plurality of first weight centers and the plurality of second weight centers; Wherein, the on-chip interconnection includes a crossbar switch circuit, and the crossbar switch circuit is configured to perform sharing and exchange of resources of the plurality of first units and resources of the plurality of second units; The planning unit includes an initial planning sub-unit and an iterative optimization sub-unit; The initial planning sub-unit is configured to use the plurality of first weight centers as the initial positions of the plurality of first units respectively, use the plurality of second weight centers as the initial positions of the plurality of second units respectively, and use the global weight center as the initial position of the crossbar switch circuit, and perform layout and wiring on the digital circuit to obtain an initial layout result; The iterative optimization sub-unit is configured to perform optimization iteration processing based on the initial layout result to obtain a layout optimization result; Wherein, the optimization iteration processing includes: According to a source layout result, calculate the transmission power consumption of multiple groups of interconnection lines between the plurality of first units and the plurality of second units, wherein the source layout result includes the initial layout result, and each group of interconnection lines is used to connect a first unit and a second unit; Perform layout and wiring optimization processing on the source layout result according to the transmission power consumption of the multiple groups of interconnection lines to obtain the layout optimization result; In response to the layout optimization result meeting a predetermined condition, stop executing the optimization iteration processing, and use the layout optimization result as the layout planning result; In response to the layout optimization result not meeting the predetermined condition, use the layout optimization result as the source layout result, and continue to execute the optimization iteration processing.

14. An electronic device, comprising: A memory that stores computer-executable instructions non-transiently; A processor configured to run the computer-executable instructions; Wherein, when the computer-executable instructions are run by the processor, the layout planning method of the digital circuit according to any one of claims 1-12 is implemented.

15. A non-transitory computer-readable storage medium, wherein, The non-transient computer-readable storage medium stores computer-executable instructions; When the computer-executable instructions are executed by a processor, the layout planning method of the digital circuit according to any one of claims 1-12 is implemented.

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