An IP unit, a logic control chip, and a three-dimensional stacked chip

Abstract

The application discloses an IP unit, a logic control chip and a three-dimensional stacked chip. The IP unit comprises a first device module, a second device module and a control module. The control module is located between the first device module and the second device module and is connected with the first device module and the second device module. The IP unit further comprises a signal output end. The first device module and the second device module are used for performing signal enhancement processing on a data interaction signal output by the control module. The signal output end is used for outputting the processed data interaction signal to an external control unit. The application solves the problem of signal attenuation caused by an excessively long signal transmission line by arranging the first device module and the second device module on the two sides of the control module and performing signal enhancement processing on the data interaction signal output by the control module through the first device module and the second device module respectively.

Description

Technical Field

[0001] This application relates to the field of logic control chips, and in particular to an IP unit and a logic control chip. Background Technology

[0002] In 3D integrated circuit design, logic control chips and DRAM chips exchange data through macrocells (HB Macros). During this data exchange, numerous signal traces cross macrocell boundaries, resulting in excessively long traces. This affects signal integrity when signals cross macrocell boundaries and can easily lead to timing violations. Summary of the Invention

[0003] This application provides at least one IP unit, a logic control chip, and a three-dimensional stacked chip to solve the signal attenuation problem caused by excessively long signal transmission lines.

[0004] The first aspect of this application provides an IP unit, which includes a first device module, a second device module, and a control module. The control module is located between the first device module and the second device module and is connected to the first device module and the second device module.

[0005] The IP unit also includes a signal output terminal. The first device module and the second device module are used to perform signal enhancement processing on the data interaction signal output by the control module, and the signal output terminal is used to output the processed data interaction signal to the external control unit.

[0006] Optionally, the control module includes a first input port and a second input port, the first input port being close to the first device module, the second input port being close to the second device module, and the signal output terminal being located on the side of the second device module away from the control module;

[0007] Specifically, the first input port outputs a data interaction signal to the first device module, the first device module enhances the data interaction signal, and transmits the enhanced data interaction signal to the second device module for output through the signal output terminal. The second input port outputs a data interaction signal to the second device module, the second device module enhances the data interaction signal, and outputs it through the signal output terminal.

[0008] Optionally, the second device module has a third input port on the side closer to the control module. The first device module enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module through the third input port.

[0009] Optionally, the IP unit is provided with signal lines and shielding lines. The signal lines connect the first device module and the third input port, and the shielding lines are provided on both sides of the signal lines to enhance the anti-interference capability of the signal lines.

[0010] Optionally, the first device module includes a first standard unit and a fourth input port. The first input port is connected to the fourth input port, and the input terminal of the first standard unit is connected to the fourth input port, so that the first standard unit is connected to the control module and receives the data interaction signal output by the control module. The output terminal of the first standard unit is connected to the third input port through a signal line.

[0011] Optionally, the second device module includes a second standard unit and a fifth input port. The second input port is connected to the fifth input port, and the first input terminal of the second standard unit is connected to the fifth input terminal so that the second standard unit is connected to the control module and receives the data interaction signal output by the control module. The second input terminal of the second standard unit is connected to the third input terminal so that the first standard unit is connected to the second standard unit and receives the data interaction signal enhanced by the first device module. The output terminal of the second standard unit is connected to the signal output terminal.

[0012] Optionally, the first standard unit includes at least one of a buffer or an inverter, and the second standard unit includes at least one of a buffer or an inverter.

[0013] Optionally, the signal enhancement capability of the first device module is greater than that of the second device module.

[0014] Optionally, the distance between the first device module and the control module is equal to the distance between the second device module and the control module.

[0015] A second aspect of this application provides a logic control chip, which includes an IP unit and a control unit as described above. The signal output port of the IP unit is connected to the control unit to output data interaction signals to the control unit.

[0016] Optionally, the IP unit includes multiple signal output terminals, and the logic control chip includes multiple control units. Each signal output terminal is connected to a corresponding control unit so that the control unit receives the data interaction signal enhanced by the first device module and / or the data interaction signal enhanced by the second device module.

[0017] A third aspect of this application provides a three-dimensional stacked chip, the three-dimensional stacked chip comprising:

[0018] Memory chips;

[0019] The logic control chip and the memory chip are three-dimensionally heterogeneously integrated; the logic control chip includes IP units and control units as described above, the signal output ports of the IP units are connected to the control unit to output data interaction signals to the control unit; the control unit is used to control the data reading and writing of the memory chip.

[0020] The beneficial effects of this application are as follows: Unlike the prior art, this application solves the signal attenuation problem caused by excessively long signal transmission lines by setting a first device module and a second device module on both sides of the control module, and by using the first device module and the second device module to perform signal enhancement processing on the data interaction signal output by the control module respectively.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this application. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art three-dimensional integrated circuit;

[0024] Figure 2 yes Figure 1 A schematic diagram of the structure of a logic chip according to an embodiment;

[0025] Figure 3 This is a first structural schematic diagram of an embodiment of the IP unit of this application;

[0026] Figure 4 This is a second structural schematic diagram of an embodiment of the IP unit of this application;

[0027] Figure 5 This is a schematic diagram of the structure of an embodiment of the logic control chip of this application;

[0028] Figure 6 This is a schematic diagram of the structure of an embodiment of the three-dimensional stacked chip of this application. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solutions of this application, the IP unit, logic control chip, and three-dimensional stacked chip provided in this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It is understood that the described embodiments are merely some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0031] Please see Figure 1-2 , Figure 1 This is a schematic diagram of the structure of an embodiment of a prior art three-dimensional integrated circuit; Figure 2 yes Figure 1 A schematic diagram of the structure of a logic chip according to an embodiment.

[0032] like Figure 1 As shown, in the design of high-frequency 3D integrated circuits for 3D DRAM, to achieve data interaction between the logic control wafer and the DRAM wafer, the logic control chip design includes macrocells for 3D-IC hybrid bonding (HB) and data interaction, called Hybrid Bonding Macros, also known as HB Macros. Among them, as... Figure 1 As shown, the HB Macro is configured to correspond to the transmission interface (TM1) of the logic control wafer and the transmission interface (TM2) of the DRAM wafer, and is composed of TM1, TM2 and a Hybrid Bonding cell.

[0033] Due to limitations of the HB process, the position of the HB Macro is relatively fixed for logic control chips, and its width is all above 800um. When DRAM interacts with the control unit (Memory Controller) in the logic control chip through the HB Macro, a large number of signal traces inevitably cross the HB Macro, resulting in long traces and potential risks of signal integrity and timing violations.

[0034] like Figure 2 As shown, in the placement and routing design, to avoid placing standard cells in and around the HB Macro, placement blocking modules are added around the HB Macro, i.e. Figure 2As shown, the black squares surrounding the HBMacro disrupt the site row, preventing the placement of standard cells. The site row can specifically be the connection line between the micro controller (MC) and the macrocell, or the connection line between other functional cells and the macrocell.

[0035] Therefore, to eliminate crosstalk noise, for long signal lines (e.g., >1000um) spanning the HB Macro, it is generally not possible to directly add standard cells in the middle of the long line, i.e., above the HB Macro, to increase immunity. Current technology can only add larger buffers and inverters at the far ports of the HB Macro (i.e., the ports of the HB Macro furthest from the Memory Controller) and other IP cell ports to enhance drive capability and mitigate signal integrity issues caused by crosstalk noise.

[0036] However, the main drawbacks and risks of this method are: (1) The routing resources of this channel are relatively tight, which may introduce the risk of routing congestion; (2) The routing is usually done automatically by tools, the placement of standard units of IP unit ports is uncontrollable, the length of the traces is also uncontrollable, and the risk of crosstalk and timing violations still exists; (3) The buffers and inverters with strong driving capabilities have a large area, which is not conducive to the utilization rate of chip layout, and the placement of other logic units is limited; (4) The buffers and inverters with strong driving capabilities may also introduce the risk of setup violation of the top-level data path.

[0037] This application provides an IP unit to address the problems of excessively long lines and crosstalk noise caused by bridging macrocell signals. This IP unit can be used as a low-level sub-unit and called by the top-level module of the logic control chip. It is provided to the top-level logic control chip using the Abstraction format, making the internal layout and routing of the logic control chip more flexible and increasing design redundancy.

[0038] Please see Figure 3-4 , Figure 3 This is a first structural schematic diagram of an embodiment of the IP unit of this application. Figure 4 This is a second structural schematic diagram of an embodiment of the IP unit of this application. For example... Figure 3 and Figure 4 As shown, IP unit 1 includes a first device module 11, a second device module 12, a reserved area 13, a control module 14, and a signal output terminal 15.

[0039] In this embodiment, the first device module 11, the reserved area 13, and the second device module 12 are arranged adjacent to each other in sequence. The reserved area 13 is used to place the control module 14, so that the control module 14 is located between the first device module 11 and the second device module 12, and is connected to both the first device module 11 and the second device module 12. Optionally, in this embodiment, the distance between the first device module 11 and the control module 14 is equal to the distance between the second device module 12 and the control module 14, and the strength of the data interaction signal output by the control module 14 to the first device module 11 and the second device module 12 is consistent.

[0040] The control module 14 is the one described above. Figure 2 The macro unit is shown. Optionally, the number of control modules 14 can be single or multiple, such as one, two, four, etc.

[0041] Specifically, the sizes of the first device module 11, the reserved area 13, and the second device module 12 in this embodiment can be set according to actual needs, and the distances between the first device module 11, the second device module 12, and the control module 14 can be set according to actual needs. Figure 3 and Figure 4 This is merely an illustrative diagram and is not intended to limit the only embodiments of this application. In actual design, the first device module 11 and the second device module 12 are much smaller than the reserved area 13, so that the logic control chip equipped with IP unit 1 and control module 14 has the advantages of small size and low cost.

[0042] The first device module 11 and the second device module 12 are used to perform signal enhancement processing on the data interaction signal output by the control module 14, and the signal output terminal 15 is used to output the processed data interaction signal to the external control unit.

[0043] like Figure 3 and Figure 4 As shown, in this embodiment, the first device module 11 is disposed on the left side of IP unit 1, and the second device module 12 is disposed on the right side of IP unit 1. Optionally, in other embodiments, the first device module 11 may be disposed on the right side of IP unit 1, and the second device module 12 may be disposed on the left side of IP unit 1.

[0044] like Figure 4 As shown, the control module 14 includes a first input port 141 and a second input port 142. The first input port 141 is close to the first device module 11, and the second input port 142 is close to the second device module 12. The signal output terminal 15 is located on the side of the second device module 12 away from the control module 14.

[0045] Specifically, the first input port 141 outputs a data interaction signal to the first device module 11, the first device module 11 enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module 12 for output through the signal output terminal 15, the second input port 142 outputs a data interaction signal to the second device module 12, the second device module 12 enhances the data interaction signal and outputs it through the signal output terminal 15.

[0046] Optionally, since the transmission line of the data interaction signal output by the control module 14 through the first device module 11 is longer than the transmission line of the data interaction signal output by the control module 14 through the second device module 12, the signal enhancement capability corresponding to the first device module 11 can be set to be greater than the signal enhancement capability corresponding to the second device module 12, so as to reduce the signal attenuation of the left path and make the signal strength output by the control module 14 to the external control unit consistent.

[0047] like Figure 3 As shown, the first device module 11 includes a fourth input port 111 and a first standard unit 112. The fourth input port 111 is located on the side of the first device module 11 closer to the control module 14. The first input port 141 is connected to the fourth input port 111. The input terminal of the first standard unit 112 is connected to the fourth input port 111, so that the first standard unit 112 is connected to the control module 14 and receives data interaction signals output by the control module 14.

[0048] Optionally, the number of fourth input ports 111 can be single or multiple, and the number of first standard units 112 can be single or multiple, with each first standard unit 112 connected to at least one fourth input port 111. For example, in this embodiment, the number of fourth input ports 111 is six, and the number of first standard units 112 is four. The first first standard unit 112 is connected to two fourth input ports 111, and the second, third, and fourth first standard units 112 are each connected to one fourth input port 111.

[0049] Optionally, the first standard unit 112 includes at least one of a buffer or an inverter, wherein the buffer and inverter are standard driving units in the digital chip, which is beneficial to enhancing the driving capability of the IP unit 1 for the bridging signals of the control module 14. For example, in this embodiment, the four first standard units 112 may include two buffers and two inverters. Meanwhile, the specific locations of the buffers and inverters can be determined according to the logical function requirements. For example, the first and fourth first standard units 112 are buffers, and the second and third first standard units 112 are inverters. Optionally, in other embodiments, the first standard unit 112 may also include one buffer and three inverters, or three buffers and one inverter, or four buffers, or four inverters, etc.

[0050] The second device module 12 includes a fifth input port 121 and a second standard unit 123. The fifth input port 121 is located on the side of the second device module 12 closer to the control module 14, and the signal output terminal 15 is located on the side of the second device module 12 away from the control module 14.

[0051] The second input port 142 is connected to the fifth input port 121, and the first input terminal of the second standard unit 123 is connected to the fifth input terminal, so that the second standard unit 123 is connected to the control module 14 and receives the data interaction signal output by the control module 14.

[0052] Optionally, the number of fifth input ports 121 can be single or multiple, and the number of second standard units 123 can be single or multiple, with each second standard unit 123 connected to at least one fifth input port 121. For example, in this embodiment, the number of fifth input ports 121 is ten, and the number of second standard units 123 is four. The first second standard unit 123 is connected to three fifth input ports 121, and the second, third, and fourth second standard units 123 are respectively connected to two fourth input ports 111.

[0053] Optionally, the second standard unit 123 includes at least one of a buffer or an inverter, wherein the buffer and inverter are standard driving units in the digital chip, which is beneficial to enhancing the driving capability of the IP unit 1 for the bridging signals of the control module 14. For example, in this embodiment, the four second standard units 123 may include two buffers and two inverters. Meanwhile, the logic function needs to determine the specific locations of the buffers and inverters. For example, the first and third second standard units 123 are buffers, and the second and fourth second standard units 123 are inverters. Optionally, in other embodiments, the second standard unit 123 may also include one buffer and three inverters, or three buffers and one inverter, or four buffers, or four inverters, etc.

[0054] Furthermore, the second device module 12 is provided with a third input port 122 on the side near the control module 14. The first device module 11 enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module 12 through the third input port 122.

[0055] IP unit 1 further includes a signal line 16 and a shield line 161. The signal line 16 connects the first device module 11 and the third input port 122 to connect the first device module 11 and the second device module 12, and is used to transmit the data interaction signal processed by the first device module 11. The shield line 161 is disposed on both sides of the signal line 16 to enhance the anti-interference capability of the signal line 16. Optionally, the shield line 161 may also be disposed around the signal line 16 to further enhance the anti-interference capability of the signal line 16 and prevent signal crosstalk.

[0056] Optionally, in this embodiment, the signal line 16 is made of high-layer metal, double the line width and double the spacing, and the strong interference capability of the signal line 16 is enhanced by adding shielding lines 161 on both sides of the signal line 16.

[0057] The first input port 141 outputs a data interaction signal to the first device module 11. The first device module 11 enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module 12 for output through the signal output terminal 15. The second input port 142 outputs a data interaction signal to the second device module 12. The second device module 12 enhances the data interaction signal and outputs it through the signal output terminal 15.

[0058] The data interaction signals output by the control module 14 include cross-unit signals and short-distance signals. The first standard unit 112 receives the cross-unit signals from the data interaction signals output by the control module 14, while the second standard unit 123 receives the short-distance signals from the data interaction signals output by the control module 14.

[0059] Specifically, the fourth input port 111 is used to connect the control module 14 to the first input port 141 near the first device module 11, and the input terminal of the first standard unit 112 is connected to the fourth input port 111. The fourth input port 111 receives cross-unit signals input from the first input port 141 of the control module 14 connected to the fourth input port 111, and transmits them to the first standard unit 112.

[0060] The fifth input port 121 is used to connect the port of the control module 14 closest to the second device module 12, and also to connect the output terminal of the first standard unit 112. The input terminal of the second standard unit 123 is connected to the fifth input port 121, and the output terminal of the second standard unit 123 is connected to the signal output terminal 15. The fifth input port 121 receives short-circuit signals input from the second input port 142 of the control module 14 connected to the fifth input port 121. The third input port 122 receives cross-unit signals transmitted from the first standard unit 112 connected to the third input port 122, and transmits them to the second standard unit 123. The second standard unit 123 transmits the signals to the back-end implementation unit through the signal output terminal 15.

[0061] Optionally, in this embodiment, the back-end implementation unit is an external control unit. Optionally, in other embodiments, the back-end implementation unit may also be other top-level logic units, with signal output terminal 15 serving as a top-level data interaction port.

[0062] The fourth input port 111 is connected to the first standard unit 112, the second standard unit 123 is connected to the fifth input port 121, and the second standard unit 123 is connected to the signal output terminal 15 via internal wiring. The internal wiring can be standardized by defining non-default routing rules, specifying the wiring layer, line width and spacing, and further enhancing the anti-interference capability.

[0063] Specifically, when the control module 14 needs to interact with the control unit, the control module 14 transmits signals to the IP unit 1 through the port.

[0064] If the signal at this time is a cross-unit signal, the cross-unit signal enhances the signal driving capability through the first standard unit 112 inside IP unit 1, and is transmitted to the third input port 122 through the signal line 16 across the control module 14. It is then logically matched through the second standard unit 123 inside IP unit 1, and output to the external control unit through the signal output terminal 15.

[0065] If the signal at this time is a short-range signal, the short-range signal is directly transmitted to the external control unit through the second standard unit 123 inside IP unit 1. Since the transmission line is short, the signal integrity is less affected, and no additional processing is required for the short-range signal.

[0066] Furthermore, the size and logical functions of IP unit 1 depend entirely on the number, size, and arrangement of the bridging control modules 14. The number and layout depth of the first standard unit 112 and the second standard unit 123 are customizable and not limited by IP unit 1 itself. At the same time, port timing constraints are applied separately to ensure internal timing convergence. Specifically, the first standard unit 112 and the second standard unit 123 inside IP unit 1 are placed close together according to their logical relationships. The first standard unit 112 and the second standard unit 123 are connected to the fourth input port 111 and the fifth input port 121, respectively, thereby effectively standardizing the distribution of the first standard unit 112 and the second standard unit 123.

[0067] This application improves the signal integrity of data interaction between the control module 14 and the logic control chip by placing the control module 14 in the reserved area 13 of the IP unit 1, and optimizes the noise and crosstalk issues of cross-unit signals. At the same time, the IP unit 1 optimizes the data interaction reliability of the design itself, enhances design redundancy, improves design efficiency, and improves the implementability of the logic control chip.

[0068] Furthermore, this application achieves this by setting the first standard unit 112 and the second standard unit 123 in the first device module 11 and the second device module 12 respectively, through the back-end technology of the logic control chip, without changing the front-end design netlist, so as to ensure the consistency of the logic function of the logic control chip.

[0069] This application also provides a logic control chip; please refer to... Figure 3-4 See Figure 5 , Figure 5 This is a schematic diagram of the structure of an embodiment of the logic control chip of this application. Figure 5 As shown, the logic control chip 20 includes an IP unit 21 and a control unit 22. The signal output port of the IP unit 21 is connected to the control unit 22 to output data interaction signals to the control unit 22. The IP unit 21 is the IP unit 1 disclosed in the above embodiments, and will not be described again here.

[0070] The IP unit 21 includes multiple signal output terminals 15, and the logic control chip 20 includes multiple control units 22. Each signal output terminal 15 is connected to a corresponding control unit 22 so that the control unit 22 receives the data interaction signal enhanced by the first device module 11 and / or the data interaction signal enhanced by the second device module 12.

[0071] Specifically, the control unit 22 is connected to the signal output terminal 15 via a signal transmission line. This signal transmission line can be the top-level trace of the logic control chip 20.

[0072] Alternatively, in other embodiments, the control unit 22 may also be another top-level logic unit of the logic control chip 20.

[0073] This application also provides a three-dimensional stacked chip; please refer to... Figure 3-5 See Figure 6 , Figure 6 This is a schematic diagram of the structure of an embodiment of the three-dimensional stacked chip of this application. Figure 6 As shown, the three-dimensional stacked chip 30 includes a memory chip 31 and a logic control chip 32, which are three-dimensionally heterogeneously integrated. The logic control chip 32 is the logic control chip 20 disclosed in the above embodiments, such as the IP unit 21 and control unit 22 mentioned above, and will not be described again here.

[0074] The signal output port of IP unit 21 is connected to control unit 22 to output data interaction signals to control unit 22; control unit 22 is used to control data reading and writing of storage chip 31.

[0075] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An IP unit, characterized in that, The IP unit includes a first device module, a second device module, and a control module. The control module is located between the first device module and the second device module and is connected to both the first device module and the second device module. The IP unit further includes a signal output terminal. The first device module and the second device module are used to perform signal enhancement processing on the data interaction signal output by the control module, and the signal output terminal is used to output the processed data interaction signal to an external control unit. The control module includes a first input port and a second input port. The first input port is close to the first device module, and the second input port is close to the second device module. The signal output terminal is located on the side of the second device module away from the control module. Wherein, the first input port outputs the data interaction signal to the first device module, the first device module enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module for output through the signal output terminal, the second input port outputs the data interaction signal to the second device module, the second device module enhances the data interaction signal and outputs it through the signal output terminal; The second device module has a third input port on the side near the control module. The first device module enhances the data interaction signal and transmits the enhanced data interaction signal to the second device module through the third input port.

2. The IP unit according to claim 1, characterized in that, The IP unit is provided with signal lines and shielding lines. The signal lines connect the first device module and the third input port. The shielding lines are located on both sides of the signal lines to enhance their anti-interference capability.

3. The IP unit according to claim 2, characterized in that, The first device module includes a first standard unit and a fourth input port. The first input port is connected to the fourth input port, and the input terminal of the first standard unit is connected to the fourth input port so that the first standard unit is connected to the control module and receives the data interaction signal output by the control module. The output terminal of the first standard unit is connected to the third input port through the signal line.

4. The IP unit according to claim 3, characterized in that, The second device module includes a second standard unit and a fifth input port. The second input port is connected to the fifth input port. The first input terminal of the second standard unit is connected to the fifth input terminal so that the second standard unit is connected to the control module and receives the data interaction signal output by the control module. The second input terminal of the second standard unit is connected to the third input terminal so that the first standard unit is connected to the second standard unit and receives the data interaction signal enhanced by the first device module. The output terminal of the second standard unit is connected to the signal output terminal.

5. The IP unit according to claim 4, characterized in that, The first standard unit includes at least one of a buffer or an inverter, and the second standard unit includes at least one of a buffer or an inverter.

6. The IP unit according to claim 1, characterized in that, The signal enhancement capability of the first device module is greater than that of the second device module.

7. The IP unit according to claim 1, characterized in that, The distance between the first device module and the control module is equal to the distance between the second device module and the control module.

8. A logic control chip, characterized in that, The logic control chip includes an IP unit and a control unit as described in any one of claims 1-7, wherein the signal output port of the IP unit is connected to the control unit to output data interaction signals to the control unit.

9. The logic control chip according to claim 8, characterized in that, The IP unit includes multiple signal output terminals, and the logic control chip includes multiple control units. Each signal output terminal is connected to a corresponding control unit, so that the control unit receives the data interaction signal enhanced by the first device module and / or the data interaction signal enhanced by the second device module.

10. A three-dimensional stacked chip, characterized in that, The three-dimensional stacked chip includes: Memory chips; A logic control chip is provided, wherein the memory chip and the logic control chip are three-dimensionally heterogeneously integrated; wherein the logic control chip includes an IP unit and a control unit as described in any one of claims 1-7, the signal output port of the IP unit is connected to the control unit to output data interaction signals to the control unit; the control unit is used to control the data reading and writing of the memory chip.

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